Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply SOT 23 6

3 4

GND

SDATA

SCLK

ADC081S051

www.ti.com

SNAS309E –APRIL 2005–REVISED MARCH 2013

ADC081S051 Single Channel, 200 to 500 ksps, 8-Bit A/D Converter

Check for Samples: ADC081S051

FEATURES

DESCRIPTION

The ADC081S051 is a low-power, single channel

• Specified Over a Range of Sample Rates

CMOS 8-bit analog-to-digital converter with a high-

• 6-lead WSON and SOT-23 Packages

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC081S051 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range

sample rate range of 200 ksps to 500 ksps. The

• SPI™/QSPI™/MICROWIRE/DSP Compatible

converter is based on a successive-approximation

KEY SPECIFICATIONS

circuit.

• DNL: +0.06 / -0.045 LSB (Typ)

The output serial data is straight binary, and is

• INL: +0.06 / -0.05 LSB (Typ)

compatible with several standards, such as SPI™,

QSPI™, MICROWIRE, and many common DSP

• SNR: 49.6 dB (Typ)

serial interfaces.

• Power Consumption:

The ADC081S051 operates with a single supply that

– 3.6V Supply: 1.6 mW (Typ)

can range from +2.7V to +5.25V. Normal power

– 5.25V Supply: 8.5 mW (Typ)

consumption using a +3.6V or +5.25V supply is 1.6

mW and 8.5 mW, respectively. The power-down

APPLICATIONS

feature reduces the power consumption to as low as

2.6 µW using a +5.25V supply.

• Portable Systems

The ADC081S051 is packaged in 6-lead WSON and

• Remote Data Acquisition

SOT-23 packages. Operation over the industrial

• Instrumentation and Control Systems

temperature range of −40°C to +85°C is ensured.

Table 1. Pin-Compatible Alternatives by Resolution and Speed

(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC121S021 ADC121S051 ADC121S101

10-bit ADC101S021 ADC101S051 ADC081S101

8-bit ADC081S021 ADC081S051 ADC081S101

(1) All devices are fully pin and function compatible.

Connection Diagram

Figure 1. 6-Lead WSON or SOT-23

See NGF0006A or DBV Package

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 ADC081S051 Single Channel, 200 to 500 ksps, 8-Bit A/D Converter Check for Samples: ADC081S051 FEATURES DESCRIPTION • • • • • The ADC081S051 is a low-power, single channel CMOS 8-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC081S051 is fully specified over a sample rate range of 200 ksps to 500 ksps.
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com Block Diagram VIN T/H 8-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA PIN DESCRIPTIONS and EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 3 VIN Analog input. This signal can range from 0V to VA. DIGITAL I/O 4 SCLK 5 SDATA Digital clock input. This clock directly controls the conversion and readout processes. 6 CS Chip select. On the falling edge of CS, a conversion process begins.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) −0.3V to 6.5V Analog Supply Voltage VA −0.3V to (VA +0.3V) Voltage on Any Analog Pin to GND −0.3V to 6.
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com ADC081S051 Converter Electrical Characteristics (1) (2) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4 MHz to 10 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 15 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits (2) Units 8 Bits ±0.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 ADC081S051 Converter Electrical Characteristics(1)(2) (continued) The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4 MHz to 10 MHz, fSAMPLE = 200 ksps to 500 ksps, CL = 15 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Typical Limits (2) Units ISOURCE = 200 µA VA − 0.07 VA − 0.2 V (min) ISOURCE = 1 mA VA − 0.1 ISINK = 200 µA 0.03 0.
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com ADC081S051 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 4 MHz to 10 MHz, CL = 25 pF, fSAMPLE = 200 ksps to 500 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 Timing Diagrams IOL 200 PA 1.6 V To Output Pin CL 25 pF IOH 200 PA Figure 2. Timing Test Circuit Hold Track | CS tCS tSU tACQ tCL 1 2 3 4 12 13 14 15 16 17 Z1 Z0 DB7 3 leading zero bits 18 19 20 tQUIET tCH tH | Z2 5 tACC tEN SDATA | SCLK tDIS TRI-STATE Zero Zero 8 data bits Zero Zero 4 trailing zeroes Figure 3.
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com Specification Definitions ACQUISITION TIME is the time required to acquire the input voltage. That is, it is time required for the hold capacitor to charge up to the input voltage. Acquisition time is measured backwards from the falling edge of CS when the signal is sampled and the part moves from track to hold.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dB or dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as THD = 20 ‡ log10 A f 22 + + A f 62 A f 12 where • Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the first 5 harmonic frequencies.
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated. 10 DNL fSCLK = 4 MHz INL fSCLK = 4 MHz Figure 4. Figure 5. DNL fSCLK = 10 MHz INL fSCLK = 10 MHz Figure 6. Figure 7. DNL vs. Clock Frequency INL vs. Clock Frequency Figure 8. Figure 9.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated. Total Unadjusted Error vs. Clock Frequency SNR vs. Clock Frequency Figure 10. Figure 11. SINAD vs. Clock Frequency THD vs. Clock Frequency Figure 12. Figure 13. SFDR vs.Clock Frequency Spectral Response, VA = 5V, fSCLK = 4 MHz Figure 14. Figure 15.
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 200 ksps to 500 ksps, fSCLK = 4 MHz to 10 MHz, fIN = 100 kHz unless otherwise stated. 12 Spectral Response, VA = 5V, fSCLK = 10 MHz Power Consumption vs.Throughput, fSCLK = 10 MHz Figure 16. Figure 17.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 APPLICATIONS INFORMATION ADC081S051 OPERATION The ADC081S051 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter core. Simplified schematics of the ADC081S051 in both track and hold modes are shown in Figure 18 and Figure 19, respectively.
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com USING THE ADC081S051 The serial interface timing diagram for the ADC is shown in Figure 3. CS is chip select, which initiates conversions on the ADC and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. SDATA is the serial data out pin, where a conversion result is found as a serial data stream.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 ADC081S051 TRANSFER FUNCTION The output format of the ADC is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC is VA/256. The ideal transfer characteristic is shown in Figure 20. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of VA/512. Other code transitions occur at steps of one LSB. 111...111 111...000 | | ADC CODE 111..
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com ANALOG INPUTS An equivalent circuit of the ADC's input is shown in Figure 22. Diodes D1 and D2 provide ESD protection for the analog inputs. At no time should the analog input go beyond (VA + 300 mV) or (GND − 300 mV), as these ESD diodes will begin to conduct, which could result in erratic operation. For this reason, the ESD diodes should not be used to clamp the input signal.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 To enter shutdown mode, a conversion must be interrupted by bringing CS high anytime between the second and tenth falling edges of SCLK, as shown in Figure 23. Once CS has been brought high in this manner, the device will enter shutdown mode, the current conversion will be aborted and SDATA will enter TRI-STATE.
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ADC081S051 SNAS309E – APRIL 2005 – REVISED MARCH 2013 www.ti.com POWER SUPPLY NOISE CONSIDERATIONS The charging of any output load capacitance requires current from the power supply, VA. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC.
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ADC081S051 www.ti.com SNAS309E – APRIL 2005 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADC081S051CIMF/NOPB SOT-23 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 ADC081S051CISD/NOPB WSON NGF 6 1000 178.0 12.4 2.8 2.5 1.0 8.0 12.0 Q1 NGF 6 4500 330.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC081S051CIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 SOT-23 DBV 6 3000 210.0 185.0 35.0 WSON NGF 6 1000 210.0 185.0 35.0 WSON NGF 6 4500 367.0 367.0 35.
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MECHANICAL DATA NGF0006A www.ti.
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