Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) Supply SOT 23 6

3 4

GND

SDATA

SCLK

ADC081S021

www.ti.com

SNAS308E –APRIL 2005–REVISED MARCH 2013

ADC081S021 Single Channel, 50 to 200 ksps, 8-Bit A/D Converter

Check for Samples: ADC081S021

FEATURES

DESCRIPTION

The ADC081S021 is a low-power, single channel

• Specified Over a Range of sample Rates.

CMOS 8-bit analog-to-digital converter with a high-

• 6-lead WSON and SOT-23 Packages

speed serial interface. Unlike the conventional

• Variable Power Management

practice of specifying performance at a single sample

rate only, the ADC081S021 is fully specified over a

• Single Power Supply with 2.7V - 5.25V Range

sample rate range of 50 ksps to 200 ksps. The

• SPI™/QSPI™/MICROWIRE/DSP Compatible

converter is based upon a successive-approximation

KEY SPECIFICATIONS

circuit.

• DNL: +0.04/-0.03 LSB (typ)

The output serial data is straight binary, and is

• INL: +0.04/-0.03 LSB (typ)

compatible with several standards, such as SPI,

QSPI, MICROWIRE, and many common DSP serial

• SNR: 49.6 dB (typ)

interfaces.

• Power Consumption

The ADC081S021 operates with a single supply that

– 3.6V Supply: 1.3 mW (typ)

can range from +2.7V to +5.25V. Normal power

– 5.25V Supply: 7.7 mW (typ)

consumption using a +3.6V or +5.25V supply is 1.3

mW and 7.7 mW, respectively. The power-down

APPLICATIONS

feature reduces the power consumption to as low as

2.6 µW using a +5.25V supply.

• Portable Systems

The ADC081S021 is packaged in 6-lead WSON and

• Remote Data Acquisition

SOT-23 packages. Operation over the industrial

• Instrumentation and Control Systems

temperature range of −40°C to +85°C is ensured.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Pin-Compatible Alternatives by Resolution and Speed

(1)

Resolution Specified for Sample Rate Range of:

50 to 200 ksps 200 to 500 ksps 500 ksps to 1 Msps

12-bit ADC081S021121S021 ADC081S021121S051 ADC081S021121S101

10-bit ADC081S021101S021 ADC081S021101S051 ADC081S021101S101

8-bit ADC081S021 ADC081S021081S051 ADC081S021081S101

(1) All devices are fully pin and function compatible.

Connection Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (24 pages)

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ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 ADC081S021 Single Channel, 50 to 200 ksps, 8-Bit A/D Converter Check for Samples: ADC081S021 FEATURES DESCRIPTION • • • • • The ADC081S021 is a low-power, single channel CMOS 8-bit analog-to-digital converter with a highspeed serial interface. Unlike the conventional practice of specifying performance at a single sample rate only, the ADC081S021 is fully specified over a sample rate range of 50 ksps to 200 ksps.
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ADC081S021 SNAS308E – APRIL 2005 – REVISED MARCH 2013 www.ti.com Block Diagram VIN T/H 8-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS SDATA PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Description ANALOG I/O 3 VIN Analog input. This signal can range from 0V to VA. DIGITAL I/O 4 SCLK 5 SDATA Digital clock input. This clock directly controls the conversion and readout processes. 6 CS Chip select. On the falling edge of CS, a conversion process begins.
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ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 Operating Ratings (1) (2) −40°C ≤ TA ≤ +85°C Operating Temperature Range VA Supply Voltage +2.7V to +5.25V −0.3V to 5.25V Digital Input Pins Voltage Range (regardless of supply voltage) Analog Input Pins Voltage Range 0V to VA Clock Frequency 25 kHz to 20 MHz Sample Rate (1) (2) up to 1Msps Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
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ADC081S021 SNAS308E – APRIL 2005 – REVISED MARCH 2013 www.ti.com ADC081S021 Converter Electrical Characteristics (1) (2) The following specifications apply for VA = +2.7V to 5.25V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 15 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Parameter Conditions Typical Limits (2) 8 Bits ±0.03 ±0.3 LSB (max) Units STATIC CONVERTER CHARACTERISTICS Resolution with No Missing Codes VA = +2.
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ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 ADC081S021 Converter Electrical Characteristics(1)(2) (continued) The following specifications apply for VA = +2.7V to 5.25V, fSCLK = 1 MHz to 4 MHz, fSAMPLE = 50 ksps to 200 ksps, CL = 15 pF, unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C. Symbol Typical Limits (2) Units ISOURCE = 200 µA VA − 0.07 VA − 0.2 V (min) ISOURCE = 1 mA VA − 0.1 ISINK = 200 µA 0.03 0.
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ADC081S021 SNAS308E – APRIL 2005 – REVISED MARCH 2013 www.ti.com ADC081S021 Timing Specifications The following specifications apply for VA = +2.7V to 5.25V, GND = 0V, fSCLK = 1.0 MHz to 4.0 MHz, CL = 25 pF, fSAMPLE = 50 ksps to 200 ksps, Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C.
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ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 Hold Track | CS tCS tSU tACQ tCL 1 2 3 | SCLK 4 5 14 15 16 Z1 Z0 tH DB7 3 leading zero bits 17 18 19 20 tQUIET tCH | Z2 13 tACC tEN SDATA 12 tDIS TRI-STATE Zero Zero 8 data bits Zero Zero 4 trailing zeroes Figure 2. ADC081S021 Serial Timing Diagram SCLK 1 tCSH 2 tCSSU CS Figure 3.
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ADC081S021 SNAS308E – APRIL 2005 – REVISED MARCH 2013 www.ti.com negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC081S021 input at the same time.
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ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 Typical Performance Characteristics TA = +25°C, fSAMPLE = 50 ksps to 200 ksps,fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz unless otherwise stated. DNL fSCLK = 1 MHz INL fSCLK = 1 MHz Figure 4. Figure 5. DNL fSCLK = 4 MHz INL fSCLK = 4 MHz Figure 6. Figure 7. DNL vs. Clock Frequency INL vs. Clock Frequency Figure 8. Figure 9.
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ADC081S021 SNAS308E – APRIL 2005 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps,fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz unless otherwise stated. 10 Total Unadjusted Error vs. Clock Frequency VA = 3.0V or 5.0V SNR vs. Clock Frequency Figure 10. Figure 11. SINAD vs. Clock Frequency SFDR vs. Clock Frequency Figure 12. Figure 13. THD vs. Clock Frequency Spectral Response, VA = 5V fSCLK = 1 MHz Figure 14. Figure 15.
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ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 Typical Performance Characteristics (continued) TA = +25°C, fSAMPLE = 50 ksps to 200 ksps,fSCLK = 1 MHz to 4 MHz, fIN = 100 kHz unless otherwise stated. Spectral Response, VA = 5V fSCLK = 4 MHz Power Consumption vs. Throughput, fSCLK = 4 MHz Figure 16. Figure 17.
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ADC081S021 SNAS308E – APRIL 2005 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION ADC081S021 OPERATION The ADC081S021 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter core. Simplified schematics of the ADC081S021 in both track and hold modes are shown in Figure 18 and Figure 19, respectively.
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ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 Sixteen SCLK cycles are required to read a complete sample from the ADC. The sample bits (including leading or trailing zeroes) are clocked out on falling edges of SCLK, and are intended to be clocked in by a receiver on subsequent rising edges of SCLK. The ADC will produce three leading zero bits on SDATA, followed by eight data bits, most significant first. After the data bits, the ADC will clock out four trailing zeros.
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ADC081S021 SNAS308E – APRIL 2005 – REVISED MARCH 2013 www.ti.com TYPICAL APPLICATION CIRCUIT A typical application of the ADC is shown in Figure 21. Power is provided in this example by the Texas Instruments LP2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. The power supply pin is bypassed with a capacitor network located close to the ADC.
PAGE 15
ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 MODES OF OPERATION The ADC has two possible modes of operation: normal mode, and shutdown mode. The ADC enters normal mode (and a conversion process is begun) when CS is pulled low. The device will enter shutdown mode if CS is pulled high before the tenth falling edge of SCLK after CS is pulled low, or will stay in normal mode if CS remains low. Once in shutdown mode, the device will stay there until CS is brought low again.
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ADC081S021 SNAS308E – APRIL 2005 – REVISED MARCH 2013 www.ti.com If CS is brought back high before the 10th falling edge of SCLK, the device will return to shutdown mode. This is done to avoid accidentally entering normal mode as a result of noise on the CS line. To exit shutdown mode and remain in normal mode, CS must be kept low until after the 10th falling edge of SCLK. The ADC will be fully powered-up after 16 SCLK cycles.
PAGE 17
ADC081S021 www.ti.com SNAS308E – APRIL 2005 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ SOT-23 DBV 6 1000 178.0 8.4 ADC081S021CIMF/NOPB SOT-23 ADC081S021CIMF Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 DBV 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 SOT-23 DBV 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC081S021CIMF SOT-23 DBV 6 1000 210.0 185.0 35.0 ADC081S021CIMF/NOPB SOT-23 DBV 6 1000 210.0 185.0 35.0 SOT-23 DBV 6 3000 210.0 185.0 35.0 WSON NGF 6 1000 210.0 185.0 35.0 WSON NGF 6 4500 367.0 367.0 35.
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MECHANICAL DATA NGF0006A www.ti.
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