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ADC08060

www.ti.com

SNAS120H –OCTOBER 2000–REVISED MARCH 2013

ADC08060 8-Bit, 20 MSPS to 60 MSPS, 1.3 m W/MSPS A/D Converter with Internal Sample-

and-Hold

Check for Samples: ADC08060

FEATURES

DESCRIPTION

The ADC08060 is a low-power, 8-bit, monolithic

• Single-Ended Input

analog-to-digital converter with an on-chip track-and-

• Internal Sample-and-Hold Function

hold circuit. Optimized for low cost, low power, small

• Low Voltage (Single +3V) Operation

size and ease of use, this product operates at

conversion rates of 20 MSPS to 70 MSPS with

• Small Package

outstanding dynamic performance over its full

• Power-Down Feature

operating range while consuming just 1.3 mW per

MHz of clock frequency. That's just 78 mW of power

KEY SPECIFICATION

at 60 MSPS. Raising the PD pin puts the ADC08060

into a Power Down mode where it consumes just 1

• Resolution: 8 bits

mW.

• Maximum Sampling Frequency: 60 MSPS (min)

The unique architecture achieves 7.5 Effective Bits

• DNL: 0.4 LSB(typ)

with 25 MHz input frequency. The excellent DC and

• ENOB 7.5bits (typ) at f

= 25 MHz

AC characteristics of this device, together with its low

• THD: -60 dB (typ)

power consumption and single +3V supply operation,

make it ideally suited for many imaging and

• Power Consumption

communications applications, including use in

– Operating: 1.3 mW/MSPS (typ)

portable equipment. Furthermore, the ADC08060 is

– Power Down Mode: 1 mW (typ)

resistant to latch-up and the outputs are short-circuit

proof. The top and bottom of the ADC08060's

APPLICATIONS

reference ladder are available for connections,

enabling a wide range of input possibilities. The

• Digital Imaging Systems

digital outputs are TTL/CMOS compatible with a

• Communication Systems

separate output power supply pin to support

interfacing with 3V or 2.5V logic. The output coding is

• Portable Instrumentation

straight binary and the digital inputs (CLK and PD)

• Viterbi Decoders

are TTL/CMOS compatible.

• Set-Top Boxes

The ADC08060 is offered in a 24-lead TSSOP

package and is specified over the industrial

temperature range of −40°C to +85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 ADC08060 8-Bit, 20 MSPS to 60 MSPS, 1.3 m W/MSPS A/D Converter with Internal Sampleand-Hold Check for Samples: ADC08060 FEATURES DESCRIPTION • • • • • The ADC08060 is a low-power, 8-bit, monolithic analog-to-digital converter with an on-chip track-andhold circuit.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com Block Diagram DR VD (pin 18) VA VRT COARSE/FINE COMPARATORS 1 1 7 ENCODER & ERROR CORRECTION 8 1 7 8 SWITCHES VRM MUX COARSE/FINE COMPARATORS 25 6 VRB 1 7 ENCODER & ERROR CORRECTION 8 AGN D P D 8 OUTPUT DRIVERS DAT A OU T CLOCK GEN CL K VIN VIN GND DR GND (pin 17) Pin Configuration Figure 1.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS Pin No. Symbol Equivalent Circuit 6 VIN Analog signal input. Conversion range is VRB to VRT. 3 VRT Analog Input that is the high (top) side of the reference ladder of the ADC. Nominal range is 1.0V to VA. Voltage on VRT and VRB inputs define the VIN conversion range. Bypass well. See THE ANALOG INPUT for more information. 9 VRM Mid-point of the reference ladder.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) (3) Supply Voltage (VA) 3.8V Driver Supply Voltage (DR VD) VA + 0.3V Voltage on Any Input or Output Pin −0.3V to VA Reference Voltage (VRT, VRB) VA to AGND −0.3V to (VA + 0.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 Converter Electrical Characteristics The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TA = 25°C (1) (2) (3) Symbol Parameter Conditions Typical (4) Limits (4) Units (Limits) DC ACCURACY INL Integral Non-Linearity DNL Differential Non-Linearity ±0.5 ±1.3 LSB (max) ±0.4 +1.0 −0.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com Converter Electrical Characteristics (continued) The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle. Boldface limits apply for TJ = TMIN to TMAX: all other limits TA = 25°C (1)(2)(3) Symbol Parameter Conditions Typical (4) Limits (4) Units (Limits) CLK, PD DIGITAL INPUT CHARACTERISTICS VIH Logical High Input Voltage DR VD = VA = 3.3V 2.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 Converter Electrical Characteristics (continued) The following specifications apply for VA = DR VD = +3.0VDC, VRT = +1.9V, VRB = 0.3V, CL = 10 pF, fCLK = 60 MHz at 50% duty cycle.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated 8 INL INL vs. Temperature Figure 2. Figure 3. INL vs. Supply Voltage INL vs. Sample Rate Figure 4. Figure 5. DNL DNL vs. Temperature Figure 6. Figure 7.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated DNL vs. Supply Voltage DNL vs. Sample Rate Figure 8. Figure 9. SNR vs. Temperature SNR vs. Supply Voltage Figure 10. Figure 11. SNR vs. Sample Rate SNR vs. Input Frequency Figure 12. Figure 13.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated 10 SNR vs. Clock Duty Cycle Distortion vs. Temperature Figure 14. Figure 15. Distortion vs. Supply Voltage Distortion vs. Sample Rate Figure 16. Figure 17. Distortion vs. Input Frequency Distortion vs. Clock Duty Cycle Figure 18. Figure 19.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated SINAD/ENOB vs. Temperature SINAD/ENOB vs. Supply Voltage Figure 20. Figure 21. SINAD/ENOB vs. Sample Rate SINAD/ENOB vs. Clock Duty Cycle Figure 22. Figure 23. SINAD/ENOB vs. Input Frequency Power Consumption vs. Sample Rate Figure 24. Figure 25.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VA = DR VD = 3V, fCLK = 60 MHz, fIN = 10 MHz, unless otherwise stated Spectral Response @ fIN = 10.1 MHz Spectral Response @ fIN = 25 MHz Figure 26. Figure 27. Intermodulation Distortion (IMD) Figure 28.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input signal and goes into the “hold” mode tAD after the clock goes low. APERTURE JITTER is the variation in aperture delay from sample to sample. Aperture jitter shows up as noise at the output.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal frequency at the output to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The ADC08060 uses a new, unique architecture that achieves over 7.4 effective bits at input frequencies up to 30 MHz. The analog input signal that is within the voltage range set by VRT and VRB is digitized to eight bits. Output format is straight binary. Input voltages below VRB will cause the output word to consist of all zeroes. Input voltages above VRB will cause the output word to consist of all ones.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com APPLICATIONS INFORMATION REFERENCE INPUTS The reference inputs VRT and VRB are the top and bottom of the reference ladder, respectively. Input signals between these two voltages will be digitized to 8 bits. External voltages applied to the reference input pins should be within the range specified in the Operating Ratings (1.0V to (VA + 0.1V) for VRT and 0V to (VRT − 1.0V) for VRB).
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 +3V Choke 10 PF 10 PF 604: 0.1 PF 3 8 + 2 1 1 4 12 1/2 LM8272 VIN - 0.1 PF 18 VA 6 DR VD 7 4 0.1 PF VIN GND 0.01 PF 3 D7 D6 D5 D4 D3 D2 D1 D0 VRT 1 PF 4.7k 9 1.62k ADC08060 0.1 PF 4.7k 10 13 14 15 16 19 20 21 22 VRB 1 PF 0.1 PF 10 PF +3V 1 PF + LM4040-2.5 + + 470: 0.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com Choke +3V + 10 PF 0.1 PF Gain Adjust 10 PF 0.1 PF 12 200 - * + +5V 10 22 6 LMH6702 240 Signal Input 1 + 47 VA VIN DR VD VIN GND ADC08060 0.1 PF 0.33 PF 0.1 PF 18 10 pF 7 100 4 12 VRT 3 * D7 D6 D5 D4 D3 D2 D1 D0 * 4.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 While a single voltage source is recommended for the VA and DR VD supplies of the ADC08060, these supply pins should be well isolated from each other to prevent any digital noise from being coupled into the analog portions of the ADC. A choke or 27Ω resistor is recommended between these supply lines with adequate bypass capacitors close to the supply pins.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 • • www.ti.com tPD is the signal propagation rate down the clock line, "L" is the line length ZO is the characteristic impedance of the clock line (7) This termination should be located as close as possible to, but within one centimeter of, the ADC08060 clock pin. Further, the termination should be beyond the ADC08060 clock pin as seen from the clock source. Typical tPD is about 150 ps/inch on FR-4 board material.
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ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 Single Ground Plane ADC Clock Source Locate driving amplifier near ADC input pin RF Locate Clock Source near ADC clock pin RIN R C LMH6702 ADC 08060 Locate power supply on the digital side of the ADC Figure 33. Layout Example DYNAMIC PERFORMANCE The ADC08060 is a.c. tested and its dynamic performance is ensured. To meet the published specifications, the clock source driving the CLK input must exhibit less than 10 ps (rms) of jitter.
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ADC08060 SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 www.ti.com Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must charge for each conversion, the more instantaneous digital current is required from DR VD and DR GND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Buffering the digital data outputs (with a 74F541, for example) may be necessary if the data bus capacitance exceeds 10 pF.
PAGE 23
ADC08060 www.ti.com SNAS120H – OCTOBER 2000 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision G (March 2013) to Revision H • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ADC08060CIMTX/NOPB Package Package Pins Type Drawing TSSOP PW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 8.3 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADC08060CIMTX/NOPB TSSOP PW 24 2500 367.0 367.0 35.
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