Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Switched integrator SOIC 24

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ACF2101

Low Noise, Dual

SWITCHED INTEGRATOR

A B

V+ Gnd V–

Sw In B

Hold

Sw In A

Cap A

In A

Com A Sw Com A

Sw Out A

Out A

100pF

Cap B

In B

Com B Sw Com B

Sw Out B

Out B

Reset Hold Select

100pF

A B A B

Hold

Reset

Select

INTERNAL

APPLICATIONS

● CURRENT TO VOLTAGE CONVERSION

● PHOTODIODE INTEGRATOR

● CURRENT MEASUREMENT

● CHARGE MEASUREMENT

● CT SCANNER FRONT END

● MEDICAL, SCIENTIFIC, AND INDUSTRIAL

INSTRUMENTATION

DESCRIPTION

The ACF2101 is a dual switched integrator for preci-

sion applications. Each channel can convert an input

current to an output voltage by integration, using either

an internal or external capacitor. Included on the chip

are precision 100pF integration capacitors, hold and

reset switches, and output multiplexers.

As a complete circuit on a single chip, the ACF2101

eliminates many of the problems commonly encoun-

tered in discrete designs, such as leakage current errors

and noise pickup. The integrating approach can pro-

vide lower noise than conventional transimpedance

amplifier designs and also eliminates the need for high

performance, high value feedback resistors.

The extremely low bias current and low noise of the

ACF2101’s

Difet

amplifiers, along with active la-

ser trimming of both offset and drift, assure precision

current to voltage conversion.

Although designed for +5V, –15V supplies, the

ACF2101 can be operated on supplies up to ±18VDC.

It is available in both 24-pin plastic DIP and SOIC

packages.

Difet

Burr-Brown Corp.

FEATURES

● INCLUDES INTEGRATION CAPACITOR,

RESET AND HOLD SWITCHES, AND

OUTPUT MULTIPLEXER

● LOW NOISE: 10µVrms

● LOW CHARGE TRANSFER: 0.1pC

● WIDE DYNAMIC RANGE: 120dB

● LOW BIAS CURRENT: 100fA

FPO

SBFS003

Summary of content (16 pages)

PAGE 1
® ACF2101 FPO Low Noise, Dual SWITCHED INTEGRATOR FEATURES APPLICATIONS ● INCLUDES INTEGRATION CAPACITOR, RESET AND HOLD SWITCHES, AND OUTPUT MULTIPLEXER ● LOW NOISE: 10µVrms ● LOW CHARGE TRANSFER: 0.
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SPECIFICATIONS ELECTRICAL At TA = +25°C, V+ = +5V, V– = –15V, Internal CINTEGRATION = CINTERNAL = 100pF, unless otherwise noted. ACF2101BP, BU PARAMETER CONDITIONS MIN TYP MAX UNITS ±100 ±100 µA µA ANALOG INPUT INPUT RANGE Input Current Range Switched Input (SW IN A, SW IN B) Direct Input (IN A, IN B) INPUT IMPEDANCE Switched Input Hold Switch OFF Hold Switch ON Direct Input HOLD SWITCH VOLTAGE Hold Switch Withstand Voltage 1000 1.
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SPECIFICATIONS (CONT) At TA = +25°C, V+ = +5V, V– = –15V, Internal CINTEGRATION = CINTERNAL = 100pF, unless otherwise noted. ACF2101BP, BU PARAMETER CONDITIONS MIN TYP MAX UNITS –10 ±5 –13.5, +1.0 +0.
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ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply ............................................................................................... ±18V Input Current ..................................................................................... ±5mA Output Short Circuit Duration .................................. Continuous to Ground Power Dissipation .......................................................................... 500mW Operating Temperature ..............................
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DICE INFORMATION PAD FUNCTION PAD FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 A Out A Ground A Common A Cap A In A Switch-In B Switch-In B In B Cap B Common B Ground B Out 13 14 15 16 17 18 19 20 21 22 23 24 B Switch-Out B Switch-Common B Select B Reset B Hold V– V+ A Hold A Reset A Select A Switch-Common A Switch-Out Substrate Bias: Ground. MECHANICAL INFORMATION Die Size Die Thickness Min. Pad Size MILS (0.001") MILLIMETERS 132 x 157 ±5 20 ±3 4x4 3.35 x 3.99 ±0.13 0.51 ±0.08 0.10 x 0.
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TYPICAL PERFORMANCE CURVES At TA = +25°C, V+ = +5V, V– = –15V, CINTEGRATION = CINTERNAL = 100pF, unless otherwise noted. TOTAL OUTPUT NOISE vs C1 and C2 BIAS CURRENT vs TEMPERATURE 100 10pA Total Output Noise (µVrms) Op Amp Bias Current 90 1pA 100fA 80 C2 = 70 50 40 C2 = 200pF 30 F C 2 = 500p 20 10fA C2 = 1000pF 0 –40 –20 0 20 40 60 80 0 100 100 200 300 400 500 600 700 800 900 1000 C1 (pF) Temperature (°C) Sw Out Settling Time (µs) to 0.
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APPLICATIONS INFORMATION Improper handling or cleaning may increase droop. Contamination from handling parts and circuit boards can be removed with cleaning solvents and de-ionized water. BASIC CIRCUIT CONNECTION Basic Layout As with any precision circuit, careful layout will ensure best performance. Make short, direct interconnections and avoid stray wiring capacitance—especially at the analog and digital input pins. Pinout The pinout for the DIP and SOIC package of the ACF2101 is different.
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Top View ACF2101BU Top View ACF2101BP Guards Input 1 Sw In B 2 In B Sw In A 24 In A 23 Input 1 Out A 24 2 Gnd A 23 VOUT * * 3 Cap B Cap A 22 3 Com A 22 4 Com B Com A 21 4 Cap A 21 5 Gnd B Gnd A 20 5 In A 20 6 Out B Out A 19 6 Sw In A V+ 19 V– 18 * Input VOUT Guards VOUT Input V+ 1µF 7 18 7 Sw In B 8 17 8 In B 17 9 16 9 Cap B 16 10 15 10 Com B 15 11 Gnd B 14 12 Out B 1µF V– * 14 11 1µF 1µF 12 + V– SOIC V+ 13 * Option
PAGE 9
MODES OF OPERATION The three basic modes of operation of each integrator are controlled by the Hold and Reset switches. In Integrate mode, the output voltage integrates negatively toward –10V. In Hold mode, the output voltage remains at the present value, except for output droop. In Reset mode, the integration capacitor is discharged and the output voltage is driven to analog common. See Figure 4. Hold and Reset Switches To use the Hold switch, connect the input current to the “Sw In” pin.
PAGE 10
OUTPUT VOLTAGE The integrator output voltage range is from +0.5V to –10V. The output voltage (VOUT) can be calculated as: V OUT = VOUT = CINT = IIN = ∆t = the the the the NOISE The total output noise for a specific application of the ACF2101 is the rms total of the noise in the modes used: Integrate noise (enI), Hold noise (enH) and Reset noise (enR). The noise in both the Hold (enH) and Reset (enR) modes is 10µVrms.
PAGE 11
Charge Transfer Charge transfer is the charge that is coupled from the logic control inputs through circuit capacitance to the integration capacitor when the Hold and Reset switches change mode. Careful printed circuit layout must be used to minimize external coupling from digital to analog circuitry and the resulting charge transfer. Charge transfer results in a DC charge offset error voltage. The ACF2101 switches are compensated to reduce charge transfer errors.
PAGE 12
For CINTEGRATION = 100pF, RPROGRAM is calculated below: RPROGRAM 10kHz 1kHz 100Hz 60Hz 50Hz 10Hz 1MΩ 10MΩ 100MΩ 167MΩ 200MΩ 1GΩ At the end of the integration cycle, the Hold switch of the ACF2101 is opened to hold a constant value at the output of the ACF2101. The constant value output voltage of the ACF2101 is transferred onto a 10nF capacitor by closing the ACF2101’s Select switch.
PAGE 13
+15V 10kΩ 164kΩ 8 fs 4 2 1000pF Approximately 18µs 7 555 Timer 6 1 100pF 3 Hold +VS 10kΩ 14 1N914 4 6 54.5kΩ 100pF Both approximately 6µs 1 2 556 Dual Timer 8 1000pF 54.5kΩ 10 7 5 13 12 9 100pF 20kΩ Reset Select FIGURE 11. Timing Generator. VOLTAGE INPUT EXAMPLE Figure 12 illustrates the use of the ACF2101 with a voltage input. This approach is useful in applications where a constant current source is needed.
PAGE 14
+15V 2 6 REF 102 Hold 7 4 Reset Select 1µF CINTERNAL Cap Out 100pF 400kΩ R1 In Reset IOFF Sw In Sw Out Hold D1 C1 Com Sw Com 1/2 ACF2101 FIGURE 12. Using the ACF2101 with a Voltage Source.
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PACKAGE OPTION ADDENDUM www.ti.
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