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74ACT11008

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS013C – AUGUST 1987 – REVISED APRIL 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Inputs Are TTL-Voltage Compatible

Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

EPIC

 (Enhanced-Performance Implanted

CMOS) 1- m Process

500-mA Typical Latch-Up Immunity

at 125°C

Package Options Include Plastic

Small-Outline (D), Plastic Thin Shrink

Small-Outline (PW), and Standard Plastic

300-mil DIPs (N) Packages

description

The 74ACT11008 contains four independent 2-input AND gates. It performs the Boolean function Y = A B or

Y A B

in positive logic.

The 74ACT11008 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

H H H

L XL

X L L

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

logic diagram (positive logic)

GND

(TOP VIEW)

D, N, OR PW PACKAGE

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

EPIC is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (14 pages)

PAGE 1
74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C – AUGUST 1987 – REVISED APRIL 1996 D D D, N, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D), Plastic Thin Shrink Small-Outline (PW), and Standard Plastic 300-mil DIPs (N) Packages D D D 1A 1Y 2Y GND GND 3Y 4Y 4B 1
PAGE 2
74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C – AUGUST 1987 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.
PAGE 3
74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C – AUGUST 1987 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN 4.5 V IOH = –50 50 mA VOH 24 mA IOH = –24 IOL = 50 mA VOL IOL = 24 mA TA = 25°C TYP MAX MIN 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.7 5.5 V 4.94 MAX UNIT V 4.7 4.5 V 0.1 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 V 0.44 IOH† IOL† VO = 3.
PAGE 4
74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE SCAS013C – AUGUST 1987 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 3V Input (see Note B) From Output Under Test CL = 50 pF (see Note A) 1.5 V 1.5 V 0V tPLH tPHL 500 Ω Output 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS LOAD CIRCUIT NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ACT11008DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 23-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ACT11008DR SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.