Datasheet

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74ACT11004

HEX INVERTER

SCAS215B – JANUARY 1988 – REVISED JUNE 1997

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Inputs Are TTL-Voltage Compatible

Flow-Through Architecture Optimizes PCB

Layout

Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

EPIC  (Enhanced-Performance Implanted

CMOS) 1- m Process

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages and Standard Plastic (N) 300-mil

DIPs

description

This device contains six independent inverters. It performs the Boolean function Y = A.

The 74ACT11004 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each inverter)

INPUT

OUTPUT

H L

L H

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

GND

DB, DW, N, OR PW PACKAGE

(TOP VIEW)

NC – No internal connection

Summary of content (15 pages)

PAGE 1
74ACT11004 HEX INVERTER SCAS215B – JANUARY 1988 – REVISED JUNE 1997 D D D D D D DB, DW, N, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages and Standard Pl
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74ACT11004 HEX INVERTER SCAS215B – JANUARY 1988 – REVISED JUNE 1997 logic diagram (positive logic) 1A 20 1 19 2 2A 2Y 18 3 3A 4A 5A 6A 1Y 3Y 13 8 12 9 11 10 4Y 5Y 6Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . .
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74ACT11004 HEX INVERTER SCAS215B – JANUARY 1988 – REVISED JUNE 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –50 50 mA VOH 24 mA IOH = –24 IOH = –75 mA† II ICC ∆ICC‡ Ci TA = 25°C TYP MAX 4.4 4.4 5.5 V 5.4 5.4 4.5 V 3.94 3.8 5.5 V 4.94 IOL = 75 mA† VI = VCC or GND 0.1 V 0.1 5.5 V 0.1 0.1 4.5 V 0.36 0.44 5.5 V 0.36 0.44 V 1.65 mA ±0.1 ±1 5.5 V 4 40 mA 5.5 V 0.
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74ACT11004 HEX INVERTER SCAS215B – JANUARY 1988 – REVISED JUNE 1997 PARAMETER MEASUREMENT INFORMATION Input (see Note B) From Output Under Test CL = 50 pF (see Note A) 3V 1.5 V 1.5 V 0V tPHL 500 Ω 50% VCC Output LOAD CIRCUIT tPLH VOH 50% VCC VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 7
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device 74ACT11004DBR Package Package Pins Type Drawing SSOP DB 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.5 2.5 12.0 16.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74ACT11004DBR SSOP DB 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.