Datasheet

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54AC16244, 74AC16244

16-BIT BUFFERS/LINE DRIVERS

WITH 3-STATE OUTPUTS

SCAS120A – MARCH 1990 – REVISED APRIL 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

Widebus

Family

3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

Flow-Through Architecture Optimizes PCB

Layout

Distributed V

and GND Configuration

Minimizes High-Speed Switching Noise

EPIC

(Enhanced-Performance Implanted

CMOS) 1- m Process

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages Using 25-mil

Center-to-Center Pin Spacings, and 380-mil

Fine-Pitch Ceramic Flat (WD) Packages

Using 25-mil Center-to-Center Pin Spacings

description

The ’AC16244 are 16-bit buffers/line drivers

designed specifically to improve both the

performance and density of 3-state memory

address drivers, clock drivers, and bus-oriented

receivers and transmitters. They can be used as

four 4-bit buffers, two 8-bit buffers, or one 16-bit

buffer. These devices provide true outputs and

symmetrical active-low output-enable (OE

)

inputs. When OE is low, the device passes

noninverted data from the A inputs to the Y

outputs. When OE

is high, the outputs are in the

high-impedance state.

The 74AC16244 is packaged in the TI’s shrink small-outline package, which provides twice the I/O pin count

and functionality of standard small-outline packages in the same printed-circuit-board area.

The 54AC16244 is characterized for operation over the full military temperature range of –55°C to 125°C. The

74AC16244 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each driver)

INPUTS

OUTPUT

OE A

L H H

L LL

H X Z

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

1OE

1Y1

1Y2

GND

1Y3

1Y4

2Y1

2Y2

GND

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

4Y1

4Y2

GND

4Y3

4Y4

4OE

2OE

1A1

1A2

GND

1A3

1A4

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

4A1

4A2

GND

4A3

4A4

3OE

54AC16244 . . . WD PACKAGE

74AC16244 . . . DGG OR DL PACKAGE

(TOP VIEW)

Summary of content (12 pages)

PAGE 1
54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 D D D D D D D Members of the Texas Instruments Widebust Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Distributed VCC and GND Configuration Minimizes High-Speed Switching Noise EPIC t (Enhanced-Performance Implanted CMOS) 1-mm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic 300-mil Shrin
PAGE 2
54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 logic symbol† 1OE 1 48 2OE 3OE 4OE 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 25 24 EN1 EN2 EN3 EN4 47 46 1 1 3 44 5 43 6 41 8 40 1 2 9 38 11 37 12 36 13 35 1 3 14 33 16 32 17 30 19 29 1 4 20 27 22 26 23 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 2OE 2A1 2A2 2A3 2A4 1 3OE 47 2 46 3 44 5 43 6 1Y1 3A1 1Y2 3A2 1Y3 3A3 1Y4 3A4 48 4OE 41 8 40 9 38 11 37 12 2Y1 4A1 2Y2 4A2 2Y3 4A3 2Y4 4A4 25 36 13 35 14 33 16 32 17 3Y1 3Y2 3Y3 3Y4 24 30 19 29 20 27 22 26 23 4Y1 4Y2 4Y3 4Y4 absolute maximum ratings over operating free-air t
PAGE 4
54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 recommended operating conditions (see Note 3) 54AC16244 VCC VIH Supply voltage (see Note 4) VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL VI VO IOH IOL ∆t/∆v Low-level input voltage NOM MAX 3 5 5.5 3 5 5.5 3.15 V V 0.9 0.9 1.35 1.35 1.65 1.65 VCC VCC 0 0 VCC VCC 0 –4 –4 –24 –24 VCC = 5.5 V VCC = 3 V –24 –24 12 12 VCC = 4.5 V VCC = 5.
PAGE 5
4AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y MIN TA = 25°C TYP MAX 54AC16244 74AC16244 MIN MAX MIN MAX 2 7.1 9.4 2 10.8 2 10.8 2.4 8.3 10.7 2.4 11.8 2.4 11.8 2.2 7.5 10 2.2 11.5 2.
PAGE 6
54AC16244, 74AC16244 16-BIT BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS120A – MARCH 1990 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test Open GND TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND 500 Ω CL = 50 pF (see Note A) LOAD CIRCUIT VCC 50% Input 50% 0V tPHL tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VOH 50% VCC VOL VCC Output Waveform 2 S1 at GND (see Note B) 50% 50% 0V tPZL [ VCC tPLZ Output Waveform 1 S1 at 2
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 74AC16244DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 74AC16244DLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74AC16244DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 74AC16244DLR SSOP DL 48 1000 346.0 346.0 49.
PAGE 10
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 11
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 12
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