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74AC11086

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Center-Pin V

and GND Configurations

Minimize High-Speed Switching Noise

EPIC

 (Enhanced-Performance Implanted

CMOS) 1-µm Process

500-mA Typical Latch-Up Immunity at

125°C

Package Options Include Plastic

Small-Outline (D) Packages and Standard

Plastic 300-mil DIPs (N)

description

This device contains four independent 2-input exclusive-OR gates. It performs the Boolean function

Y = A ⊕ B = AB + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced

in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the

output.

The 74AC11086 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

L L L

L HH

H LH

H H L

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

GND

D OR N PACKAGE

(TOP VIEW)

Summary of content (9 pages)

PAGE 1
74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 D D D D Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity at 125°C Package Options Include Plastic Small-Outline (D) Packages and Standard Plastic 300-mil DIPs (N) D OR N PACKAGE (TOP VIEW) 1A 1Y 2Y GND GND 3Y 4Y 4B description 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 1B 2A 2B VCC VCC
PAGE 2
74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 logic diagram (positive logic) 1A 1B 2A 2B 3A 3B 4A 4B 1 2 16 15 3 14 1Y 2Y 11 6 10 9 7 8 3Y 4Y exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These are five equivalent exclusive-OR symbols valid for a 74AC11086 gate in positive logic; negation may be shown at any two ports.
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74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 recommended operating conditions VCC Supply voltage VIH High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V MIN NOM MAX 3 5 5.5 0.9 VI VO Input voltage 0 Output voltage 0 IOH High-level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature V 3.85 Low-level input voltage Low-level output current V 2.1 3.15 VIL IOL UNIT VCC = 4.
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74AC11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS081A – NOVEMBER 1989 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B Y MIN TA = 25°C TYP MAX MIN MAX 1.5 5.6 9.4 1.5 10.6 1.5 5.1 7.4 1.5 8.2 UNIT ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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