Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state DIP 24

MOTOROLA CMOS LOGIC DATAMC14508B

344

The MC14508B dual 4–bit latch is constructed with MOS P–channel and

N–channel enhancement mode devices in a single monolithic structure. The

part consists of two identical, independent 4–bit latches with separate Strobe

(ST) and Master Reset (MR) controls. Separate Disable inputs force the

outputs to a high impedance state and allow the devices to be used in time

sharing bus line applications.

These complementary MOS latches find primary use in buffer storage,

holding register, or general digital logic functions where low power

dissipation and/or high noise immunity is desired.

• 3–State Output

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable–of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load over the Rated Temperature Range

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter Value Unit

DC Supply Voltage – 0.5 to + 18.0 V

, V

out

Input or Output Voltage (DC or Transient) – 0.5 to V

+ 0.5 V

, I

out

Input or Output Current (DC or Transient),

per Pin

± 10 mA

Power Dissipation, per Package† 500 mW

stg

Storage Temperature – 65 to + 150

Lead Temperature (8–Second Soldering) 260

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

TRUTH TABLE

MR ST Disable D3 D2 D1 D0 Q3 Q2 Q1 Q0

0 1 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 1 0 0 0 1

0 1 0 0 0 1 0 0 0 1 0

0 1 0 0 1 0 0 0 1 0 0

0 1 0 1 0 0 0 1 0 0 0

0 0 0 X X X X Latched

1 X 0 X X X X 0 0 0 0

X X 1 X X X X High Impedance

X = Don’t Care

CIRCUIT DIAGRAM

DIS

(TO OTHER THREE LATCHES)

SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94

L SUFFIX

CERAMIC

CASE 623

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBDW SOIC

= – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 709

DW SUFFIX

SOIC

CASE 751E

BLOCK DIAGRAM

DIS

= PIN 24

= PIN 12

Summary of content (7 pages)

PAGE 1
SEMICONDUCTOR TECHNICAL DATA The MC14508B dual 4–bit latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4–bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time sharing bus line applications.
PAGE 2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.
PAGE 3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) All Types Characteristic Symbol VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 220 90 60 440 180 120 tWH(R) 5.0 10 15 200 100 70 100 50 35 — — — ns trem 5.0 10 15 30 25 20 – 15 0 0 — — — ns tWH(S) 5.
PAGE 4
tWH(S) STROBE INPUT 50% 50% tsu tWH(R) th Dn INPUT MASTER RESET INPUT 50% tPLH Qn OUTPUT tPHL 10% VSS VOH Qn OUTPUT 90% 50% tTLH VDD 50% VOL tTHL Figure 1. AC Waveforms VDD MR ST DISABLE D0 D1 D2 D3 PULSE GENERATOR VDD ST3 VDD Q0 ST1 Q1 Q2 1.0 k Test ST1 ST2 ST3 ST4 tPHZ tPLZ tPZL tPZH Open Close Close Open Close Open Open Close Close Open Open Close Open Close Close Open Q3 1.
PAGE 5
IOD 3–STATE MODE OF OPERATION The MC14508B can be used in bussed systems as shown. The output terminals of N 4–bit latches can be directly wired to a bus line, and to one of the 4–bit latches selected. The selected latch controls the logic state of the bus line and the remaining (N–1) 4–bit latches are disabled into a high impedance “off” state.
PAGE 6
OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 623–05 ISSUE M 24 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). 13 B 1 12 DIM A B C D F G J K L M N A F SEATING PLANE C L N D G INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050 J M K MILLIMETERS MIN MAX 31.24 32.
PAGE 7
OUTLINE DIMENSIONS DW SUFFIX PLASTIC SOIC PACKAGE CASE 751E–04 ISSUE E –A– 24 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. 13 –B– 12X P 0.010 (0.25) 1 M B M 12 24X D J 0.