LE866 Hardware Design Guide [01.2017] 1VV0301355 Rev. 0 – 2017-02-21 Mod.0818 2017-01 Rev.
LE866 Hardware Design Guide SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE NOTICE While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies or omissions.
LE866 Hardware Design Guide USAGE AND DISCLOSURE RESTRICTIONS I. License Agreements The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement. II. Copyrighted Materials Software and documentation are copyrighted materials. Making unauthorized copies is prohibited by law.
LE866 Hardware Design Guide APPLICABILITY TABLE PRODUCTS LE866-SV1 LE866A1-NA LE866A1-KK LE866A1-JS LE866A1-KS 1VV0301355 Rev.
LE866 Hardware Design Guide Contents NOTICE 2 COPYRIGHTS ................................................................................................ 2 COMPUTER SOFTWARE COPYRIGHTS ...................................................... 2 USAGE AND DISCLOSURE RESTRICTIONS ............................................... 3 I. License Agreements ..................................................................... 3 II. Copyrighted Materials ...........................................................
LE866 Hardware Design Guide 4. POWER SUPPLY ....................................................................... 24 Power Supply Requirements....................................................... 24 Power Consumption ................................................................... 25 General Design Rules ................................................................. 26 4.3.1. Electrical Design Guidelines ....................................................... 26 4.3.1.1.
LE866 Hardware Design Guide 5.10.2. LOW Pass filter Example ............................................................ 56 6. RF SECTION .............................................................................. 57 Antenna requirements................................................................. 57 6.1.1. Main Antenna ............................................................................. 57 6.1.2. PCB Design guidelines ...............................................................
LE866 Hardware Design Guide 14. ACRONYMS ............................................................................... 82 15. DOCUMENT HISTORY .............................................................. 84 1VV0301355 Rev.
LE866 Hardware Design Guide 1. INTRODUCTION Scope This document introduces the Telit LE866 modules and presents possible and recommended hardware solutions for developing a product based on this module. All the features and solutions detailed in this document are applicable to all LE866 variants, where LE866 refers to the variants listed in the applicability table. Obviously, this document cannot embrace every hardware solution or every product that can be designed.
LE866 Hardware Design Guide Text Conventions Danger – This information MUST be followed or catastrophic equipment failure or bodily injury may occur. Caution or Warning – Alerts the user to important points about integrating the module, if these points are not followed, the module and end user equipment may fail or malfunction. Tip or Information – Provides advice and suggestions that may be useful when integrating the module. All dates are in ISO 8601 format, i.e. YYYY-MM-DD. 1VV0301355 Rev.
LE866 Hardware Design Guide Related Documents SIM Holder Design Guides, 80000NT10001A LE866 AT Commands Reference Guide, 80471ST10691A Telit EVK2 User Guide, 1vv0300704 xE866 Interfaces User Guide, 1vv0301260 1VV0301355 Rev.
LE866 Hardware Design Guide 2. GENERAL PRODUCT DESCRIPTION Overview LE866 is Telit’s new LTE series for IoT applications. In its most basic use case, LE866 can be applied as a wireless communication front-end for telematics products, offering mobile communication features to an external host CPU through its interfaces. Product Variants and Frequency Bands All LE866 variants are single mode LTE.
LE866 Hardware Design Guide Target market LE866 can be used for telematics applications where tamper-resistance, confidentiality, integrity, and authenticity of end-user information are required, for example: Emergency call Telematics services Road pricing Pay-as-you-drive insurance Stolen vehicles tracking Internet connectivity Main features Function Features Modem Multi-RAT cellular modem for voice and data communication o LTE FDD Cat1 (10/5Mbps DL/UL).
LE866 Hardware Design Guide TX Output Power Band Power class LTE All Bands Class 3 (0.2W) RX Sensitivity Below the 3GPP measurement conditions used to define the RX sensitity: Technology 3GPP Compliance 4G LTE Throughput >95% 10MHz Dual Receiver Product Band Sensitivity (dBm) LE866-SV1 LTE FDD B4 -102.0 LTE FDD B13 LE866A1-NA LTE FDD B2 -102.0 LTE FDD B4 LTE FDD B12 LE866A1-KK LTE FDD B3 -102.0 LTE FDD B8 LE866A1-JS LTE FDD B1 -102.0 LTE FDD B8 1VV0301355 Rev.
LE866 Hardware Design Guide Mechanical specifications 2.7.1. Dimensions The overall dimensions of LE866 family are: Length: 25 mm Width: 15 mm Thickness: 2.2 mm 2.7.2. Weight The nominal weight of the module is 1.80 grams. Temperature range Note Operating Temperature Range Storage and nonoperating Temperature Range –20°C ÷ +55°C The module is fully functional(*) in all the temperature range, and it fully meets the 3GPP specifications.
LE866 Hardware Design Guide 3. PINS ALLOCATION Pin-out Pin Signal I/O Function Type Comment USB HS 2.0 COMMUNICATION PORT E5 USB_D+ I/O USB differential Data (+) - E6 USB_D- I/O USB differential Data (-) - Asynchronous Serial Port (USIF0) - Prog. / Data + HW Flow Control A4 C103/TXD I Serial data input (TXD) from DTE CMOS 1.8V A5 C104/RXD O Serial data output to DTE CMOS 1.8V A2 C108/DTR I Input for (DTR) from DTE CMOS 1.
LE866 Hardware Design Guide External SIM signal – Data I/O CMOS 1.8 Presence SIM input CMOS 1.8 A6 SIMIO I/O X SIMIN I C5 GPIO_01 DVI_WA0 SIM_IN I/O INT Main Function: GPIO01 Configurable GPIO Alternate function 1: Digital Audio Interface (WA0) Alternate Function 2: SIM_IN CMOS 1.8V C6 GPIO_02 DVI_RX SIM_IN I/O INT Main Function: GPIO02 Configurable GPIO Alternate Function 1: Digital Audio Interface (RX) Alternate Function 2: SIM_IN CMOS 1.
LE866 Hardware Design Guide Miscellaneous Functions G4 RESET* I G6 VAUX/PWRMON O Reset Input VBATT Pull up to VBATT (10Kohm) 1.8V stabilized output Power Power ON monitor 3GPP Rel12 PSM (Power Saving Mode) D3 PSM_WAKE I 3GPP Rel12 PSM Wake Up E8 PSM_STATUS O 3GPP Rel12 PSM Status CMOS 1.8V F8 PSM_ENA_OUT O 3GPP Rel12 PSM Enable for external LDOs CMOS 1.
LE866 Hardware Design Guide F3 GND - Ground Power G3 GND - Ground Power F6 GND - Ground Power A8 GND - Ground Power G8 GND - Ground Power A11 GND - Ground Power G11 GND - Ground Power A0 RESERVED - RESERVED G5 RESERVED - RESERVED B6 RESERVED - RESERVED D7 RESERVED - RESERVED E7 RESERVED - RESERVED F7 RESERVED - RESERVED G7 RESERVED - RESERVED B8 RESERVED - RESERVED C8 RESERVED - RESERVED A9 RESERVED - RESERVED B9 RESERVED - RESER
LE866 Hardware Design Guide G9 RESERVED - RESERVED A10 RESERVED - RESERVED B10 RESERVED - RESERVED C10 RESERVED - RESERVED D10 RESERVED - RESERVED E10 RESERVED - RESERVED F10 RESERVED - RESERVED G10 RESERVED - RESERVED B11 RESERVED - RESERVED C11 RESERVED - RESERVED D4 RESERVED - RESERVED F5 RESERVED - RESERVED F11 RESERVED - RESERVED E11 RESERVED - RESERVED D11 RESERVED - RESERVED WARNING Reserved pins must not be connected. 1VV0301355 Rev.
LE866 Hardware Design Guide If not used, almost all pins should be left disconnected.
LE866 Hardware Design Guide A7 SIMCLK A6 SIMIO D8 VDDIO_IN To be always supplied (or using VAUX/PWRMON or with an external LDO) RTS pin should be connected to the GND (on the module side) if flow control is not used. The above pins are also necessary to debug the application when the module is assembled on it so we recommend connecting them also to dedicated test point. 1VV0301355 Rev.
LE866 Hardware Design Guide LGA Pads Layout TOP VIEW A B C D E F G 0 RESERVED GND DIV ANT GND VBATT_PA GND GND 1 C105/RTS C106/CTS TX AUX GND VBATT_PA GND GND 2 C108/DTR C109/DCD RX AUX GND VBATT GND MAIN ANT 3 C107/DSR C125/RING GND PSM_WAK E GND GND GND 4 C103/TXD GPIO_06 GPIO_07 RESERVED DAC_OUT ADC_IN1 RESET* 5 C104/RXD GPIO_05 GPIO_01 GPIO_04 USB_D+ 6 SIMIO RESERVED GPIO_02 GPIO_03 USB_D- 7 SIMCLK SIMRST SIMVCC 8 GND 9 RESERVED RESERVE
LE866 Hardware Design Guide 4. POWER SUPPLY The power supply circuitry and board layout are a very important part in the full product design and they strongly reflect on the product overall performances, hence read carefully the requirements and the guidelines that will follow for a proper design. Power Supply Requirements The external power supply must be connected to VBATT & VBATT_PA signals and must fulfil the following requirements: Power Supply Value Nominal Supply Voltage 3.
LE866 Hardware Design Guide Power Consumption Mode Average (mA) AT+CFUN=1 23.4 AT+CFUN=4 21.0 Mode Description Connected mode USB Not connected Radio Disabled USB Not connected Power Saving Enabled AT+CFUN=5 3.0 USB not connected I-DRX (3GPP Rel.8) – paging 2.
LE866 Hardware Design Guide General Design Rules The principal guidelines for the Power Supply Design embrace three different design steps: the electrical design the thermal design the PCB layout. 4.3.1. Electrical Design Guidelines The electrical design of the power supply depends strongly from the power source where this power is drained. We will distinguish them into three categories: +5V input (typically PC internal regulator output) +12V input (typically automotive) Battery 4.3.1.1.
LE866 Hardware Design Guide 1VV0301355 Rev.
LE866 Hardware Design Guide 4.3.2. +12V Source Power Supply Design Guidelines The desired output for the power supply is 3.8V, hence due to the big difference between the input source and the desired output, a linear regulator is not suited and shall not be used. A switching power supply will be preferable because of its better efficiency.
LE866 Hardware Design Guide 4.3.2.1. Battery Source Power Supply Design Guidelines The desired nominal output for the power supply is 3.8V and the maximum voltage allowed is 4.2V, hence a single 3.7V Li-Ion cell battery type is suited for supplying the power to the Telit LE866 module. A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current absorption peaks, a 100μF tantalum capacitor is usually suited.
LE866 Hardware Design Guide 4.3.3. Thermal Design Guidelines The thermal design for the power supply heat sink should be done with the following specifications: Average current consumption during LTE transmission @PWR level max : 600 mA Average current during idle: 23 mA Considering the very low current during idle, especially if Power Saving function is enabled, it is possible to consider from the thermal point of view that the device absorbs current significantly only during calls.
LE866 Hardware Design Guide 4.3.4. Power Supply PCB layout Guidelines As seen on the electrical design guidelines the power supply shall have a low ESR capacitor on the output to cut the current peaks on the input to protect the supply from spikes The placement of this component is crucial for the correct working of the circuitry. A misplaced component can be useless or can even decrease the power supply performances.
LE866 Hardware Design Guide The below figure shows the recommended circuit: RTC Bypass out The LE866 module is provided by an internal RTC section but its reference supply is VBATT. So, in order to maintain active the RTC programming, VBATT should not be removed 1VV0301355 Rev.
LE866 Hardware Design Guide VAUX Power Output A regulated power supply output is provided in order to supply small devices from the module. The signal is present on Pad G6 and it is in common with the PWRMON (module powered ON indication) function. This output is always active when the module is powered ON. The operating range characteristics of the supply are: Item Min Typical Max Output voltage 1.7V 1.80V 1.9V Output current - - 60mA 1.
LE866 Hardware Design Guide VDDIO_IN Power Input VDDIO_IN is an input line used to supply the Digital section of LE866. The operating range characteristics of the external supply have to be: Item Min Typical Max Voltage 1.7V 1.80V 1.9V NOTE: If VDDIO_IN line is not powered (i.e. during the sleep states in PSM=2 when supplied by VAUX, during transition phases BOOT, RESET etc. and when the module is unsupplied) it is important to avoid back powering the digital pins.
LE866 Hardware Design Guide 3GPP Power Saving Mode (PSM) The LE866 is supporting a new feature introduced in 3GPP Rel.12 that allows the Module to skip idle mode tasks for a longer time period while still maintaining the NAS context. This feature permits to reduce the overall power consumption when there is no required data activity with the network for a long time. Additional hardware lines are defined to support this feature and to synchronize the activities with the external Host processor.
LE866 Hardware Design Guide 5. DIGITAL SECTION Logic Levels ABSOLUTE MAXIMUM RATINGS: Parameter Min Max Input level on any digital pin (CMOS 1.8) with respect to ground -0.3V VDDIO_IN +0.3V Min Max Input high level 1.55V 1.9V Input low level 0V 0.35V Output high level 1.35V 1.8V Output low level 0V 0.8V Input level on any digital pin (CMOS 1.8) with respect to ground OPERATING RANGE - INTERFACE LEVELS (1.
LE866 Hardware Design Guide Power On The LE866 will automatically power on itself when VBATT & VBATT_PA are applied to the module. VAUX / PWRMON pin will be then set at the high logic level.
LE866 Hardware Design Guide A flow chart showing the AT commands managing procedure is displayed below: “Start AT CMD” START Delay = 300 msec Enter AT AT answer in 1 sec ? N Disconnect PWR Supply Y GO TO “Modem ON Proc.” “Start AT CMD” END NOTE: In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the LE866 when the module is not supplied or during a reboot transition. 1VV0301355 Rev.
LE866 Hardware Design Guide Power Off The following flowchart shows the proper Turn-off procedure: “Modem OFF Proc” AT#SYSHALT 10s Timeout Disconnect PWR Supply “Modem ON Proc.” Delay 1.5s In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the LE866 when the module is powered off or during an ON/OFF transition. 1VV0301355 Rev.
LE866 Hardware Design Guide Unconditional Restart To unconditionally restart the LE866, the pad RESET* must be tied low for at least 200 milliseconds and then released. The maximum current that can be drained from the RESET* pad is 0,15 mA. The hardware unconditional Restart must not be used during normal operation of the device since it does not detach the device from the network.
LE866 Hardware Design Guide OPERATING LEVELS The RESET* line is connected to VBATT with a Pull Up so the electrical levels are on this pin are aligned to the main supply level. WARNING: The hardware unconditional Reset must not be used during normal operation of the device since it does not detach the device from the network. It shall be kept as an emergency exit procedure.
LE866 Hardware Design Guide In the following flow chart is detailed the proper restart procedure: Modem RESET Proc. RESET* = LOW Delay = 200ms RESET* = HIGH Delay = 38s Start At CMD NOTE: Do not use any pull up resistor on the RESET* line nor any totem pole digital output. Using pull up resistor may bring to latch up problems on the LE866 power regulator and improper functioning of the module.
LE866 Hardware Design Guide Fast System Turn Off The procedure to power off LE866 described in previous chapters normally takes more than 1 second to detach from network and make LE866 internal filesystem properly closed. In case of unwanted supply voltage loss the system can be switched off without any risk of filesystem data corruption by implementing Fast Syshalt feature. Fast Syshalt feature permits to reduce the current consumption and the time-to-poweroff to minimum values.
LE866 Hardware Design Guide The capacitor is rated with the following formula: NOTE: In case of power on with slow ramp-up of Vbatt supply voltage, RESET* line has to be used according to Power On diagram described in previous chapters. 5.5.2. Fast Shut Down by Software The Fast Power Down can be triggered by AT command. 1VV0301355 Rev.
LE866 Hardware Design Guide Communication ports 5.6.1. USB 2.0 HS The LE866 includes one integrated universal serial bus (USB 2.0 HS) transceiver. The following table is listing the available signals: PAD Signal I/O Function Type E5 USB_D+ I/O USB differential Data (+) 3.3V/100mV E6 USB_D- I/O USB differential Data (-) 3.3V/100mV The USB_DPLUS and USB_DMINUS signals have a clock rate of 480 MHz. The signal traces should be routed carefully.
LE866 Hardware Design Guide 5.6.2. Serial Ports The LE866 module is provided with by 2 Asynchronous serial ports: MODEM SERIAL PORT 1 (Main) MODEM SERIAL PORT 2 (Auxiliary) Several configurations can be designed for the serial port on the OEM hardware, but the most common are: RS232 PC com port microcontroller UART @ 1.8V (Universal Asynchronous Receive Transmit) microcontroller UART @ 5V or other voltages different from 1.
LE866 Hardware Design Guide 8 C105/RTS B1 Request to Send Input to the LE866 that controls the Hardware flow control 9 C125/RING B3 Ring Indicator Output from the LE866 that indicates the incoming call condition NOTE: According to V.
LE866 Hardware Design Guide 5.6.2.2. MODEM SERIAL PORT 2 (USIF1) The secondary serial port on the LE866 is a CMOS1.8V with only the RX and TX signals. The signals of the LE866 serial port are: PAD Signal I/O Function Type C1 TX_AUX O Auxiliary UART (TX Data to DTE) CMOS 1.8V C2 RX_AUX I Auxiliary UART (RX Data from DTE) CMOS 1.
LE866 Hardware Design Guide In order to translate the whole set of control lines of the UART you will need: 5 drivers 3 receivers An example of RS232 level adaptation circuitry could be done using a MAXIM transceiver (MAX218). In this case the chipset is capable to translate directly from 1.8V to the RS232 levels (Example done on 4 signals only). NOTE: Ensure to have the translator’s supply/enable synchronized with VDDIO_IN supply source.
LE866 Hardware Design Guide General purpose I/O The LE866 module is provided by a set of Configurable Digital Input / Output pins (CMOS 1.8V) Input pads can only be read; they report the digital value (high or low) present on the pad at the read time. Output pads can only be written or queried and set the value of the pad output. An alternate function pad is internally controlled by the LE866 firmware and acts depending on the function implemented.
LE866 Hardware Design Guide NOTE: The internal GPIO’s pull up/pull down could be set to the preferred status for the application using the AT#GPIO command. Please refer for the AT Commands User Guide for the detailed command Syntax. WARNING: During power up the GPIOs may be subject to transient glitches. 5.7.1.
LE866 Hardware Design Guide 5.7.2. Using a GPIO as OUTPUT The GPIO pads, when used as outputs, can drive 1.8V CMOS digital devices or compatible hardware. When set as outputs, the pads have a push-pull output and therefore the pull-up resistor may be omitted. 5.7.3. Indication of network service availability The STAT_LED pin status shows information on the network service availability and Call status.
LE866 Hardware Design Guide A schematic example could be: 5.7.4. SIMIN Detection All the GPIO pins can be used as SIM DETECT input. The AT Command used to enable the function is: AT#SIMINCFG Use the AT command AT#SIMDET=2 to enable the SIMIN detection Use the AT command AT&W0 and AT&P0 to store the SIMIN detection in the common profile. NOTE: Don’t use the SIM IN function on the same pin where the GPIO function is enabled and viceversa. 1VV0301355 Rev.
LE866 Hardware Design Guide External SIM Holder Please refer to the related User Guide (SIM Holder Design Guides, 80000NT10001a). ADC Converter The LE866 is provided by one AD converter. It is able to read a voltage level in the range of 0÷1.2 volts applied on the ADC pin input, store and convert it into 10 bit word. The input line is named as ADC_IN1 and it is available on Pad F4 The following table is showing the ADC characteristics: Item Min Typical Max Unit Input Voltage range 0 - 1.
LE866 Hardware Design Guide DAC Converter The LE866 provides a Digital to Analog Converter. The signal (named DAC_OUT) is available on pin E4 of the LE866. The on board DAC is a 10 bit converter, able to generate an analogue value based on a specific input in the range from 0 up to 1023. However, an external low-pass filter is necessary. The following table is showing the ADC characteristics: Item Min Max Unit Voltage range (filtered) 0 1.
LE866 Hardware Design Guide 5.10.2. LOW Pass filter Example 1VV0301355 Rev.
LE866 Hardware Design Guide 6. RF SECTION Antenna requirements 6.1.1. Main Antenna The antenna connection and board layout design are the most important aspect in the full product design as they strongly affect the product overall performances, hence read carefully and follow the requirements and the guidelines for a proper design.
LE866 Hardware Design Guide 6.1.2. PCB Design guidelines When using the LE866, since there's no antenna connector on the module, the antenna must be connected to the LE866 antenna pad by means of a transmission line implemented on the PCB. In the case the antenna is not directly connected at the antenna pad of the LE866, then a PCB line is needed in order to connect with it or with its connector.
LE866 Hardware Design Guide If you don't have EM noisy devices around the PCB of LE866, by using a micro strip on the superficial copper layer for the antenna line, the line attenuation will be lower than a buried one; The following image is showing the suggested layout for the Antenna pad connection (dimensions in mm): 6.1.3.
LE866 Hardware Design Guide The interface board is realized on a FR4, 4-layers PCB. Substrate material is characterized by relative permittivity εr = 4.6 ± 0.4 @ 1 GHz, TanD= 0.019 ÷ 0.026 @ 1 GHz. A characteristic impedance of nearly 50 Ω is achieved using trace width = 1.1 mm, clearance from coplanar ground plane = 0.3 mm each side. The line uses reference ground plane on layer 3, while copper is removed from layer 2 underneath the line. Height of trace above ground plane is 1.335 mm.
LE866 Hardware Design Guide Return Loss plot of line under test is shown below: Line input impedance (in Smith Chart format, once the line has been terminated to 50 Ω load) is shown in the following figure: 1VV0301355 Rev.
LE866 Hardware Design Guide Insertion Loss of G-CPW line plus SMA connector is shown below: 6.1.3.3. Antenna Installation Guidelines Install the antenna in a place covered by the LTE signal. If the device antenna is located farther than 20cm from the human body and there are no co-located transmitter then the Telit FCC/IC approvals can be re-used by the end product.
LE866 Hardware Design Guide Second Antenna requirements This product is including an input for a second RX antenna to improve the data throughput. The function is called Antenna Diversity (downlink MIMO) in LTE.
LE866 Hardware Design Guide 6.2.1. Single Antenna Operation In 4G LTE mode, 3GPP standard does not include single antenna operation because MIMO is the standard downlink configuration in this cellular system and because of reduced overall downlink performance when one or more neighbor cells are present.
LE866 Hardware Design Guide 7. AUDIO SECTION The Telit digital audio interface (DVI) of the LE910-V2 Module is based on the I2S serial bus interface standard. The audio port can be directly connected to end device using digital interface, or via one of the several compliant codecs (in case an analog audio is needed).
LE866 Hardware Design Guide 8. MECHANICAL DESIGN Drawing NOTE: The dimensions are in mm 1VV0301355 Rev.
LE866 Hardware Design Guide 9. APPLICATION PCB DESIGN The LE866 modules have been designed in order to be compliant with a standard leadfree SMT process. Footprint Units: mm General Tolerance +- 0.05 Angular Tolerance +-1° In order to easily rework the LE866 is suggested to consider on the application a 1.5 mm placement inhibit area around the module. It is also suggested, as common rule for an SMT component, to avoid having a mechanical part of the application in direct contact with the module.
LE866 Hardware Design Guide PCB pad design Non solder mask defined (NSMD) type is recommended for the solder pads on the PCB.
LE866 Hardware Design Guide Inhibit area for micro-via Holes in pad are allowed only for blind holes and not for through holes. Recommendations for PCB pad surfaces: Finish Layer Thickness (um) Electro-less Ni / Immersion Au 3 –7 / 0.05 – 0.15 Properties good solder ability protection, high shear force values The PCB must be able to resist the higher temperatures which are occurring at the leadfree process. This issue should be discussed with the PCB-supplier.
LE866 Hardware Design Guide Solder paste Item Lead Free Solder Paste Sn/Ag/Cu We recommend using only “no clean” solder paste in order to avoid the cleaning of the modules after assembly. Solder Reflow Recommended solder reflow profile: 1VV0301355 Rev.
LE866 Hardware Design Guide Profile Feature Pb-Free Assembly Average ramp-up rate (TL to TP) 3°C/second max Preheat – Temperature Min (Tsmin) 150°C – Temperature Max (Tsmax) 200°C – Time (min to max) (ts) 60-180 seconds Tsmax to TL – Ramp-up Rate 3°C/second max Time maintained above: – Temperature (TL) 217°C – Time (tL) 60-150 seconds Peak Temperature (Tp) 245 +0/-5°C Time within 5°C of actual Peak 10-30 seconds Temperature (tp) Ramp-down Rate 6°C/second max.
LE866 Hardware Design Guide 10. PACKAGING Tray The LE866 modules are packaged on trays of 70 pieces each. These trays can be used in SMT processes for pick & place handling. 1VV0301355 Rev.
LE866 Hardware Design Guide 1VV0301355 Rev.
LE866 Hardware Design Guide Moisture sensitivity The LE866 is a Moisture Sensitive Device level 3, in according with standard IPC/JEDEC J-STD-020, take care all the relatives requirements for using this kind of components. Moreover, the customer has to take care of the following conditions: a) Calculated shelf life in sealed bag: 12 months at <40°C and <90% relative humidity (RH). b) Environmental condition during the production: 30°C / 60% RH according to IPC/JEDEC J-STD-033A paragraph 5.
LE866 Hardware Design Guide 11. CONFORMITY ASSESSMENT ISSUES Approvals GCF (LE866-SV1) PTCRB (LE866A1-NA) FCC, IC (LE866A1-NA, LE866-SV1) KC (LE866A1-KK, LE866A1-KS) JRL (a.k.a. TELEC) / JTBL (a.k.a. JATE) (LE866A1-JS) RoHS and REACH (all versions) Approvals for major Mobile Network Operators Declaration of Conformity The DoC is available here: http://www.telit.com/RED/ FCC certificates The FCC Certificate is available here: https://www.fcc.
LE866 Hardware Design Guide Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes : (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
LE866 Hardware Design Guide television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate the receiving antenna. Increase the separation between the equipment and receiver. Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. Consult the dealer or an experienced radio/TV technician for help.
LE866 Hardware Design Guide 12. SAFETY RECOMMENDATIONS READ CAREFULLY Be sure the use of this product is allowed in the country and in the environment required. The use of this product may be dangerous and has to be avoided in the following areas: Where it can interfere with other electronic devices in environments such as hospitals, airports, aircrafts, etc. Where there is risk of explosion such as gasoline stations, oil refineries, etc.
LE866 Hardware Design Guide 13. REFERENCE TABLE OF RF BANDS CHARACTERISTICS Mode Freq. Tx (MHz) Freq. Rx (MHz) Channels Tx-Rx Offset PCS 1900 1850.2 ~ 1909.8 1930.2 ~ 1989.8 512 ~ 810 80 MHz DCS 1800 1710 ~ 1785 1805 ~ 1880 512 ~ 885 95 MHz GSM 850 824.2 ~ 848.8 869.2 ~ 893.
LE866 Hardware Design Guide Mode LTE 1900 – B2 Freq. Tx (MHz) Freq.
LE866 Hardware Design Guide Mode Freq. Tx (MHz) Freq.
LE866 Hardware Design Guide 14.
LE866 Hardware Design Guide MISO Master Input – Slave Output CLK Clock MRDY Master Ready SRDY Slave Ready CS Chip Select RTC Real Time Clock PCB Printed Circuit Board ESR Equivalent Series Resistance VSWR Voltage Standing Wave Radio VNA Vector Network Analyzer 1VV0301355 Rev.
LE866 Hardware Design Guide 15. DOCUMENT HISTORY Revision Date Changes 0 2017-02-06 First issue This document replaces the LE866 HW User Guide Doc# 1VV0301210. 1VV0301355 Rev.
[01.2017] Mod.0818 2017-01 Rev.
