TOBY-L3 series Multi-mode LTE (Cat 4) modules with 3G and 2G fallback System Integration Manual 35.6 x 24.8 x 2.6 mm LTE Module Abstract This document describes the features and the system integration of TOBY-L3 series multi-mode cellular modules. The modules are a complete and cost efficient LTE-FDD, LTE-TDD, DC-HSPA+, (E)GPRS multimode and multi-band solution with open CPU embedded Linux programming capability.
TOBY-L3 series - System Integration Manual Document Information Title TOBY-L3 series Subtitle Multi-mode LTE (Cat 4) modules with 3G and 2G fallback Document type System Integration Manual Document number TSD-19090601 Revision and date R15 03-Nov-2022 Disclosure Restriction Product status Corresponding content status Functional Sample Draft For functional testing. Revised and supplementary data will be published later. In Development / Objective Specification Target values.
TOBY-L3 series - System Integration Manual Contents Contents...................................................................................................................................................... 3 1 System description ............................................................................................................................ 7 1.1 Overview .......................................................................................................................................
TOBY-L3 series - System Integration Manual 1.14 Reserved pins (RSVD) ............................................................................................................................................................... 53 1.15 System features ........................................................................................................................................................................... 53 1.15.1 Network indication ..........................................................
TOBY-L3 series - System Integration Manual 2.6.4 DDC (I2C) interfaces ..................................................................................................................................................... 100 2.6.5 SDIO interface ................................................................................................................................................................. 106 2.6.6 SGMII interface ..........................................................................
TOBY-L3 series - System Integration Manual 3.3.6 Wave soldering .............................................................................................................................................................. 127 3.3.7 Hand soldering ............................................................................................................................................................... 127 3.3.8 Rework ..................................................................................
TOBY-L3 series - System Integration Manual 1 System description 1.1 Overview The TOBY-L3 series modules support multi-band LTE-FDD, LTE-TDD, DC-HSPA+, and (E)GPRS radio access technologies in the very small TOBY 248-pin LGA form-factor (35.6 x 24.8 x 2.6 mm), which is easy to integrate in compact designs.
TOBY-L3 series - System Integration Manual Table 1summarizes the main features and interfaces of the TOBY-L3 series modules. 1,3,7,8, 20, 1,8 28,38 APAC / TOBY-L3204-50A-00 South. American TOBY-L3404-50A-00 North.
TOBY-L3 series modules provide multi-band 4G / 3G / 2G multi-mode radio access technologies, based on the 3GPP Release 10 protocol stack, with main characteristics summarized in Table 2 and Table 3.
TOBY-L3414-50A-00 North America 2 (1900 MHz) 41 (2500 MHz) 4 (1700 MHz) 2 (1900 MHz) PCS 1900 4 (1700 MHz) 7 (2600 MHz) 12 (700 MHz) 13 (700 MHz) 66 (1700 MHz) 71 (600 MHz) TOBY-L3904-50A-00 China / 1 (2100 MHz) 38 (2600 MHz) 1 (2100 MHz) E-GSM 900 India / 3 (1800 MHz) 39 (1900 MHz) 6 (800 MHz) DCS 1800 Japan 5 (850 MHz) 40 (2300 MHz) 8 (900 MHz) 8 (900 MHz) 41 (2500 MHz) 19 (850 MHz) 1 (2100 MHz) 38 (2600 MHz) 1 (2100 MHz) E-GSM 900 3 (1800 MHz) 39 (1900 MHz) 8 (900 MHz) D
1.2 Architecture RF section The RF section is composed of an RF transceiver, PAs, crystal oscillator, filters, duplexers and RF switches. The Tx signal is pre-amplified by the RF transceiver, then output to the primary antenna input/output port (ANT1) of the module via power amplifier (PA), SAW band pass filters band, specific duplexer and antenna switch.
Low power idle mode support 1.3 Pin-out Table 4 lists the pin-out of the TOBY-L3 series modules, with pins grouped by function. Function Pin Name Pin No I/O Description Remarks Power VCC 70,71,72 I Module supply input VCC supply circuit affects the RF performance and compliance of the device integrating the module with applicable required certification schemes. See section 1.5.1 for functional description / requirements. See section 2.2.1 for external circuit design-in.
Function Pin Name Pin No I/O Description Remarks Antennas ANT1 81 I/O Primary antenna Main Tx / Rx antenna interface. 50 nominal characteristic impedance. Antenna circuit affects the RF performance and application device compliance with required certification schemes. See section 1.7.1 for functional description / requirements. See section 2.4 for external circuit design-in. ANT2 87 I Secondary antenna Rx only for Down-Link, MIMO and Rx diversity. 50 nominal characteristic impedance.
Function Pin Name Pin No I/O Description Remarks USB_D+ 28 I/O USB High-Speed 2.0 90 nominal differential impedance (Z0). diff. transceiver (+) 30 nominal common mode impedance (ZCM). Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 specs [4] are part of the USB pin driver and need not be provided externally. Test-Point for diagnostic / FW update access is recommended. See section 1.9.1 for functional description. See section 2.6.
Function Pin Name Pin No I/O Description Remarks TXD1 159 I/ UART1 data input / 1.8 V input, Circuit 103 (TXD) in ITU-T V.24, I/ SPI2 MISO / alternatively configurable as SPI2 MISO, I2S1 Receive Data In I/ I2S1 Receive Data In / or PCM1 Data In by open CPU API or AT command. I PCM1 Data In Internal pull-up to V_INT enabled when UART1 data input. See section 1.9.2 / 1.9.2.3 for functional description. See section 2.6.2 / 2.6.3 for external circuit design-in.
Function Pin Name Pin No I/O Description Remarks SPI_SCLK 179 O/ SPI0 Shift Clock / 1.8 V, SPI0 clock. O UART4 Clear To Send Alternatively configurable as UART4 Clear To Send by Open CPU or AT Command. See section 1.9.3.1 for functional description. See section 2.6.3 for external circuit design-in. SPI_CS 173 O/ SPI0 Chip Select 0 / 1.8 V, SPI0 chip select 0. I UART4 Ready To Send Alternatively configurable as UART4 Ready To Send by Open CPU or AT Command. See section 1.9.3.
Function Pin Name Pin No I/O Description Remarks Ethernet V_ETH 221 O Ethernet Interface Ethernet SGMII interface supply output. supply output See section 1.9.6 for functional description. See section 2.6.6 for external circuit design-in. ETH_RST_N 33 O Ethernet PHY reset SGMII: Ethernet PHY reset signal. signal See section 1.9.6 for functional description. See section 2.6.6 for external circuit design-in.
Function Pin Name Pin No I/O Description Remarks MMC_CMD 215 I/O Multi-Media Card Embedded Multi-Media / SD Card memory command. Command See section 1.10 for functional description. See section 2.7 for external circuit design-in. MMC_CLK 216 O Multi-Media Card Clock Embedded Multi-Media / SD Card memory clock. See section 1.10 for functional description. See section 2.7 for external circuit design-in. MMC_RST_N 211 O Multi-Media Card Reset Embedded Multi-Media / SD Card memory reset.
Function Pin Name Pin No I/O Description Remarks GPIO3 24 I/O GPIO 1.8 V GPIO with alternatively configurable functions. Configurable as External Interrupt by open CPU API. See section 1.13 for functional description. See section 2.10 for external circuit design-in. GPIO4 25 I/O GPIO 1.8 V GPIO with alternatively configurable functions. Configurable as SPI0 Chip Select 1 by open CPU API. See sections 1.13, 1.9.2.3 for functional description. See sections 2.10, 2.6.
1.4 Operating modes TOBY-L3 series modules have several operating modes. The operating modes are defined in Table 5 and described in detail in Table 6, provding general guidelines for operation. General Status Operating Mode Definition Power-down Not-Powered Mode VCC supply not present and the module is switched off. Power-Off mode VCC supply within operating range and modules is switched off.
The modules switch from active mode to download mode before starting the firmware downloading procedure, once the firmware downloading is finished, the system reboot and enter booting mode. Sleep-Mode Module is switched on with application The modules automatically switch from active-mode to low power interfaces temporarily disabled or sleep-mode whenever possible if power saving is enabled.
Not powered Apply VCC power supply Remove VCC power supply Switch ON with the Pin TX2 pull up to high Power off Switch ON: 1). PWR_ON Switch OFF: 1). AT+CPWROFF 2). RESET_N (hardware reset) 3).
1.5 Supply interfaces 1.5.1 Module supply input (VCC) The modules must be supplied via the three VCC pins that represent the module power supply input.
functional until the VCC voltage is inside the extended operating range limits. VCC average current Support with adequate margin the The maximum average current consumption can be greater than highest averaged VCC current the specified value according to the actual antenna mismatching, consumption value in connected mode temperature and supply voltage. conditions Sections 1.5.1.2, 1.5.1.3 and 1.5.1.4 describe the current consumption profiles in 2G, 3G and LTE connected modes.
Figure shows an example of the module current consumption profile versus time in 2G single-slot mode. Current [A] 2.5 1900 m A 2.0 1.5 Peak current depends on TX power and act ual ant enna load 1.0 0.5 200 m A 60-120 m A 0.0 RX slot 60-120 m A 10-40 m A unused unused slot slot TX slot unused unused M ON unused slot slot slot slot RX slot unused unused slot slot GSM f ram e 4.615 m s (1 f ram e = 8 slot s) TX slot unused unused M ON unused slot slot slot slot GSM f ram e 4.
Figure reports the current consumption profiles in GPRS class 12 connected mode, in the 850 or 900 MHz bands, with 4 slots used to transmit and 1 slot used to receive. It must be noted that the actual current consumption of the module in 2G connected mode depends also on the specific concurrent activities performed by the integrated CPU, beside the actual Tx power and antenna load. Current [A] 2.5 1600 m A 2.0 1.5 Peak current depends on TX power and act ual ant enna load 1.0 0 .
It must be noted that the actual current consumption of the module in 3G connected mode depends also on the specific concurrent activities performed by the integrated CPU, beside the actual Tx power and antenna load.
It must be noted that the actual current consumption of the module in LTE connected mode depends also on the specific concurrent activities performed by the integrated CPU, beside the actual Tx power and antenna load. Current [mA] 90 0 80 0 70 0 60 0 Current consum pt ion value depends on TX power and act ual ant enna load 50 0 40 0 30 0 20 0 10 0 0 1 Slot 1 Resource Block (0.
In LTE, the paging period can vary from 320 ms (DRX = 5, i.e. length of 2 5 LTE frames = 32 x 10 ms) up to 2560 ms (DRX = 8, length of 28 LTE frames = 256 x 10 ms). Figure illustrates a typical example of the module current consumption profile when power saving is enabled. The module is registered with the network, automatically enters the low power idle mode and periodically wakes up to active mode to monitor the paging channel for the paging block reception.
Current [mA] 20 0 10 0 0 Current [mA] Time [s] Paging period 2G case: 0 .44-2.0 9 s 3G case: 0 .61-5.0 9 s LTE case: 0 .32-2.56 s 20 0 10 0 0 Time [ms] RX Enabled ACTIVE M ODE Figure 9: VCC current consumption profile with low power mode disabled and module registered with the network: active mode is always held and the receiver is periodically activated to monitor the paging channel for paging block reception 1.5.
1.6 System function interfaces 1.6.1 Module power-on TOBY-L3 series modules can be switched on in the following way: Low pulse on the PWR_ON pin, which is normally set high by an internal pull-up, for a valid time period, when the applied VCC voltage is stable at its nominal value within normal operating range. As shown in Figure 2, the TOBY-L3 series PWR_ON input is equipped with an internal active pull-up resistor to an internal 1.
Figure 3 shows the module power-on sequence, describing the following phases: The VCC module supply is stable at its nominal value within the normal operating range The PWR_ON input pin is set low for a valid time period, representing the switch-on event.
☞ The duration of the TOBY-L3 series modules’ switch-on routine can largely vary depending on the application / network settings and any concurrent module activities. ⚠ It is highly recommended to avoid an abrupt removal of the VCC supply and/or performing an abrupt emergency shutdown procedure during TOBY-L3 series modules’ switch-on routine. 1.6.
Figure 4 describes the TOBY-L3 series modules’ proper normal switch-off sequence started by means of the +CPWROFF AT command, allowing storage of current parameter settings in module’s non-volatile memory and a clean network detach, with the following phases The +CPWROFF AT command is sent to the module by the external application: the module starts the switch-off routine Then, the module replies OK on the AT interface: the switch-off routine is in progress At the end of the switch-off routine, all th
Figure 5 describes the TOBY-L3 series modules’ proper normal switch-off sequence started by means of the PWR_ON input pin, allowing storage of current parameter settings in the module’s non-volatile memory and a clean network detach, with the following phases A low pulse with the appropriate time duration is applied at the PWR_ON input (see TOBY-L3 series Data Sheet [1], normal graceful switch-off), which is normally set high by an internal pull-up: the module starts the switch-off routine when the PWR_ON
reboot command on the Linux shell4 The methods listed above represent appropriate reset (reboot) events, triggering an appropriate “internal” or “software” reset of the module: the current parameter settings are saved in the module’s non-volatile memory and a clean network detach is performed. An abrupt hardware reset occurs on TOBY-L3 series modules when a low level is applied on the RESET_N input pin.
1.7 Antenna interfaces 1.7.1 Antenna RF interfaces (ANT1 / ANT2) TOBY-L3 series modules provide two RF interfaces for connecting the external antennas for 4G/3G/2G network: ANT1 represents the primary RF input/output for transmission and reception of RF signals. ANT1 pin has a nominal characteristic impedance of 50 and must be connected to the primary Tx / Rx antenna through a 50 transmission line to allow clean RF transmission and reception.
Item Requirements Remarks Radiated Power (TRP) and the Total Isotropic Sensitivity (TIS), specified by applicable related certification schemes. Maximum Gain According to radiation exposure The power gain of an antenna is the radiation efficiency multiplied by the limits directivity: the gain describes how much power is transmitted in the direction of peak radiation to that of an isotropic source.
The radiation efficiency of the secondary antenna needs to be roughly the same as the radiation efficiency of the primary antenna for good RF performance. Envelope < 0.4 recommended The Envelope Correlation Coefficient (ECC) between the primary (ANT1) Correlation < 0.5 acceptable and the secondary (ANT2) antenna is an indicator of 3D radiation pattern Coefficient similarity between the two antennas: low ECC results from antenna patterns with radiation lobes in different directions.
High-speed SIM/ME interface and the PPS procedure for baud-rate selection is implemented according to the values proposed by the SIM card/chip. The VSIM supply output provide internal short circuit protection to limit the start-up current and protect the SIM from short circuits. 1.8.2 SIM detection interface The GPIO5 pin of TOBY-L3 series modules can be configured to detect the mechanical / physical presence of an external SIM card connected to the SIM interface.
UART interfaces (see section 1.9.2): o UART0 interface, providing: Can be configured as SPI (SPI1) interface by open CPU API or AT commands alternatively. Communication with external serial devices by means of open CPU API or AT commands. o UART1 interface, providing: Can be configured as I2S (I2S1), PCM (PCM1) or SPI (SPI2) interface by open CPU API or AT commands alternatively. Communication with external serial devices by means of open CPU API or AT commands.
The USB High-Speed 2.0 compliant interface consists of the following pins: USB_D+/USB_D–, USB High-Speed differential data lines as per USB 2.0 specification [4] VUSB_DET input pin, which senses the VBUS rail presence (nominally 5 V at the source) to detect the host connection and enable the USB 2.0 interface with the module acting as a USB device.
Ring Indicator functionality, over the following pin: o RI module output line The UART0 interface can operate at 4.8kbit/s, 9.6kbit/s, 19.2kbit/s, 38.4kbit/s, 57.6kbit/s, 115.2kbit/s, 230.4kbit/s, 1Mbit/s, 3Mbit/s, 4Mbit/s baud rates, with 8N1 frame format (illustrated in Figure 7), and with hardware flow control output (CTS line) driven to the OFF state when the module is not prepared to accept data by the UART0 interface.
The RI line can notify an incoming call: the line is switched from the OFF state to the ON state with a 4:1 duty cycle and a 5 s period (ON for 1 s, OFF for 4 s, see Figure 8), until the DTE attached to the module sends the ATA string and the module accepts the incoming data call. The RING string sent by the module (DCE) to the serial port at constant time intervals is not correlated with the switch of the Ring Indicator line to the ON state.
The RI function can be alternatively configured by GPIO by an AT command. 120ms RI OFF RI ON 0 time [s] Wake up host Figure 19: RI behavior at wake up host in mode 2 As described in Figure , the RI line can wake up the external host after configured the pin as mode 2 by AT command.
4-wire UART Mode (UART1) SPI Mode (SPI2) I2S Mode (I2S1) PCM Mode (PCM1) RXD1 (Module output); SPI2_MOSI; I2S1_WA; PCM1_SYNC; UART1 Receive Data SPI2 MOSI Pin (Module Output) I2S1 Word alignment PCM1 Frame Sync TXD1 (Module Input); SPI2_MISO; I2S1_RXD; PCM1_DIN; UART1 Transmit Data SPI2 MISO Pin (Module Input) I2S1 Receive Data In PCM1 Data In CTS1 (Module Output); SPI2_CLK; I2S1_CLK; PCM1_CLK; UART1 Clear To Send SPI2 Clock Pin (Module Output) I2S Serial Clock PCM1 Clock RTS1 (M
1.9.3 SPI interfaces 1.9.3.1 SPI0 interface The SPI0 1.
dedicated DDC (I2C) interface. An interface connected to the positioning device is not necessary: the cellular module allows full control of the GNSS device. The modules provide embedded GNSS aiding that is a set of specific features developed by u-blox to improve the cellular / GNSS system power consumption and the GNSS performance, decreasing the TimeTo-First-Fix (TTFF), thus allowing to calculate the position in shorter time with higher accuracy.
Tashang has implemented special features in the cellular modules to ease the design effort for the integration of the TOBY-L3 cellular module with a u-blox short range radio communication module, to provide Router functionality. The cellular modules provide additional custom functions over GPIO pins to improve the integration with u-blox short range radio communication modules (see section 1.13).
1.10 eMMC interface TOBY-L3 series modules include a 4-bit embedded Multi-Media Card interface compliant with the JESD84B451 Embedded Multimedia Card (eMMC) Electrical Standard 4.51 [9].
1.11 Digital Audio interfaces TOBY-L3 series modules provide a 4-wire I2S digital audio interface: I2S digital audio interface, consisting of the following pins: o I2S_TXD data output o I2S_RXD data input o I2S_CLK bit clock input/output o I2S_WA world alignment / synchronization signal input/output The I2S0 digital audio interfaces is suitable to transfer digital audio data with an external compatible digital audio device, as an audio codec or as an audio digital signal processor.
The modules support I2S transmit and I2S receive data 16-bit words long, linear. Data is transmitted and read in 2’s complement notation. The MSB is transmitted and read first. I2S clock signal frequency depends on the frame length, the sample rate and the selected mode of operation: 17 x or 18 x in PCM mode (short synchronization signal) 16 x 2 x in Normal I2S mode (long synchronization signal) 1.
Function Description Default Configurable GPIOs Wake-up Wi-Fi Wake-up the Wi-Fi module from sleep mode GPIO1 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, HOST_SELECT0, HOST_SELECT1, RI WWAN Status Indicator the status of WWAN.
Network searching Registered the network Data transfer is on going Voice call is on going Mode Output Status Mode 1 Mode 2 Mode 3 Mode 4 Remarks Network indication function is disabled. (Default configuration mode) Blink slowly (200ms High/1800ms Low) Network is on searching. Blink slowly (1800ms High/200ms Low) The module has registered on the network and work in idle state. Blink quickly (125ms High/125ms Low) The module has registered on the network with data transfer is ongoing.
Bridge mode: In bridge mode the module acts as a cellular modem dongle connected to the host over serial interface. The IP termination of the network is placed on the host IP stack. The module is configured as a bridge which means the network IP address is assigned to the host (host IP termination). Router mode: In router mode the module acts as a cellular modem router which means the IP termination of the network is placed on the Internal IP stack of the module (on-target IP termination).
For more details about the embedded FTP and FTPS functionalities, see the TOBY-L3 series AT commands manual [2]. 1.15.
The +UFWUPD AT command triggers a reboot followed by the upgrade procedure at specified a baud rate. A special boot loader on the module performs firmware installation, security verifications and module reboot. Firmware authenticity verification is performed via a security signature during the download. The firmware is then installed, overwriting the current version. In case of power loss during this phase, the boot loader detects a fault at the next wake-up, and restarts the firmware downloaded.
The GNSS data ready pin trigger the interruption Other interruption pin have the interrupt input signal For the definition and the description of TOBY-L3 series modules operating modes, including the events forcing transitions between the different operating modes.
2 Design-in 2.1 Overview For optimal integration of the modules in the application PCB, follow the design guidelines stated in this section. Every application circuit must be properly designed to guarantee the correct functionality of the relative interface, but a number of points require greater attention during the design of the application device. The following list provides a rank of importance in the application design, starting with the most significant: 1.
9. Other digital interfaces: (UART, SPI, I2C, I2S, Host Select, GPIOs, and Reserved pins). Accurate design is required to guarantee correct functionality and reduce the risk of digital data frequency harmonics coupling. Follow the suggestions provided in sections 2.6.1, 2.6.3, 2.6.4, 2.3.3, 2.10, 2.11. 10. Other supplies: V_INT is generic digital interface supply. Correct design is required to guarantee functionality. Follow the suggestions provided in 2.2.2.
Main Supply Available? No, portable device Battery Li-Ion 3.7 V Yes, always available Main Supply Voltage > 4.2V? No, less than 4.2 V Linear LDO Regulator Yes, greater than 4.2 V Switching StepDown Regulator Figure 10: VCC supply concept selection The switching step-down regulator is the typical choice when the available primary supply source has a nominal voltage much higher (e.g. greater than 4.2 V) than the operating supply voltage of TOBY-L3 series.
The usage of more than one DC supply at the same time should be evaluated carefully: depending on the supply source characteristics, different DC supply systems can result as mutually exclusive. The usage of a regulator or a battery not able to support the highest peak of VCC current consumption specified in the TOBY-L3 series Data Sheet [1] is generally not recommended.
Figure 11 and Table 18 show an example of a high reliability power supply circuit, where the module VCC input is supplied by a step-down switching regulator capable of delivering maximum current with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz.
2.2.1.3 Guidelines for VCC supply circuit design using a LDO linear regulator The use of a linear regulator is suggested when the difference from the available supply rail source and the VCC value is low. The linear regulators provide high efficiency when transforming a 5 VDC supply to a voltage value within the module VCC normal operating range.
R3 3.9 k Resistor 0402 5% 0.1 W RC0402JR-073K9L - Yageo Phycomp U1 LDO Linear Regulator ADJ 3.0 A LT1764AEQ#PBF - Linear Technology Table 19: Components for high reliability VCC supply application circuit using an LDO linear regulator ☞ See section 2.2.1.6, in particular Figure 13 / Table 20, for the additional parts recommended for noisesensitive applications and/or for applications with antenna(s) placed close to the module. 2.2.1.
2.2.1.6 Additional guidelines for VCC supply circuit design To reduce voltage drops, use a low impedance power source. The series resistance of the supply lines (connected to modules’ VCC and GND pins) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible to minimize losses. Three pins are allocated to the VCC supply. Several pins are designated for GND connection.
Table 20: Suggested components to reduce ripple / noise on the VCC ☞ The necessity of each part depends on the specific design, but it is recommended to provide all the bypass capacitors illustrated in Figure 13 / Table 20 for noise-sensitive applications and/or if the enddevice integrates an internal antenna. ☞ The ESD sensitivity rating of the VCC supply pins is 1 kV (HBM as per JESD22-A114). A higher protection level can be required if the line is externally accessible on the application board, e.g.
Li-Ion/Li-Polymer Battery Charger IC TOBY-L3 series 5V0 USB Supply VIN VOUT 70 VCC 71 VCC 72 VCC VINSNS VOSNS MODE R1 R2 R3 Li-Ion/Li-Pol Battery Pack VREF ISEL C3 IUSB IAC R4 C4 TH + θ IEND C5 C6 C7 C8 C9 TPRG SD C1 B1 GND C2 U1 GND D1 D2 Figure 14: Li-Ion (or Li-Polymer) battery charging application circuit Reference Description Part Number - Manufacturer B1 Li-Ion (or Li-Polymer) battery pack with 470 NTC Various manufacturer C1, C4 1 µF Capacitor Ceramic X7R 0603 10% 1
A power management IC should meet the following prerequisites to comply with the module’s VCC requirements as summarized in Table 7: High efficiency internal step down converter, compliant with features specified in section 2.2.1.
Pre-charge constant current (active when the battery is deeply discharged): the battery is charged with a low current, set to 10% of the fast-charge current. Fast-charge constant current: the battery is charged with the maximum current, configured by the value of an external resistor to a value suitable for the application. Constant voltage: when the battery voltage reaches the regulated output voltage (4.2 V), the current is progressively reduced until the charge termination is done.
D1, D2 Low Capacitance ESD Protection CG0402MLE-18G - Bourns D3 Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor R1, R3, R5, R7 10 k Resistor 0402 1% 1/16 W Generic manufacturer R2 1.05 k Resistor 0402 1% 0.1 W Generic manufacturer R4 22 k Resistor 0402 1% 1/16 W Generic manufacturer R6 26.5 k Resistor 0402 1% 1/16 W Generic manufacturer L1 2.2 µH Inductor 7.
Reference Description Part Number - Manufacturer R1 47 k Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp R2 10 k Resistor 0402 5% 0.1 W RC0402JR-0710KL - Yageo Phycomp R3 100 k Resistor 0402 5% 0.1 W RC0402JR-07100KL - Yageo Phycomp T1 P-Channel MOSFET Low On-Resistance AO3415 - Alpha & Omega Semiconductor Inc. T2 NPN BJT Transistor BC847 - Infineon C1 330 µF Capacitor Tantalum D_SIZE 6.
noise rejection in the band centered on the Self-Resonant Frequency of the pF capacitors. This is highly recommended if the application device integrates an internal antenna. Since VCC input provides the supply to the RF Power Amplifiers, any voltage ripple at high frequency may result in unwanted spurious modulation of the transmitter RF signal.
Pull-up SIM detection signal (see section 2.5 for more details) Supply voltage translators to connect 1.8 V module generic digital interfaces to 3.0 V devices (e.g. see section 2.6.1 for more details) Pull-up DDC (I2C) interface signals (see section 2.6.4 for more details) Supply a 1.8 V u-blox GNSS device (see section 2.6.4 for more details) Enable external voltage regulators providing supply for external devices, as linear LDO regulators providing the 3.3 V / 1.
2.3 System functions interfaces 2.3.1 Module power-on (PWR_ON) 2.3.1.1 Guidelines for PWR_ON circuit design TOBY-L3 series PWR_ON input is equipped with an internal active pull-up resistor to an internal 1.3 V supply rail as shown in Figure 18: an external pull-up resistor is not required and should not be provided. If connecting the PWR_ON input to a push button, the pin will be externally accessible on the application device.
2.3.1.2 Guidelines for PWR_ON layout design The power-on circuit (PWR_ON) requires careful layout since it is the sensitive input available to switch on the TOBY-L3 series modules. It is required to ensure that the voltage level is well defined during operation and no transient noise is coupled on this line, otherwise the module might detect a spurious power-on request. 2.3.2 Module reset (RESET_N) 2.3.2.
☞ If the external reset function is not required by the customer application, the RESET_N pin can be left unconnected to external components, but it is recommended to provide direct access on the application board by means of an accessible test point directly connected to the RESET_N pin. 2.3.2.
2.4 Antenna interface TOBY-L3 series modules provide two RF interfaces for connecting the external antennas: The ANT1 pin represents the primary RF input/output for RF signals transmission and reception. The ANT2 pin represents the secondary RF input for MIMO and Rx diversity RF signals reception.
can be radiated. Therefore, the ground plane can be reduced down to a minimum size that should be similar to the quarter of the wavelength of the minimum frequency that must be radiated, given that the orientation of the ground plane relative to the antenna element must be considered. The isolation between the primary and the secondary antennas must be as high as possible and the correlation between the 3D radiation patterns of the two antennas must be as low as possible.
Correct transition between ANT1 / ANT2 pads and application board must be provided, implementing the following design-in guidelines for the application PCB layout close to the ANT1 / ANT2 pads: On a multilayer board, the whole layer stack below the RF connection should be free of digital lines. Increase GND keep-out (i.e.
5 0 0 um 3 8 0 um 5 0 0 um L1 Copper 3 5 um FR-4 dielect ric 270 um L2 Copper 3 5 um FR-4 dielect ric 760 um L3 Copper 3 5 um FR-4 dielect ric 270 um L4 Copper 3 5 um Figure 20: Example of a 50 coplanar waveguide transmission line design for the described 4-layer board layup 40 0 um 120 0 um 40 0 um L1 Copper 3 5 um FR-4 dielect ric 15 10 um L2 Copper 3 5 um Figure 21: Example of a 50 coplanar waveguide transmission line design for the described 2-layer board layup If the two examp
Additionally to the 50 impedance, the following guidelines are recommended for transmission line design: Minimize the transmission line length: the insertion loss should be minimized as much as possible, in the order of a few tenths of a dB. Add GND keep-out (i.e. clearance, a void area) on buried metal layers below any pad of a component present on the RF transmission lines, if the top-layer to buried layer dielectric thickness is below 200 µm, to reduce parasitic capacitance to ground.
Guidelines for RF termination design RF terminations must provide a characteristic impedance of 50 as well as the RF transmission lines up to the RF terminations themselves, to match the characteristic impedance of the ANT1 / ANT2 ports of the modules. However, real antennas do not have a perfect 50 load on all the supported frequency bands.
Place the antennas far from sensitive analog systems or employ countermeasures to reduce EMC issues. Take care of interaction between co-located RF systems since the LTE/3G/2G transmitted power may interact or disturb the performance of companion systems. Place the two LTE antennas providing low Envelope Correlation Coefficient (ECC) between the primary (ANT1) and secondary (ANT2) antenna: the antenna 3D radiation patterns should have lobes in different directions.
120.2 x 50.4 mm Taoglas FXUB70.A.07.C.001 GSM / WCDMA / LTE PCB MIMO Antenna with cables and U.FL 698..960 MHz, 1575.42 MHz, 1710..2170 MHz, 2400..2690 MHz 182.2 x 21.2 mm EAD FSQS35241-UF-10 SQ7 GSM / WCDMA / LTE PCB Antenna with cable and U.FL 690..960 MHz, 1710..2170 MHz, 2500..2700 MHz 110.0 x 21.0 mm Ethertronics 5001537 Prestta GSM / WCDMA / LTE PCB Antenna with cable 704..960 MHz, 1710..2170 MHz, 2300..2400 MHz, 2500..2690 MHz 80.0 x 18.
2.4.2 Antenna detection interface (ANT_DET) 2.4.2.1 Guidelines for ANT_DET circuit design Figure 23 and Table 29 describe the recommended schematic / components for the antennas detection circuit that must be provided on the application board and for the diagnostic circuit that must be provided on the antennas’ assembly to achieve primary and secondary antenna detection functionality.
Additional components (R1, C1 and D1 in Figure 23) are needed at the ANT_DET pin as ESD protection. The ANT1 / ANT2 pins must be connected to the antenna connector by means of a transmission line with a nominal characteristic impedance as close as possible to 50 . The DC impedance at the RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna).
2.4.2.2 Guidelines for ANT_DET layout design The recommended layout for the primary antenna detection circuit to be provided on the application board to achieve the primary antenna detection functionality, implementing the recommended schematic illustrated in Figure 23 and Table 29, is explained here: The ANT1 / ANT2 pins must be connected to the antenna connector by means of a 50 transmission line, implementing the design guidelines described in section 2.4.
Removable SIM cards are suitable for applications requiring a change of SIM card during the product’s lifetime. A SIM card holder can have 6 or 8 positions if a mechanical card presence detector is not provided, or it can have 6+2 or 8+2 positions if two additional pins relative to the normally-open mechanical switch integrated in the SIM connector for the mechanical card presence detection are provided.
Provide a very low capacitance (i.e. less than 10 pF) ESD protection (e.g. Tyco PESD0402-140) on each externally accessible SIM line, close to each relative pad of the SIM connector. The ESD sensitivity rating of the SIM interface pins is 1 kV (HBM). So that, according to EMC/ESD requirements of the custom application, a higher protection level can be required if the lines are externally accessible on the application device.
Provide a 100 nF bypass capacitor (e.g. Murata GRM155R71C104K) at the SIM supply line close to the relative pad of the SIM chip, to prevent digital noise. Provide a bypass capacitor of about 22 pF to 47 pF (e.g. Murata GRM1555C1H470J) on each SIM line, to prevent RF coupling especially when the RF antenna is placed closer than 10 - 30 cm from the SIM lines.
Guidelines for single SIM card connection with detection If the optional SIM card detection feature is required by the application, then a removable SIM card placed in a SIM card holder must be connected to the SIM0 interface of TOBY-L3 series modules as shown in Figure 26: Follow these guidelines to connect the module to a SIM connector implementing SIM detection: Connect the UICC / SIM contact C1 (VCC) to the VSIM pin of the module.
SIM CARD HOLDER TOBY-L3 series V_INT 5 TP R1 GPIO5 60 R2 VSIM 59 SW1 SW2 VPP (C6) VCC (C1) SIM_IO 57 C C C C 5 6 7 8 IO (C7) SIM_CLK 56 CLK (C3) SIM_RST 58 RST (C2) C1 C2 C3 C4 C5 GND (C5) D1 D2 D3 D4 D5 D6 C C C C 1 2 3 4 SIM Card Bottom View (contacts side) J1 Figure 26: Application circuit for the connection to a single removable SIM card, with SIM detection implemented Reference Description Part Number - Manufacturer C1, C2, C3, C4 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555
2.6 Data communication interfaces 2.6.1 USB interface 2.6.1.1 Guidelines for USB circuit design USB 2.0 interface, with the module acting as USB device, as shown in Figure 27 and Table 33 USB 2.0 interface, with the module acting as USB host, as shown in Figure and Table 34 USB pull-up or pull-down resistors and external series resistors on the USB_D+ and USB_D– lines as required by the USB 2.0 specification [4] are part of the module USB pins driver and do not need to be externally provided.
USB 2.0 HOST CONNECTOR 5V VBUS VCC Boost OUT IN 4 U1 D+ D– GND D1 D2 D3 C1 TOBY-L3 series C2 USB 2.0 DEVICE PROCESSOR VUSB_DET VBUS 28 USB_D+ D+ 27 USB_D– D– 168 USB_ID 5V OUT IN U1 C1 GND TOBY-L3 series VCC Boost 4 VUSB_DET 28 USB_D+ 27 USB_D– 168 USB_ID C2 GND GND Figure 39: USB 2.
40 0 um 3 5 0 um 40 0 um 3 5 0 um 40 0 um L1 Copper 3 5 um FR-4 dielectric 270 um L2 Copper 3 5 um FR-4 dielect ric 760 um L3 Copper 3 5 um FR-4 dielect ric L4 Copper 270 um 3 5 um Figure 28: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the described 4-layer board layup 410 um 740 um 410 um 740 um 410 um L1 Copper 3 5 um FR-4 dielectric 15 10 um L2 Copper 3 5 um Figure 29: Example of USB line design, with Z0 close to 90 and ZCM close to 30 , for the desc
3V Processor / Device Unidirectional Voltage Translator 3V0 VCC C1 VCCA DIR1 DIR3 TOBY-L3 series 1V8 TP VCCB C2 0 Ohm TP 5 V_INT TxD A1 B1 RxD A2 B2 RTS A3 B3 RTSx CTS A4 B4 CTSx GND DIR2 DIR4 0 Ohm TP OE GND TXDx RXDx GND U1 Figure 31: 4-wire UART interface application circuit to connect an external 3.
3V Processor / Device Unidirectional Voltage Translator 3V0 VCC VCCA C1 5 V_INT C2 DIR1 A1 B1 RxD A2 B2 DIR2 TP VCCB TxD GND TOBY-L3 series 1V8 0 Ohm TP 0 Ohm TP OE GND TXDx RXDx GND U1 Figure 33: 2-wire UART interface application circuit to connect an external 3.
3V Processor / Device Unidirectional Voltage Translator 3V0 VCC RI GND C1 VCCA VCCB A1 B1 A2 B2 DIR1 DIR2 TOBY-L3 series 1V8 TP C2 5 V_INT 11 RI OE GND GND U1 Figure 35: Ring Indicator(Configured by GPIO8) application circuit to connect an external 3.
Figure 36 describes a possible application circuit for the SPI0 interface, where two SPI slave devices are connected to the module using the two SPI0 Chip Select 0 (SPI_CS pin) to select the specific SPI slave device. The external SPI slave device must provide compatible voltage levels (1.80 V typ.), otherwise it is recommended to connect the 1.8 V SPI interface of the module to the external 3.0 V (or similar) SPI device by means of appropriate unidirectional voltage translators (e.g.
☞ Connect the DDC (I2C) pull-ups to the V_INT 1.8 V supply source, or another 1.8 V supply source enabled after V_INT (e.g., as the GNSS 1.8 V supply present in Figure 37 application circuit), as any external signal connected to the DDC (I2C) interface must not be set high before the switch-on of the V_INT supply of DDC (I2C) pins, to avoid latch-up of circuits and allow a clean boot of the module. The signal shape is defined by the values of the pull-up resistors and the bus capacitance.
☞ If the pins are not used as DDC (I2C) bus interface, they can be left unconnected. Connection with u-blox 1.8 V GNSS devices Figure 37 shows an application circuit for connecting the cellular modules to a u-blox 1.8 V GNSS device. SDA / SCL pins of the cellular module are directly connected to the relative I 2C pins of the u-blox 1.8 V GNSS device, with appropriate pull-up resistors connected to the 1.8 V GNSS supply enabled after the V_INT supply of the I2C pins of the cellular module.
Figure 38 illustrates an alternative application circuit solution in which the cellular module supplies a u-blox 1.8 V GNSS device. The V_INT 1.8 V regulated supply output of the cellular module can be used as supply source for a u-blox 1.8 V GNSS device instead of using an external voltage regulator, as shown in Figure 37. The V_INT supply is able to support the maximum current consumption of these positioning devices. The internal switching step-down regulator that generates the V_INT supply is set to 1.
T1 P-Channel MOSFET Low On-Resistance IRLML6401 - International Rectifier or NTZS3151P - ON Semi T2 NPN BJT Transistor BC847 - Infineon C1 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C104KA01 - Murata Table 40: Components for connecting TOBY-L3 series modules to u-blox 1.8 V GNSS devices using V_INT as supply Connection with u-blox 3.0 V GNSS devices Figure 39 shows an application circuit for connecting the cellular modules to a u-blox 3.
u-blox GNSS 3.0 V device TOBY-L3 series GNSS LDO Regulator 3V0 VCC C1 VMAIN OUT IN GND SHDNn GNSS supply enabled I2C-bus Bidirectional Voltage Translator C2 SDA2 R1 R2 VCCB 1V8 VCCA 5 C3 OE R4 R5 V_INT SDA_A 55 SDA SCL_B SCL_A GND 54 SCL SDA_B SCL2 22 GPIO2 R3 U1 U2 Unidirectional Voltage Translator 3V0 C4 TxD1 VCCA DIR A 1V8 VCCB C5 GNSS data ready B 24 GPIO3 GND OEn U3 Figure 39: Application circuit for connecting TOBY-L3 series modules to u-blox 3.
2.6.5 SDIO interface 2.6.5.
All GND pins of the cellular module and the u-blox JODY-W2 Wi-Fi module are connected to ground. All the other pins of the u-blox JODY-W2 Wi-Fi module are intended to be not connected.
SDIO pins of the SDIO device, with appropriate low value series damping resistors to avoid reflections and other losses in signal integrity, which may create ringing and loss of a square wave shape. The most appropriate value for the series damping resistors on the SDIO lines depends on the specific line lengths and layout implemented.
Consider the usage of low value series damping resistors to avoid reflections and other losses in signal integrity, which may create ringing and loss of a square wave shape. 2.6.6 SGMII interface 2.6.6.1 Guidelines for SGMII circuit design TOBY-L3 series modules include an Ethernet Media Access Control (MAC) block supporting up to 1 Gbit/s data rate via a Serial Gigabit Media-Independent Interface compliant with the SGMII Version 1.8 specification [8].
Consider the usage of low value series damping resistors to avoid reflections and other losses in signal integrity, which may create ringing and loss of a square wave shape. 2.7 eMMC interface ☞ The eMMC interface is not supported by the "0x" product feature versions. 2.7.1 Guidelines for eMMC circuit design TOBY-L3 series modules include a 4-bit embedded Multi-Media Card interface compliant with JESD84-B451 Embedded Multimedia Card (eMMC) Electrical Standard 4.
2.8 Digital Audio interface 2.8.1 Guidelines for digital audio circuit design I2S digital audio interfaces can be connected to external digital audio devices for voice applications.
1.8 V audio device with slave role connected to a digital audio interface of the module set as master 1.8 V audio device with master role connected to a digital audio interface of the module set as slave 3.0 V audio device with slave role connected to a digital audio interface of the module set as master 3.
The module’s PCM interface (mast mode) is connected to the related pins of the external audio codec (slave mode). The external audio codec is controlled by the TOBY-L3 series module using the DDC (I2C) interfaces (I2C_SDA1, I2C_SCL1) which can be configured through AT command. For more details, see the TOBYL3 series AT Commands Manual [2]. The VDD_INT output supplies the external audio codec (SPKVDD, MICVDD, DBVDD and AVDO1 pins), the MICVDD pin of the ALC5660 is supplied by the 3.
R2,R3 2.2 k Resistor 0402 0.1% 62.5 mW RN73R1ETP2201B25 - KOA D1,D2 Low Capacitance ESD Protection USB0002RP or USB0002DP – AVX U1 LDO Linear Regulator 1.8 V 0.3 A LT1962EMS8-1.
☞ The ESD sensitivity rating of ADC pins is 1 kV (HBM according to JESD22-A114). Higher protection level could be required if the lines are externally accessible and it can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) close to the accessible points. ☞ If the ADC pins are not used, they can be left unconnected on the application board. 2.9.2 Guidelines for ADC layout design The Analog to Digital Converters (ADC1, ADC2) are high impedance analog inputs.
2.10.2 Guidelines for general purpose input/output layout design The general purpose inputs / outputs pins are generally not critical for layout. 2.11 Reserved pins (RSVD) TOBY-L3 series modules have pins reserved for future use, marked as RSVD. All the RSVD pins are to be left unconnected on the application board. 2.12 Module placement An optimized placement allows a minimum RF line’s length and a closer path from the DC source for VCC.
2.13 Module footprint and paste mask Figure 45 and Table 46 describe the suggested footprint (i.e. copper mask) and the paste mask (i.e. stencil) layout for TOBY-L3 series modules, to be implemented on the application PCB. The proposed land pattern layout (i.e. the footprint, the application board top-layer copper mask) reflects the modules’ pads layout, with the pads on the application board designed as the LGA pads of the module. L G2 H F Copper 1.50 1.10 Copper I 0.10 0.
Light-Blue marked pads: Paste layout reduced circumferentially 0.1 mm to Copper layout The recommended solder paste (i.e. stencil) thickness is 150 µm, according to application production process requirements. ☞ These are recommendations only and not specifications. The exact mask geometries, distances and stencil thicknesses must be adapted to the specific production processes of the customer. 2.
Optimize antenna return loss, to optimize overall electrical performance of the module including a decrease of module thermal power. Optimize the thermal design of any high-power components included in the application, such as linear regulators and amplifiers, to optimize overall temperature distribution in the application device. Select the material, the thickness and the surface of the box (i.e.
Do not apply loads which might exceed the limit for the maximum available current from V_INT supply. Check that the voltage level of any connected pin does not exceed the relative operating range. Provide accessible test points directly connected to the following pins of the TOBY-L3 series modules: V_INT, PWR_ON and RESET_N for diagnostic purposes. Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.
Check 50 nominal characteristic impedance of the RF transmission line connected to the ANT1 and the ANT2 ports (antenna RF interfaces). Ensure no coupling occurs between the RF interface and noisy or sensitive signals (SIM signals, high-speed digital lines such as the USB, SDIO, SGMII, eMMC, SPI and other data lines). Optimize placement for minimum length of the RF line.
Ensure a low Envelope Correlation Coefficient between the primary (ANT1) and the secondary (ANT2) antennas: the 3D antenna radiation patterns should have radiation lobes in different directions. Ensure high isolation between the cellular antennas and any other antenna or transmitter.
3 Handling and soldering ☞ No natural rubbers, no hygroscopic materials or materials containing asbestos are employed. 3.1 Packaging, shipping, storage and moisture preconditioning For information about the TOBY-L3 series reels / tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning, see the TOBY-L3 series Data Sheet [1]. 3.2 Handling The TOBY-L3 series modules are Electro-Static Discharge (ESD) sensitive devices.
To prevent electrostatic discharge through the RF pin, do not touch any exposed antenna area. If there is any risk that such an exposed antenna area is touched in a non-ESD protected work area, implement suitable ESD protection measures in the design. When soldering the module and patch antennas to the RF pin, make sure to use an ESD safe soldering iron. 3.3 Soldering 3.3.
Temperature rise rate: max 3 °C/s If the temperature rise is too rapid in the preheat phase, it may cause excessive slumping. Time: 60 – 120 s If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters. End Temperature: 150 °C - 200 °C If the temperature is too low, non-melting tends to be caused in areas containing large heat capacity.
Preheat Heating Peak Temp. 245°C [°C] 250 Cooling [°C] 250 Liquidus Temperature 217 200 217 200 40 - 60 s End Temp. 150 - 200°C max 4°C/s 150 150 max 3°C/s 60 - 120 s 100 Typical Leadfree Soldering Profile 50 100 50 Elapsed time [s] Figure 59: Recommended soldering profile ☞ The modules must not be soldered with a damp heat process. 3.3.3 Optical inspection After soldering the module, inspect it optically to verify that it is properly aligned and centered. 3.3.
(besides others) is the risk of the module falling off due to the significantly higher weight in relation to other components. ☞ Tashang gives no warranty against damages to the TOBY-L3 series modules caused by performing more than a total of two reflow soldering processes (one reflow soldering process to mount the TOBY-L3 series module, plus one reflow soldering process to mount other parts). 3.3.6 Wave soldering TOBY-L3 series LGA modules must not be soldered with a wave soldering process.
The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, and therefore care is required in applying the coating. ☞ Conformal coating of the module will void the warranty. 3.3.10 Casting If casting is required, use viscose or another type of silicon pottant. The OEM is strongly advised to qualify such processes in combination with the cellular modules before implementing this in production. ☞ Casting will void the warranty. 3.3.
4 Approvals ☞ For the complete list and specific details regarding the certification schemes approvals, see the TOBYL3 series Data Sheet [1], or contact the Tashang office or sales representative nearest you. 4.
[15] documents, is a statement of the implemented and supported capabilities, functions and options of a device. ☞ The PICS document of the application device integrating TOBY-L3 series modules must be updated from the module PICS statement if any feature stated as supported by the module in its PICS document is not implemented or disabled in the application device.
5 Product testing 5.1 Product test Tashang focuses on high quality for its products. All units produced are fully tested automatically in the production line. A stringent quality control process has been implemented in the production line. Defective units are analyzed in detail to improve production quality. This is achieved with automatic test equipment (ATE) in the production line, which logs all production and measurement data. A detailed test report for each unit can be generated from the system.
5.2 Test parameters for OEM manufacturers Because of the testing performed by Tashang (with 100% coverage), an OEM manufacturer does not need to repeat firmware tests or measurements of the module RF performance or tests over digital interface in their production test.
⚠ To avoid module damage during the transmitter test, a suitable antenna according to module specifications or a 50 termination must be connected to the ANT1 port. ⚠ To avoid module damage during receiver, test the maximum power level received at the ANT1 and ANT2 ports which must meet the module specifications. ☞ The AT+UTEST command sets the module to emit RF power ignoring LTE/3G/2G signaling protocol. This emission can generate interference that can be prohibited by law in some countries.
6 FCC Notes 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.31 (h) and (k): The host manufacturer is responsible for additional testing to verify compliance as a composite system.
designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
7 IC Notes Canada Statement This device complies with Industry Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence.
LTE B7 Dipole 1.48 LTE 12 / B71 Dipole 0.73 LTE B13 Dipole 0.12 LTE B41 Dipole 1.
Appendix Glossary Abbreviation Definition 3GPP 3rd Generation Partnership Project 8-PSK 8 Phase-Shift Keying modulation 16QAM 16-state Quadrature Amplitude Modulation 64QAM 64-state Quadrature Amplitude Modulation ACM Abstract Control Model ADC Analog to Digital Converter AP Application Processor API Application Program Interface ASIC Application-Specific Integrated Circuit AT AT Command Interpreter Software Subsystem, or attention BAW Bulk Acoustic Wave CSFB Circuit Switched Fall-B
Abbreviation Definition FTP File Transfer Protocol FW Firmware GMSK Gaussian Minimum-Shift Keying modulation GND Ground GNSS Global Navigation Satellite System GPIO General Purpose Input Output GPRS General Packet Radio Service GPS Global Positioning System HBM Human Body Model HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access HTTP HyperText Transfer Protocol HW Hardware I/Q In phase and Quadrature I2C Inter-Integrated Circuit interface I2S Inter
Abbreviation Definition QPSK Quadrature Phase Shift Keying RF Radio Frequency RGMII Reduced Gigabit Media Independent Interface RMII Reduced Media Independent Interface RSE Radiated Spurious Emission RTC Real Time Clock SAW Surface Acoustic Wave SDIO Secure Digital Input Output SDN / PCN / IN Sample Delivery Note / Product Change Notification / Information Note SGMII Serial Gigabit Media Independent Interface SIM Subscriber Identification Module SMS Short Message Service SPI Seria
Related documents [1] TOBY-L3 series Data Sheet, Doc. No. TSD-19081201 [2] TOBY-L3 series AT Commands Manual, Doc. No. TSD-19102501 [3] TOBY-L3 series Open CPU SDK User Manual. TSD-20080301 [4] Universal Serial Bus Rev. 2.0 specification, https://www.usb.org/ [5] Universal Serial Bus Rev. 3.0 specification, https://www.usb.org/ [6] ITU-T Recommendation V.
Revision history Revision Date Name Comments R01 06-Sep-2019 Herb Initial release R02 28-Feb-2020 Herb Add the details of the software features Modify the circuit design of SDIO and I2S interface R03 17-Mar-2020 Herb Modify the default GPIO configuration R04 05-Aug-2020 Herb Add the PIN reuse of UART, SPI and I2S interfaces Add LTE B18 for Japan and India region in TOBY-L3904 series module.
Contact Tashang Offices Headquarters Tashang Semiconductor (Shanghai) Co., Ltd. Phone: +86 21 6029 4659 E-mail: sales@ta-shang.com Information: info@ta-shang.com Support: support@ta-shang.