Specification Sheet

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Diagonal 6.46 mm (Type 1/2.8) CMOS Solid-state Image Sensor with Square Pixel for

Color Cameras

IMX29

LQR

Description

The IMX291LQR-C is a diagonal 6.46 mm (Type 1/2.8) CMOS active pixel type solid-state image sensor with a

square pixel array and 2.13 M effective pixels. This chip operates with analog 2.9 V, digital 1.2 V, and interface 1.8 V

triple power supply, and has low power consumption. High sensitivity, low dark current and no smear are achieved

through the adoption of R, G and B primary color mosaic filters. This chip features an electronic shutter with variable

charge-integration time.

(Applications: Surveillance cameras, FA cameras, Industrial cameras)

Features

CMOS active pixel type dots

Built-in timing adjustment circuit, H/V driver and serial communication circuit

Input frequency: 74.25 MHz / 37.125 MHz

Number of recommended recording pixels: 1920 (H) × 1080 (V) approx. 2.07M pixel

Readout mode

All-pixel scan mode

720p-HD readout mode

Window cropping mode

Vertical / Horizontal direction-normal / inverted readout mode

Readout rate

Maximum frame rate in Full HD 1080p mode: 120 frame / s

Wide dynamic range (WDR) function

Multiple exposure WDR

Variable-speed shutter function (resolution 1H units)

10-bit / 12-bit A/D converter

Conversion gain switching (HCG Mode / LCG Mode)

CDS / PGA function

0 dB to 30 dB: Analog Gain 30 dB (step pitch 0.3 dB)

30.3 dB to 72 dB: Analog Gain 30 dB + Digital Gain 0.3 to 42 dB (step pitch 0.3 dB)

Supports I/O switching

CMOS logic parallel SDR output

Low voltage LVDS (150 m Vp-p) serial ( 2 ch / 4 ch / 8 ch switching) DDR output

CSI-2 serial data output ( 2 Lane / 4 Lane, RAW10 / RAW12 output)

Recommended exit pupil distance: 30 mm to

Sony reserves the right to change products and specifications without prior notice.

This information does not convey any license by any implication or otherwise under any patents or other right.

Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits.

Summary of content (112 pages)

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Diagonal 6.46 mm (Type 1/2.8) CMOS Solid-state Image Sensor with Square Pixel for Color Cameras IMX291LQR-C Description The IMX291LQR-C is a diagonal 6.46 mm (Type 1/2.8) CMOS active pixel type solid-state image sensor with a square pixel array and 2.13 M effective pixels. This chip operates with analog 2.9 V, digital 1.2 V, and interface 1.8 V triple power supply, and has low power consumption.
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IMX291LQR-C Device Structure CMOS image sensor Image size Type 1/2.8 Total number of pixels 1945 (H) × 1109 (V) approx. 2.16 M pixels Number of effective pixels 1945 (H) × 1097 (V) approx. 2.13 M pixels Number of active pixels 1937 (H) × 1097 (V) approx. 2.12 M pixels Number of recommended recording pixels 1920 (H) × 1080 (V) approx. 2.07 M pixels Unit cell size 2.9 µm (H) × 2.
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IMX291LQR-C Absolute Maximum Ratings Item Symbol Min. Max. Unit Remarks Supply voltage (analog 2.9 V) AVDD -0.3 3.3 V Supply voltage (interface 1.8 V) OVDD -0.3 3.3 V Supply voltage (digital 1.2 V) DVDD -0.3 2.0 V Input voltage VI -0.3 OVDD + 0.3 V Not exceed 3.3 V Output voltage VO -0.3 OVDD + 0.3 V Not exceed 3.3 V Application Conditions Item Symbol Min. Typ. Max. Unit Supply voltage (analog 2.9 V) AVDD 2.80 2.90 3.00 V Supply voltage (Interface 1.
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IMX291LQR-C USE RESTRICTION NOTICE This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the image sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify this Notice which will be available to you in the latest specifications book for the Products. You should abide by the latest version of this Notice.
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IMX291LQR-C Contents Description ......................................................................................................................................................................1 Features ..........................................................................................................................................................................1 Device Structure ................................................................................................................
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IMX291LQR-C Black Level Adjustment Function ................................................................................................................................ 81 Normal Operation and Inverted Operation ................................................................................................................... 82 Shutter and Integration Time Settings .........................................................................................................................
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IMX291LQR-C Optical Center Top View Package center Optical center Package reference (H, V) 12.00 ± 0.10 mm 6.058 ± 0.
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IMX291LQR-C Pixel Arrangement Reference pin Top View P1 pin R G G B 9 A1 pin G R B G Effective margin for color processing Total number of pixels: 1945(H) × 1109(V) = 2.16 M Number of effective pixels: 1945(H) × 1097(V) = 2.13 M Number of active pixels: 1937(H) × 1097(V) = 2.12 M Number of recommended recording pixels: 1920(H) × 1080(V) = 2.
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IMX291LQR-C Block Diagram and Pin Configuration PLL Sensor Control Unit Sensor CDS/Column Circuit Block Diagram 9 Bias
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IMX291LQR-C A 1 B C D E F G H J K L M DLOMA DLOMB DLOMC DLOMD DLCKM DLOME DLOMF DLOMG DLOMH VDDMIF DLOPA DLOPB DLOPC DLOPD DLCKP DLOPE DLOPF DLOPG DLOPH VSSMIF N (GND) P (GND) N.C. N.C.
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IMX291LQR-C Pin Description No. Pin No I/O Analog /Digital Symbol 1 A1 2 A3 O A VLOADLM Reference pin 3 A4 Power A VDDHAN 2.9 V power supply 4 A5 O A VRLFR 5 A6 Power A VDDHPX 2.9 V power supply 6 A7 Power A VDDHCP 2.9 V power supply 7 A8 Power A VDDHPX 2.9 V power supply 8 A9 Power A VDDHAN 2.9 V power supply 9 A11 10 B3 GND 11 B4 12 B5 13 Description N.C. Remarks GND connectable Reference pin N.C. GND connectable A VSSHPX 2.
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IMX291LQR-C No. Pin No I/O Analog /Digital Symbol 39 E1 O D DLOMC CMOS output / LVDS output data 40 E2 O D DLOPC CMOS output / LVDS output data 41 E3 GND D VSSMIF 1.8 V GND 42 E4 Power D VDDLSC 1.2 V power supply 43 E5 N.C. GND connectable 44 E6 N.C. GND connectable 45 E7 46 E8 Description N.C. Power D VDDLSC GND D VSSLSC Remarks GND connectable 1.2 V power supply 47 E9 48 E10 N.C.
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IMX291LQR-C No. Pin No I/O Analog /Digital Symbol 79 L3 GND D VSSMIF 80 L4 81 L5 GND D VSSLSC 1.2 V GND 82 L6 GND D VSSLIF 1.2 V GND 83 L7 GND D VSSLIF 1.2 V GND 84 L8 GND D VSSLSC 1.2 V GND I/O D XHS Description Remarks 1.8 V GND N.C. GND connectable 85 L9 86 L10 N.C. GND connectable 87 L11 GND D VSSLSC 1.2 V GND 88 M1 Power D VDDMIF 1.8 V power supply 89 M2 GND D VSSMIF 1.8 V GND 90 M3 GND D VSSMIF 1.
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IMX291LQR-C Electrical Characteristics DC Characteristics Item Supply voltage Pins Symbol Condition Min. Typ. Max. Unit analog VDDHx AVDD 2.80 2.90 3.00 V Interface VDDMx OVDD 1.70 1.80 1.90 V digital VDDLx DVDD 1.10 1.20 1.30 V Digital input voltage Digital output voltage XHS XVS XCLR INCK XMASTER OMODE SCK SDI XCE XTRIG DLOP [A:F] DLOM [A:F] DLCKP DLCKM XHS XVS SDO TOUT LVDS output VIH 0.8OVDD V XVS / XHS Slave Mode VIL 0.
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IMX291LQR-C Current Consumption Typ. Item Max.
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IMX291LQR-C AC Characteristics Master Clock Waveform (INCK) 1/fINCK Tr_inck Tf_inck 0.8 × OVDD tWHINCK INCK 0.5 × OVDD tWLINCK 0.2 × OVDD tWP tP Duty Ratio = tWP / tP × 100 Item Symbol Min. Typ. Max. Unit Remarks fINCK × 0.96 fINCK fINCK × 1.02 MHz fINCK = 37.125 MHz, 74.25 MHz INCK clock frequency fINCK INCK Low level pulse width tWLINCK 4 ns fINCK = 37.125 MHz, 74.25 MHz INCK High level pulse width tWHINCK 4 ns fINCK = 37.125 MHz, 74.25 MHz 55.0 % Define with 0.
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IMX291LQR-C XVS / XHS Input Characteristics In Slave Mode (XMASTER pin = High) Tr_xvs Tf_xvs 0.8 × OVDD XVS 0.2 × OVDD Tf_xhs tWLXHS Tr_xhs tWHXHS 0.8 × OVDD XHS 0.2 × OVDD tHFDLY Item Symbol tVRDLY Min. Typ. Max.
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IMX291LQR-C Serial Communication 4-wire 0.8 × OVDD XCLR tWLXCLR tENXCE 0.2 × OVDD Tf_xclr Tr_xclr Tf_xce Tr_xce 0.8 × OVDD XCE tWHXCE 0.2 × OVDD tSUXCE 0.8 × OVDD tHDXCE Tf_sck Tr_sck 1/fSCK SCK 0.2 × OVDD tHDSDI tSUSDI Tr_sdi Tf_sdi 0.8 × OVDD SDI DATA DATA 0.2 × OVDD tDLSDO 0.8 × OVDD SDO DATA DATA 0.2 × OVDD Item Symbol Min. Typ. Max. Unit 13.
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IMX291LQR-C 2 IC Start condition Repeated Start condition Stop condition VIH/VOH SDA VIL/VOL tf tHD;DAT tBUF tr tSU;STA tSU;DAT tLOW VIH SCL VIL tHD;STA tHIGH tr tHD;STA tSU;STO 2 I C Specification Item Symbol Min. Low level input voltage VIL High level input voltage Typ. Max. Unit -0.3 0.3 × OVDD V VIH 0.7 × OVDD 1.9 V Low level input voltage VOL 0 0.2 × OVDD V High level input voltage VOH 0.
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IMX291LQR-C DLCKP / DLCKM, DLOP / DLOM CMOS Outputs 1/fDLCKP DLCKP 0.5 × OVDD tSKMINDO tSKMAXDO DLO* Item DLCKP frequency Symbol Min. Typ. fDLCKP DLCKP clock duty 40 50 Max. Unit 74.25 MHz 60 % Remarks DLCKP - DLO skew Max. tSKMAXDO 2 ns Output load capacitance: 20 pF DLCKP - DLO skew Min.
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IMX291LQR-C Low Voltage LVDS DDR Output DLCKM DLCKP DLCKP DLCKM tSUDO tHDDO DLOP* DLOM* DLOP* DLOM* Valid Data (Output load capacitance: 8 pF) Item Symbol DLCKP/DLCKM clock duty Min. Typ. Max. Unit Remarks 40 50 60 % DLCK = 297 MHz (Max.
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IMX291LQR-C I/O Equivalent Circuit Diagram : External pin Symbol Equivalent circuit Symbol Equivalent circuit VDDMIF VDDMIF OMODE TENABLE XVS XHS Digital input Digital I/O VSSLSC VSSLSC VDDMIF VDDMIF XMASTER XCE SDO TOUT Digital input Digital output VSSLSC VSSLSC VDDMIF XCLR INCK Digital input XTRIG Digital input VSSLSC VSSLSC SDI SCK Digital input VRLFR VRLST Analog I/O VSSLSC VSSHPX VDDHPX VDDMIF VDDMIF VLOADLM VBGR TAMON DLOPx DLCKP DLOxP DLOxN DLCKP DLCKN Analog I/O
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IMX291LQR-C Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics.
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IMX291LQR-C Image Sensor Characteristics (AVDD = 2.9 V, OVDD = 1.8 V, DVDD = 1.2 V, Tj = 60 Item Symbol G sensitivity , All-pixel scan mode, 12 bit 30 frame/s, Gain: 0 dB) Min. Typ. Max. 4663 (1105) 5486 (1300) Digit (mV) 2332 (553) 2743 (650) Digit (mV) S RG 0.45 0.60 B/G BG 0.32 0.
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IMX291LQR-C Image Sensor Characteristics Measurement Method Measurement Conditions 1. 2. In the following measurements, the device drive conditions are at the typical values of the bias conditions and clock voltage conditions.
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IMX291LQR-C Measurement Method 1. Sensitivity Set the measurement condition to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of 1/100 s, measure the Gr and Gb signal outputs (VGr, VGb) at the center of the screen, and substitute the values into the following formula. Sg = (VGr + VGb) / 2 × 100/30 [mV] 2. Sensitivity ratio Set the measurement condition to the standard imaging condition II.
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IMX291LQR-C Setting Registers Using Serial Communication This sensor can write and read the setting values of the various registers shown in the Register Map by 4-wire serial 2 communication and I C communication. See the Register Map for the addresses and setting values to be set. Because the two communication systems are judged at the first communication, once they are judged, the 2 communication cannot be switched until sensor reset.
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IMX291LQR-C Register Write and Read (4-wire) Follow the communication procedure below when writing registers. 1. 2. 3. 4. 5. 6. 7. Set XCE Low to enable the chip's communication function. Serial data input is executed using SCK and SDI. Transmit data in sync with SCK 1 bit at a time from the LSB using SDI. Transfer SDI in sync with the falling edge of SCK. (The data is loaded at the rising edge of SCK.) Input Chip ID (CID = 02h or 03h or 04h or 05h or 06h) to the first byte.
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IMX291LQR-C 2 Description of Setting Registers (I C) The serial data input order is MSB-first transfer. The table below shows the various data types and descriptions. SCL (shared with SCK) SDA (shared with SDI) Master IMX291 OVDD XCE Pin connection of serial communication SLAVE Address MSB 0 LSB 0 1 1 0 1 0 R/W * R/W is data direction bit R/W R / W bit Data direction 0 1 Read (Se 2 I C pin description Symbol Pin No.
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IMX291LQR-C Communication Protocol I2C serial communication supports a 16-bit register address and 8-bit data message type.
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IMX291LQR-C 2 Register Write and Read (I C) This sensor corresponds to four reed modes and the two write modes. Single Read from Random Location The sensor has an index function that indicates which address it is focusing on. In reading the data at an optional single address, the Master must set the index value to the address to be read. For this purpose it performs dummy write operation up to the register address.
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IMX291LQR-C Sequential Read Starting from Random Location In reading data sequentially, which is starting from an optional address, the Master must set the index value to the start of the addresses to be read. For this purpose, dummy write operation includes the register address setting. The Master sets the sensor index value to M by designating the sensor slave address with a read request, then designating the address (M). Then, the Master generates the Repeated Start Condition.
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IMX291LQR-C Single Write to Random Location The Master sets the sensor index value to M by designating the sensor slave address with a write request, and designating the address (M). After that the Master can write the value in the designated register by transmitting the data to be written. After writing the necessary data, the Master generates the Stop Condition to end the communication.
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IMX291LQR-C Register Map This sensor has a total of 1280 bytes (256 × 5) of registers, composed of registers with addresses 00h to FFh that correspond to Chip ID = 02h (write mode) / 82h (read mode), Chip ID = 03h (write mode) / 83h (read mode), Chip ID = 04h (write mode) / 84h (read mode), Chip ID = 05h (write mode) / 85h (read mode), and Chip ID = 06h (write mode) / 86h (read mode). Use the initial values for empty address.
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IMX291LQR-C (1) Registers corresponding to Chip ID = 02h in Write mode.
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IMX291LQR-C Address bit 4-wire 2 IC 0 Register name ADBIT Description AD conversion bits setting 0: 10 bit, 1: 12 bit 2 3005h 3 4 5 6 7 06h 07h 3006h [7:0] 3007h 0 VREVERSE Vertical (V) direction readout inversion control 0: Normal, 1: Inverted 1 HREVERSE Horizontal (H) direction readout inversion control 0: Normal, 1: Inverted 3 4 WINMODE [2:0] 6 Window mode setting 0: Full HD1080p 1: HD720p 4: Window cropping from Full HD 1080p Others: Setting prohibited 3008h [7:0] 0 FRSEL [1:0] 1
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IMX291LQR-C Address bit 4-wire 2 IC Register name 0 Description Default value after reset By register By address Reflection timing LSB 1 2 0Ah 300Ah 3 4 BLKLEVEL [8:0] Black level offset value setting 0F0h F0h V 5 6 7 0 MSB 1 2 0Bh 300Bh 3 4 5 6 7 0Ch 300Ch [7:0] 0Dh 300Dh [7:0] 0Eh 300Eh [7:0] 0Fh 300Fh [7:0] 10h 3010h [7:0] 11h 3011h [7:0] 12h 3012h [7:0] 13h 3013h [7:0] 00 0 0h 0h 0h 0h 0h 0h 0h 00h 00h 01h 01h 01h 00h F0h 00h 00h 00h 01h 01h 01h 00h F0h 00h 0
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IMX291LQR-C Address bit 4-wire 2 IC Register name 0 Description Default value after reset By register By address Reflection timing LSB 1 2 18h 3018h 3 65h 4 5 6 7 0 1 VMAX [17:0] 2 19h 3019h 3 4 When sensor master mode vertical span setting.
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IMX291LQR-C Address bit 4-wire 2 IC Register name 0 Description Default value after reset By register By address Reflection timing LSB 1 2 20h 3020h 3 00h 4 5 6 7 0 1 SHS1 [17:0] Storage time adjustment Designated in line units.
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IMX291LQR-C Address bit 4-wire 2 IC Register name 0 Description Default value after reset By register By address Reflection timing LSB 1 2 3Eh 303Eh 3 4 5 WINWV [10:0] 6 In window cropping mode Cropping size designation (Vertical direction 49h 449h V 7 0 1 2 3Fh 303Fh MSB 0h 0h 0h 0h 0h 3 4 5 6 7 0 04h LSB 1 2 40h 3040h 3 4 5 WINPH [10:0] 6 7 In window cropping mode Designation of upper left coordinate for cropping position (horizontal position) Set to become the multiple of
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IMX291LQR-C Address bit 4-wire 2 IC 0 Register name ODBIT Description Number of output bit setting 0: 10 bit, 1: 12 bit * In CSI-2 mode (OMODE = Low), 2 3 3046h 4 5 OPORTSEL [3:0] 6 7 47h 3047h [7:0] Output interface selection (In CSI-2, don't care. CSI-2 Interface will be selected by Chip ID: 06h register.) 0h: Parallel CMOS SDR Dh: LVDS 2 ch Eh: LVDS 4 ch Fh: LVDS 8 ch Others: Setting prohibited Fixed to "01h" 0 1 2 3 48h 3048h 4 5 XVSLNG [1:0] XVS pulse width setting in master mode.
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IMX291LQR-C Address bit 4-wire 2 IC Register name Description Default value after reset By register By address 0Ch 00h 10h 01h 0Ch 00h 10h 01h 4Ch to 5Bh 304Ch [7:0] to to 305Bh [7:0] Reserved 5Ch 305Ch [7:0] INCKSEL1 The value is set according to INCK. 5Dh 305Dh [7:0] INCKSEL2 The value is set according to INCK. 5Eh 305Eh [7:0] INCKSEL3 The value is set according to INCK. 5Fh 305Fh [7:0] INCKSEL4 The value is set according to INCK.
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IMX291LQR-C (2) Registers corresponding to Chip ID = 03h in Write mode.
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IMX291LQR-C Address bit 4-wire 2 IC 7Ch 317Ch [7:0] 7Dh 7Eh 7Fh to EBh 317Dh 317Eh 317Fh to 31EBh Register name ADBIT2 [7:0] [7:0] [7:0] to [7:0] ECh 31ECh [7:0] EDh 31EDh [7:0] to to to FFh 31FFh [7:0] Description The value is set according to AD conversion bits 10 bit: 12h 12 bit: 00h Fixed to 00 Set to "00h" * Default value after reset By register By address 17h 17h 00h 17h 00h 17h 0Eh 0Eh Reserved ADBIT3 The value is set according to AD conversion bits 10 bit: 37h 12 bit: 0Eh Reser
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IMX291LQR-C (3) Registers corresponding to Chip ID = 04h in Write mode.
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IMX291LQR-C (4) Registers corresponding to Chip ID = 05h in Write mode.
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IMX291LQR-C (5) Registers corresponding to Chip ID = 06h in Write mode. (Read: Chip ID = 86h) * These registers are set in CSI-2 interface only. Address bit 4-wire 00h to 04h 2 IC Register name 3400h [7:0] to to 3404h [7:0] Description 0h 0h 0h 0h 1 Fixe 2 3 3405h 4 5 Reflection timing Reserved 0 05h Default value after reset By By register address 20h REPETITION [1:0] 2h Immediately section.
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IMX291LQR-C Address bit 4-wire 2 IC Register name 1Ah 341Ah [7:0] to to to 40h 3440h [7:0] 41h 42h 3441h [7:0] 3442h [7:0] Description Default value after reset By By register address Reflection timing Reserved LSB CSI_DT_FMT [15:0] 0Ch RAW10: 0A0Ah / RAW12: 0C0Ch 0C0Ch Immediately 0Ch MSB Lane number setting 43h CSI_LANE_ [1:0] MODE 3443h [1:0] 0: Setting prohibited, 1: 2Lane, 3: 4Lane 3h 03h Immediately 2: Setting prohibited 00h [7:2] 44h 3444h [7:0] 45h 3445h [7:0] 46h 3446
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IMX291LQR-C Address bit 4-wire 2 IC 54h 3454h [7:0] 55h 3455h 56h to 71h 3456h [7:0] to to 3471h [7:0] 0 Register name TLPX[8:0] Description Global timing setting [7:1] Default value after reset Reflection timing By By register address 0Fh 00Fh Immediately 00h 00h Reserved LSB 0 1 2 72h 3472h 3 9Ch 4 5 6 7 Horizontal (H) direction effective X_OUT_SIZE [12:0] 0 pixel width setting. 079Ch Immediately * Refer to each operating setting.
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IMX291LQR-C Readout Drive mode The table below lists the operating modes available with this sensor. (N/A: Not supported mode) Window Mode All pixel INCK [MHz] 37.125 74.25 Full HD 1080p Window cropping HD720p All-pixel 37.125 74.25 37.125 74.25 AD conversion [bit] Output bit width [bit] Frame rate [frame/s] Data rate Parallel Serial LVDS CSI-2 CMOS [Mbps/ch] [Mbps/Lane] [Mpixel/s] 2 ch 4 ch 2 Lane 4 Lane 445.5 222.75 891 445.5 N/A 891 445.5 222.75 891 445.5 445.
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IMX291LQR-C Window Mode All-pixel Frame INCK rate [MHz] [frame/s] 37.125 74.25 Full HD 1080p H [pixels] 1920 V [lines] 1080 *1 Window cropping HD720p 25 30 50 60 100 120 Recording pixels All-pixel 37.125 74.25 37.125 74.25 Total number of pixels CMOS (10 bit/ 12 bit) 2640 2200 N/A N/A N/A N/A H [pixels] LVDS LVDS CSI-2 CSI-2 (10 bit) (12 bit) 3168 2640 3168 2640 3168 2640 2640 2200 2640 2200 N/A N/A V [lines] 1125 2200 1H period [µs] 35.6 29.6 17.8 14.8 8.9 7.4 29.
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IMX291LQR-C Sync code (Parallel CMOS output / Serial LVDS output) then output. The sync code is output in order of 1st, 2nd, 3rd and 4th. The fixed value is output for 1st to 3rd. (BLK: Blanking period) XHS SAV EAV XVS System delay System delay System delay V.BLK H.BLK V.BLK SAV (Invalid line) EAV (Invalid line) H.BLK H.BLK System delay V.BLK H.BLK System delay Frame information line H.BLK System delay H.OB/V.OB H.BLK System delay System delay System delay H.OB/V.OB H.BLK H.
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IMX291LQR-C Image Data Output Format (CSI-2 output) Frame Format Each line of each image frame is output like the General Frame Format of CSI-2. The settings for each packet header are shown below.
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IMX291LQR-C Embedded Data Line The Embedded data line is output in a line following the sync code FS.
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IMX291LQR-C Specific output examples are shown below.
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IMX291LQR-C Address Pixel Address [HEX] Data Byte Description IC C5h 34C5h 118 119 C6h 34C6h 120 121 C7h 34C7h 122 123 AEh 34AEh 124 125 AFh 34AFh 126 127 C9h 34C9h CAh CBh 133 CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h 191 5Ah 192 34D1h Fixed to "9Bh" Fixed to "07h" Fixed to "48h" Fixed to "04h" 152 153 D6h 34D6h Fixed to "9Ch" 154 155 D7h 34D7h Fixed to "07h" 156 157 D8h 34D8h Fixed to "49h" 158 159 D9h 34D9h Fixed to "04h" 160 161 BCh 34BCh 162 163 C0h 34C0h
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IMX291LQR-C Image Data Output Format All-pixel scan mode (Full HD 1080p) List of Setting Register for CMOS parallel / LVDS serial output Address 4-wire 2 IC bit Register Name Initial CMOS Value parallel LVDS serial 2 ch 4 ch Remarks 8 ch Chip ID: 02h 05h 07h 3005h 3007h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit [0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted [1] HREVERSE 0h 0h / 1h 0: Normal, 1: Inverted 0h 0h Full HD 1080p 2h 30 / 25 [frame/s] [6:4] WINMODE [1:0] FRSEL 2
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IMX291LQR-C List of Setting Register for CSI-2 serial output CSI-2 serial Address bit 4-wire 2 IC Register Name Initial Value 2 lane 30 / 25 [frame /s] 4 lane 60 / 50 [frame /s] 30 / 25 [frame /s] 60 / 50 [frame /s] 120 / 100 [frame /s] Remarks Chip ID: 02h 05h 07h 3005h 3007h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit [0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted [1] HREVERSE 0: Normal, 1: Inverted 0h 0h / 1h [6:4] WINMODE 0h 0h [1:0] FRSEL 2h 09h 3009h 12h 13h 18h 3018h
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IMX291LQR-C CSI-2 serial Address bit 4-wire 2 IC Register Name Initial Value 2 lane 30 / 25 [frame /s] 4 lane 60 / 50 [frame /s] 30 / 25 [frame /s] 60 / 50 [frame /s] 120 / 100 [frame /s] Remarks Chip ID = 06h 05h 3405h [5:4] REPETITION 07h 3407h [1:0] 14h 3414h [5:0] OPB_SIZE_V 18h 3418h [7:0] 19h 3419h [4:0] 41h 3441h [7:0] 42h 3442h [7:0] 43h 3443h [1:0] 44h 3444h [7:0] Data rate 445.5 891 222.75 445.
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IMX291LQR-C RG GB RG GB 8 Vertical blanking period 1 Frame information line 2 Ignored OB 10 Vertical effective OB 8 Effective margin for color processing RG GB GR BG RG GB GR BG Number of recommended recording pixels: 1920 (H) × 1080 (V) = 2.07 M pixel Number of active pixels: 1937 (H) × 1097 (V) = 2.12 M pixel Number of effective pixels: 1945 (H) × 1097 (V) = 2.13 M pixel Total number of pixels: 1945 (H) × 1109 (V) = 2.
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IMX291LQR-C XVS XHS Line No. during normal operation Line No.
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IMX291LQR-C FS 1 PH 1 EBD(Embedded data) PF PH 1 NULL 0 PF 10 Vertical effective OB 8 Effective margin for color processing RG GB RG GB RG GB GR BG RG GB GR BG PH PF 1080 Recording pixel area 4 GB RG 8 GB RG 1920 9 RG GB FE RG GB BG GR Effective margin for color processing 9 4 3 HB BG GR Vertical blanking VB Pixel Array Image Drawing in Full HD 1080p mode (CSI-2 serial output) XVS XHS Line No. during normal operation Line No.
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IMX291LQR-C Window Cropping Mode Sensor signals are cut out and read out in arbitrary positions. Cropping position is set, regarding effective pixel start position as origin (0, 0) in all pixel scan mode. Cropping is available from all-pixel scan mode and vertical, horizontal period and frame rate are fixed to the value for this mode. Pixels cropped by horizontal cropping setting are output with left justified and that extends the horizontal blanking period.
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IMX291LQR-C List of Setting Register for CMOS parallel / LVDS serial output Address 4-wire 2 IC bit Register Name Initial CMOS Value parallel LVDS serial 2 ch 4 ch Remarks 8 ch Chip ID: 02h 05h 07h 3005h 3007h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit [0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted [1] HREVERSE 0h 0h / 1h 0: Normal, 1: Inverted 0h 4h [6:4] WINMODE Window cropping 2h 09h 3009h [1:0] FRSEL [4] FDG_SEL 2h N/A N/A N/A N/A 1h N/A 0h 0h / 1h 0h 0: LCG
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IMX291LQR-C List of Setting Register for CSI-2 serial output CSI-2 serial Address bit 4-wire 2 IC Register Name Initial Value 2 lane *1 [frame /s] 4 lane *2 [frame /s] *1 [frame /s] *2 [frame /s] *3 [frame /s] Remarks Chip ID: 02h 05h 07h 3005h 3007h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit [0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted [1] HREVERSE 0h 0h / 1h [6:4] WINMODE 0h 4h [1:0] FRSEL 2h 09h 3009h 12h 13h 18h 3018h [7:0] [4] FDG_SEL 1h 2h 1h 0h 0: LCG mode, 1:
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IMX291LQR-C CSI-2 serial Address bit 4-wire 2 IC Register Name Initial Value 2 lane 4 lane *1 [frame /s] *2 [frame /s] *1 [frame /s] *2 [frame /s] *3 [frame /s] Data rate 445.5 891 222.75 445.
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IMX291LQR-C The example of window cropping setting is shown below. The frame rate is maximum setting as each image format. For adjust the frame rate, please extend the VMAX or the number of lines per frame. Example of Window cropping Mode Setting Output Frame Image INCK Resolution rate size [MHz] [bit] [frame/s] VGA CIF 37.125 74.25 37.125 74.25 Register setting [DEC] (HEX) Number of recording pixels Horizontal Vertical FRSEL HMAX 2 4400d (1130h) 1 2200d (898h) 10/12 64.9 10/12 129.
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IMX291LQR-C 8 Vertical blanking period 1 Frame information line 2 Ignored OB WINWV_OB - 2 Vertical effective OB RG GB RG GB RG GB RG GB (WINPH, WINPV) Recording pixel area WINWV + Effective margin for color processing SD 4 4 4 3 4 HB WINWH RG GB RG GB RG GB RG GB Vertical blanking VB Horizontal scan direction (Normal) XHS Pixel Array Image Drawing in Window Cropping mode (Parallel CMOS output / Serial LVDS output) XVS (1 Frame)13 + WINWV_OB + WINWV + Vx [lines] XHS WINPV Lin
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IMX291LQR-C XVS (1 Frame) 9 + WINWV_OB + WINWV + Vx [lines] XHS WINPV Line No. during normal operation Line No.
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IMX291LQR-C FS 1 PH 1 EBD(Embedded data) PH 1 NULL 0 PF PF WINWV_OB - 2 Vertical effective OB RG GB RG GB RG GB RG GB (WINPH, WINPV) PH Recording pixel area + Effective margin for color processing WINWV PF 4 4 3 WINWH RG GB FE RG GB RG GB VB RG GB Vertical blanking Pixel Array Image Drawing in Window Cropping mode (CSI-2 serial output) XVS (1 Frame) 9 + WINWV_OB + WINWV + Vx [lines] XHS WINPV Line No. during normal operation Line No.
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IMX291LQR-C HD720p mode List of Setting Register for CMOS parallel / LVDS serial output Address 4-wire 2 IC bit Register Name Initial Value CMOS parallel LVDS serial 2 ch Remarks 4 ch Chip ID: 02h 05h 07h 3005h 3007h [0] ADBIT 1h 0h / 1h 0: 10 bit, 1: 12 bit [0] VREVERSE 0h 0h / 1h 0: Normal, 1: Inverted [1] HREVERSE 0h 0h / 1h 0: Normal, 1: Inverted 0h 1h HD 720p 2h 30 [frame/s] [6:4] WINMODE 09h 3009h [1:0] FRSEL 2h 1h N/A [4] FDG_SEL 60 [frame/s] N/A 0h 0h 0h / 1h
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IMX291LQR-C List of Setting Register for CSI-2 serial output CSI-2 serial Address bit 4-wire 2 IC Register Name Initial Value 2 lane 30 [frame /s] 4 lane 60 [frame /s] 30 [frame /s] 60 [frame /s] Remarks 120 [frame /s] Chip ID: 02h 05h 07h 3005h 3007h [0] ADBIT [0] VREVERSE 0h [1] HREVERSE 0h [6:4] WINMODE 0h [1:0] FRSEL 2h 09h 3009h 12h 13h 18h 3018h [7:0] 19h 3019h [7:0] VMAX [4] FDG_SEL 0h / 1h 0: 10 bit, 1: 12 bit 0h / 1h 0: Normal, 1: Inverted 0h / 1h 0: Normal, 1:
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IMX291LQR-C CSI-2 serial Address bit 4-wire 2 IC Register Name Initial Value 2 lane 4 lane 30 [frame /s] 60 [frame /s] 30 [frame /s] 60 [frame /s] 120 [frame /s] Data rate 297 594 148.
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IMX291LQR-C RG GB RG GB 8 Vertical blanking period 1 Frame information line 2 Ignored OB 4 Vertical effective OB 4 Effective margin for color processing RG GB GR BG RG GB Number of recommended recording pixels: 1280 (H) × 720 Number of active pixels: 1297 (H) × 725 Number of effective pixels: 1305 (H) × 725 Total number of pixels: 1312 (H) × 731 GR BG (V) = 0.92 M pixel (V) = 0.94 M pixel (V) = 0.95 M pixel (V) = 0.
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IMX291LQR-C XVS (1 Frame) 30, 60, 120 frame/s: 750 [lines] XHS Line No. during normal operation Line No.
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IMX291LQR-C FS 1 PH 1 EBD(Embedded data) PF PH 1 NULL 0 PF 4 Vertical effective OB 4 Effective margin for color processing RG GB RG GB RG GB GR BG RG GB GR BG PH PF 720 Recording pixel area 4 GB RG 8 GB RG 1280 9 RG GB RG GB FE 5 Effective margin for color processing 5 Vertical blanking 4 BG GR 3 HB BG GR Pixel Array Image Drawing in HD720p mode (CSI-2 serial output) XVS (1 Frame) 30, 60, 120 frame/s: 750 [lines] XHS Line No. during normal operation Line No.
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IMX291LQR-C Description of Various Function Standby Mode This sensor stops its operation and goes into standby mode which reduces the power consumption by writing the standby control register STANDBY. Standby mode is also established after power-on or other system reset operation.
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IMX291LQR-C Slave Mode and Master Mode The sensor can be switched between slave mode and master mode. The switching is made by the XMASTER pin. Establish the XMASTER pin status before canceling the system reset. (Do not switch this pin status during operation.) Input a vertical sync signal to XVS and input a horizontal sync signal to XHS when a sensor is in slave mode.
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IMX291LQR-C XVS XVSLNG = 0d: 1H width XVSLNG = 1d: 2H width XVS XVSLNG = 2d: 4H width XVSLNG = 3d: 8H width XHS XHS XHSLNG = 0 XHSLNG = 1 XHS XHSLNG = 2 XHSLNG = 3 System delay DataOut SAV XVS/XHS output waveform in sensor master mode List of XHSLNG Register CMOS parallel output DCK XHSLNG XHSLNG XHSLNG XHSLNG =0 =1 =2 =3 LVDS serial output 74.25 [MHz] 37.125 [MHz] 594 [Mbps / ch] 297 [Mbps / ch] 148.5 [Mbps / ch] 445.5 [Mbps / ch] 222.75 [Mbps / ch] 111.
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IMX291LQR-C Gain Adjustment Function The Programmable Gain Control (PGC) of this device consists of the analog block and digital block. The total of analog gain and digital gain can be set up to 72 dB by the GAIN [7:0] register setting. The same setting is applied in all colors. The value which is 10/3 times the gain is set to register. (0.3 dB step) Example) When set to 6 dB: 6 × 10/3 = 20d; GAIN [7:0] = 14h When set to 12.6 dB: 12.
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IMX291LQR-C The gain setting is reflected at the next frame that the communication is performed as shown below.
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IMX291LQR-C Normal Operation and Inverted Operation The sensor readout direction (normal / inverted) in vertical direction can be switched by the VREVERSE register setting and in horizontal direction can be switched by the HREVERSE inverted modes. One invalid frame is generated when reading immediately after the readout direction change in order to switch the normal operation and inversion between frames.
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IMX291LQR-C Shutter and Integration Time Settings This sensor has a variable electronic shutter function that can control the integration time in line units. In addition, this sensor performs rolling shutter operation in which electronic shutter and readout operation are performed sequentially for each line. Note) For integration time control, an image which reflects the setting is output from the frame after the setting changes.
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IMX291LQR-C Normal Exposure Operation (Controlling the Integration Time in 1H Units) The integration time can be controlled by varying the electronic shutter timing. In the electronic shutter settings, the integration time is controlled by the SHS1 [17:0] register. Set SHS1 [17:0] to a value between 1 and (Number of lines per frame - 1).
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IMX291LQR-C Long Exposure Operation (Control by Expanding the Number of Lines per Frame) Long exposure operation can be performed by lengthening the frame period. When the sensor is operating in slave mode, this is done by lengthening the input vertical sync signal (XVS) pulse interval. When the sensor is operating in master mode, it is done by designating a larger register VMAX [17:0] value compared to normal operation.
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IMX291LQR-C Example of Integration Time Settings The example of register setting for controlling the storage time is shown below. Example of Integration Time Settings (In Full HD 1080p) Operation Sensor setting (register) * VMAX SHS1 Integration time ** 1123 Normal frame rate 1125 1H N (1125 - (N + 1)) H 1 1123H * In sensor master mode. In slave mode, the interval is the same as XVS input.
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IMX291LQR-C Signal Output Output Pin Settings The output formats of this sensor support the following modes. CMOS logic parallel SDR output Low voltage LVDS serial (2 ch / 4 ch / 8 ch switching) DDR output CSI-2 serial (2 Lane / 4 Lane, RAW10 / RAW12) output The switching for serial interface is made by the OMODE pin. Establish the OMODE pin status before canceling the system reset. (Do not switch this pin status during operation.) Each mode is set using the register OPORTSEL.
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IMX291LQR-C Each output pin is shown in the table below when setting low-voltage LVDS serial 2 ch / 4 ch / 8 ch output.
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IMX291LQR-C Low-voltage LVDS serial 2 ch / 4 ch / 8 ch output format is shown in the figure below. When setting 2 ch, after four data of SAV is output in the order of CH1 and CH2 pixel data is repeatedly output in the same order and then four data of EAV is output in the same order to CH1 and CH2 respectively.
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IMX291LQR-C CSI-2 output The output formats of this sensor support the following modes. CSI-2 serial 2 Lane / 4 Lane, RAW10 / RAW12 The 2 Lane / 4 Lane serial signal output method using this sensor is described below. Complied with the CSI-2, data is output using 2 Lane / 4 Lane. The image data is output from the CSI-2 output pin.
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IMX291LQR-C The each formal of 2 Lane and 4 Lane are shown below.
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IMX291LQR-C MIPI Transmitter Output pins (DMO1P, DMO1N, DMO2P, DMO2N, DMO3P, DMO3N, DMO4P, DMO4D, DMCKP, DMCKN) are described in this section. Sensor DMO1P N6 + DMO1N P6 - DMO2P N8 + DMO2N P8 - DMO3P N5 + DMO3N P5 - DMO4P N9 + DMO4N P9 - DMCKP N7 + DMCKN P7 - Data Lane 1 Data Lane 2 Data Lane 3 Data Lane 4 Clock Lane Relationship between Pin Name and MIPI Output Lane The pixel signals are output by the CSI-2 High-speed serial interface.
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IMX291LQR-C Output Pin Bit Width Selection The output pin width can be selected from 10-bit or 12-bit output using the register ODBIT. In parallel output mode, when ODBIT = 0 (10-bit output), the lower 2 bits are fixed to Low level in CMOS output mode. Therefore, when using only 10 bits, the pins corresponding to the lower 2 bits can be left open on the board by setting ODBIT = 0. When low-voltage LVDS serial output, continuous data is output MSB first by 10-bit and 12-bit output setting respectively.
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IMX291LQR-C ODBIT = 0 (Low voltage LVDS serial 10 bit output) DLCK CHx (x = 1 - 4) MSB First DLCK CHx (x = 1 - 4) Example of Data format in low-voltage LVDS serial 10-bit output ODBIT = 1 (Low voltage LVDS serial 12 bit output) DLCK CHx (x = 1 - 4) MSB First DLCK CHx (x = 1 - 4) Example of Data format in low-voltage LVDS serial 12-bit output Number of Internal A/D Conversion Bits Setting The number of internal A/D conversion bits can be selected from 10 bits or 12 bits by the register ADBIT.
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IMX291LQR-C Output Rate Setting The sensor output rate is determined uniformly by the sensor operating mode and the output format. See the relationship between each setting and the frame rate, data rate and data bit rate. The registers related to mode setting are shown in the table below.
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IMX291LQR-C INCK Setting The available operation mode varies according to INCK frequency. Input either 37.125 MHz or 74.25 MHz for INCK frequency. The INCK setting register and the list of INCK setting are shown in the table below. INCK Setting Register Register details *1: Chip ID = 02h *2: Chip ID = 03h *3: Chip ID = 06h Register name INCK = 37.
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IMX291LQR-C Software Reset (CMOS parallel / Low voltage LVDS serial only) This function is prohibited in CSI-2 output mode. Software reset can be performed by register setting using the register SW_RESET.Sensor reset is performed by setting SW_RESET = 1. However, the communication to continuous address cannot use. The registers become initial state and standby 500 ns after setting SW_RESET = 1. The SW_RESET signal returns to "0" automatically.
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IMX291LQR-C Mode Transitions When changing the operating mode during sensor drive operation, set via sensor standby. However, these transitions that described below can be transitions without standby. Change the number of vertical lines (In sensor master mode, change the VMAX. In sensor slave mode, change the period of XVS input.) Horizontal and vertical scan direction. (When the vertical scan direction is changed, an invalid frame generates during transition.) Change the HCG mode and LCG mode.
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IMX291LQR-C Power-on and Power-off Sequence Power-on sequence 1. 2. 3. 4. 5. Turn On the power supplies so that the power supplies rise in order of 1.2 V power supply (DV DD power supply (OVDD 2.9 V power supply (AVDD). In addition, all power supplies should finish rising within 200 ms. Start master clock (INCK) input after turning On the power supplies. The register values are undefined immediately after power-on, so the system must be cleared.
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IMX291LQR-C Power-off sequence Turn Off the power supplies so that the power supplies fall in order of 2.9 V power supply (AVDD DD). In addition, all power supplies should falling within 200 ms. Set each supply (OVDD digital input pin (INCK, XCE, SCK, SDI, XCLR, XMASTER, OMODE, XVS, XHS) to 0 V before the 1.8 V power supply (OVDD) falls. T6 2.9 V power supply (AVDD) T4 1.8 V power supply (OVDD) T5 1.
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IMX291LQR-C Sensor Setting Flow Setting Flow in Sensor Slave Mode The figure below shows operating flow in sensor slave mode. For details of "Power-on" to "Reset cancel", see the item of "Power-on sequence" in this section. lization", see the item of "Standby mode". Start Pin settings Power-on INCK input before power-on is available.
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IMX291LQR-C Setting Flow in Sensor Master Mode The figure below shows operating flow in sensor master mode. For details of "Power-on" to "Reset cancel", see the item of "Power on sequence" in this section. internal regulator time, set "master mode stop" by setting XMSTA to "1". Start Pin settings Power-on INCK input before power-on is available.
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IMX291LQR-C Peripheral Circuit Analog 2.9V A7 A9 A4 A8 Digital 1.2V A6 M11 D11 K8 K5 Digital 1.8V E8 E4 K7 K6 M1 PLL V Scan Ramp LVDS/CMOS Pixel Comp BIAS Counter Logic D-PHY Digital I/F CP B7 A5 B5 B9 B4 C11 B8 B6 B3 A3 M10 D10 N3 L11 L8 L5 E10 D8 D4 P3 M9 M8 M7 M6 M5 L7 L6 M3 M2 L3 K3 E3 D3 C3 Common GND Digital 1.
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IMX291LQR-C Spot Pixel Specifications (AVDD = 2.9 V, OVDD = 1.8 V, DVDD = 1.2 V, Tj = 60 , 30 frame/s, Gain: 0 dB) Maximum distorted pixels in each zone Type of distortion Level Effective OB 0 to II' Black or white pixels at high light 30 % < D White pixels in the dark D < 730 mV Remarks method 0 1 No evaluation criteria applied 150 Black pixels at signal saturated Measurement No evaluation criteria applied 15 5.
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IMX291LQR-C Notice on White Pixels Specifications After delivery inspection of CMOS image sensors, cosmic radiation may distort pixels of CMOS image sensors, and then distorted pixels may cause white point effects in dark signals in picture images. (Such white point effects shall be hereinafter referred to as "White Pixels".) Unfortunately, it is not possible with current scientific technology for CMOS image sensors to prevent such White Pixels.
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IMX291LQR-C Measurement Method for Spot Pixels After setting to standard imaging condition II, and the device driver should be set to meet bias and clock voltage conditions. Configure the drive circuit according to the example and measure. 1.
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IMX291LQR-C Spot Pixel Pattern Specification White Pixel, Black Pixel and Bright Pixel are judged from the pattern whether they are allowed or rejected, and counted. List of White Pixel, Black Pixel and Bright Pixel Pattern No. Note) Pattern R G G B It provides by color filter array described in the left. White pixel Black pixel Bright pixel 1 Same color Rejected 2 Same color Rejected 1. shows the position of white pixel, black pixel and bright pixel.
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IMX291LQR-C Marking 108
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IMX291LQR-C Notes On Handling 1. Static charge prevention Image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. (1) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. (2) Use a wrist strap when handling directly. (3) Install grounded conductive mats on the floor and working table to prevent the generation of static electricity.
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IMX291LQR-C 4. Recommended reflow soldering conditions The following items should be observed for reflow soldering. (1) Temperature profile for reflow soldering Control item Profile (at part side surface) 1. Preheating 150 to 180 °C 60 to 120 s 2. Temperature up (down) +4 °C/s or less ( 6 °C/s or less) 3. Reflow temperature Over 230 °C 10 to 30 s Max. 5 °C/s 4. Peak temperature Max. 240 ± 5 °C Temperature Peak 240 ± 5 °C 230 °C Max.
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IMX291LQR-C Package Outline (Unit: mm) 111
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IMX291LQR-C List of Trademark Logos and Definition Statements * Exmor R is a trademark of Sony Corporation. The Exmor R is a Sony's CMOS image sensor with significantly enhanced imaging TM characteristics including sensitivity and low noise by changing fundamental structure of Exmor pixel adopted column parallel A/D converter to back-illuminated type. * STARVIS is a trademark of Sony Corporation.