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M80 Hardware Design

M80_HD_V1.0 - 1 -

M80

Quectel Cellular Engine

Hardware Design

M80_HD_V1.0

Summary of content (88 pages)

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M80 Hardware Design M80 Quectel Cellular Engine Hardware Design M80_HD_V1.0 M80_HD_V1.
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M80 Hardware Design Document Title M80 Hardware Design Revision 1.0 Date 2011-11-12 Status Released Document Control ID M80_HD_V1.0 l e t l c a i e t u n Q fide n o C General Notes Quectel offers this information as a service to its customers, to support application and engineering efforts that use the products designed by Quectel. The information provided is based upon requirements specifically provided for customers of Quectel.
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M80 Hardware Design Contents Contents ............................................................................................................................................ 3 Table Index........................................................................................................................................ 5 Figure Index ...................................................................................................................................... 6 0. Revision history ..........
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M80 Hardware Design 3.10.3. Receiver and speaker interface design................................................................... 56 3.10.4. Earphone interface design ..................................................................................... 57 3.10.5. Loud speaker interface design ............................................................................... 58 3.10.6. Audio characteristics ............................................................................................. 59 3.
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M80 Hardware Design Table Index TABLE 1: RELATED DOCUMENTS ..................................................................................................... 9 TABLE 2: TERMS AND ABBREVIATIONS ....................................................................................... 10 TABLE 3: MODULE KEY FEATURES ................................................................................................ 14 TABLE 4: CODING SCHEMES AND MAXIMUM NET DATA RATES OVER AIR INTERFACE ..
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M80 Hardware Design Figure Index FIGURE 1: MODULE FUNCTIONAL DIAGRAM ............................................................................. 17 FIGURE 2: PIN ASSIGNMENT ............................................................................................................ 20 FIGURE 3: RIPPLE IN SUPPLY VOLTAGE DURING TRANSMITTING BURST ........................... 32 FIGURE 4: REFERENCE CIRCUIT OF THE VBAT INPUT ..............................................................
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M80 Hardware Design FIGURE 42: REFERENCE CIRCUIT OF THE NETLIGHT................................................................ 67 FIGURE 43: REFERENCE CIRCUIT OF THE STATUS ..................................................................... 68 FIGURE 44: REFERENCE CIRCUIT OF RF ....................................................................................... 69 FIGURE 45: RF SOLDERING SAMPLE .............................................................................................
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M80 Hardware Design 0. Revision history Revision Date Author Description of change 1.0 2011-11-01 Ray XU Initial l e t l c a i e t u n Q fide n o C M80_HD_V1.
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M80 Hardware Design 1. Introduction This document defines the M80 module and describes the hardware interface of M80 which are connected with the customer application and the air interface. This document can help customers quickly understand module interface specifications, electrical and mechanical details. With the help of this document, associated application notes and user guide, customers can use M80 module to design and set up mobile applications quickly. l e t l c a i e t u n Q fide n o C 1.1.
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M80 Hardware Design 1.2.
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M80 Hardware Design Li-Ion Lithium-Ion Abbreviation Description MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PBCCH Packet Switched Broadcast Control Channel PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol RF RMS RTC RX SIM SMS l e t l c a i e t u n Q fide n o C Radio Frequency Root Mean Square (value) Real Time Clock Receive Direction Subscriber Identification Module Short Message Service
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M80 Hardware Design SM SIM phonebook 1.3. Safety caution The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating M80 module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel and to incorporate these guidelines into all manuals supplied with the product.
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M80 Hardware Design GSM cellular terminals or mobiles operate over radio frequency signal and cellular network and cannot be guaranteed to connect in all conditions, for example no mobile fee or an invalid SIM card. While you are in this condition and need emergent help, Please Remember using emergency call. In order to make or receive call, the cellular terminal or mobile must be switched on and in a service area with adequate cellular signal strength.
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M80 Hardware Design 2. Product concept M80 is a Quad-band GSM/GPRS engine that works at frequencies of GSM850MHz, GSM900MHz, DCS1800MHz and PCS1900MHz. The M80 features GPRS multi-slot class 12 and supports the GPRS coding schemes CS-1, CS-2, CS-3 and CS-4. For more details about GPRS multi-slot classes and coding schemes, please refer to Appendix A and Appendix B. With a tiny profile of 23mm × 25mm × 2.
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M80 Hardware Design  GPRS mobile station class B Temperature range    Normal operation: -35°C ~ +80°C Restricted operation: -45°C ~ -35°C and +80°C ~ +85°C 1) Storage temperature: -45°C ~ +90°C DATA GPRS:         GPRS data downlink transfer: max. 85.6 kbps GPRS data uplink transfer: max. 85.
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M80 Hardware Design Weight: 3.3g Firmware upgrade Firmware upgrade via UART Port or USB Port Antenna interface Connected via 50 Ohm antenna pad Table 4: Coding schemes and maximum net data rates over air interface Coding scheme 1 Timeslot 2 Timeslot 4 Timeslot CS-1: 9.05kbps 18.1kbps 36.2kbps CS-2: 13.4kbps 26.8kbps 53.6kbps CS-3: 15.6kbps 31.2kbps 62.4kbps CS-4: 21.4kbps 42.8kbps 85.6kbps l e t l c a i e t u n Q fide n o C 2.2.
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M80 Hardware Design Charge RF PAM Power supply PMU RTC Saw PCM Turn on/off UART Transceiver l e t l c a i e t u n Q fide n o C SIM Baseband Engine Camera Audio codec SD EINT 26MHz 32kHz ADC USB Serial Flash Indicator Figure 1: Module functional diagram M80_HD_V1.
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M80 Hardware Design 2.3. Evaluation board In order to help customer to develop applications with M80, Quectel supplies an evaluation board (EVB), RS-232 to USB cable, USB data cable, power adapter, earphone, antenna and other peripherals to control or test the module. For details, please refer to the document [12]. l e t l c a i e t u n Q fide n o C M80_HD_V1.
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M80 Hardware Design 3. Application interface The module is equipped with 110 pin SMT pad and it adopts LGA package. Detailed descriptions on Sub-interfaces included in these pads are given in the following chapters:          Power supply Turn on/off Power saving RTC UART interfaces Audio interfaces SIM interface USB interface ADC l e t l c a i e t u n Q fide n o C M80_HD_V1.
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M80 Hardware Design 3.1. Pin 3.1.1.
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M80 Hardware Design Table 5: M80 pin assignment PIN NO. PIN NAME I/O PIN NO.
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M80 Hardware Design 73 CHGLDO 75 RESERVED 77 CS_D3 79 74 GATDRV 76 RESERVED I 78 CS_D0 I CS_VSYNC I 80 CS_D4 I 81 CS_D7 I 82 CS_D5 I 83 CS_PWDN O 84 CS_D1 I 85 RESERVED 86 RESERVED 87 RESERVED 88 RESERVED 89 RESERVED 90 RESERVED 91 93 95 97 99 101 103 105 107 109 I O l e t l c a i e t u n Q fide n o C RESERVED 92 RESERVED GND 94 GND SIM2_RST O 96 CS_D2 I CS_PCLK I 98 CS_HSYNC I CS_MCLK O 100 CS_D6 I CS_RST O 102 RESERVED 104 RESERVED
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M80 Hardware Design VDD_EXT 60 GND 37, 61, 62, 64, 65, 66, 93, 94 O VBAT is supplied. Iin=2.6~5 uA Supply 2.8V voltage for external circuit. Vmax=2.9V Vmin=2.7V Vnorm=2.8V Imax=20mA 1. If unused, keep this pin open. 2. Recommend to add a 2.2~4.7uF bypass capacitor, when using this pin for power supply. Ground l e t l c a i e t u n Q fide n o C Charge interface PIN NAME PIN NO.
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M80 Hardware Design only when normal shutdown through PWRKEY or AT command can’t perform well. pin open. Module indicator PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS COMMENT STATUS 16 O Indicate module operating status. High level indicates module is power-on and low level indicates power-down. VOHmin= 0.85*VDD_EXT VOLmax= 0.15*VDD_EXT If unused, keep this pin open. DC CHARACTERISTICS COMMENT l e t l c a i e t u n Q fide n o C Audio interface PIN NAME PIN NO.
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M80 Hardware Design NETLIGH T 4 O Network status indication VOHmin= 0.85*VDD_EXT VOLmax= 0.15*VDD_EXT If unused, keep these pins open. Main UART port PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS COMMENT DTR 47 I Data terminal ready RXD 50 I Receiving data TXD 49 O Transmitting data VILmin=-0.3V VILmax= 0.25*VDD_EXT VIHmin= 0.75*VDD_EXT VIHmax= VDD_EXT+0.3 VOHmin= 0.85*VDD_EXT VOLmax= 0.15*VDD_EXT If only use TXD, RXD and GND to communicate, recommend keeping other pins open.
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M80 Hardware Design VOLmax=0.15*VDD_ EXT SIM1 interface PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS COMMENT SIM1_ VDD 56 O Power supply for SIM card The voltage can be selected by software automatically. Either 1.8V or 3V. SIM1_ DATA 54 I/O SIM data 3V： VOLmax=0.4 VOHmin= SIM1_VDD-0.4 1.8V: VOLmax= 0.15*SIM1_VDD VOHmin= SIM1_VDD-0.4 All signals of SIM interface should be protected against ESD with a TVS diode array.
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M80 Hardware Design VDD_EXT+0.3 SIM2 interface PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS COMMENT SIM2_ VDD 107 O Power supply for SIM card The voltage can be selected by software automatically. Either 1.8V or 3V. Not supported at present. SIM2_ DATA 109 I/O SIM data 3V： VOLmax=0.4 VOHmin= SIM1_VDD-0.4 1.8V: VOLmax= 0.15*SIM1_VDD VOHmin= SIM1_VDD-0.4 SIM2_ CLK l e t l c a i e t u n Q fide n o C 108 O SIM clock 3V： VOLmax=0.4 VOHmin= 0.9*SIM1_VDD 1.8V: VOLmax= 0.
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M80 Hardware Design converter. PCM PIN NAME PIN NO. I/O DESCRIPTION DC CHARACTERISTICS COMMENT PCM_CLK 19 O PCM clock PCM_IN 18 I PCM data input Not supported at present. PCM_OUT 20 O PCM data output PCM_ SYNC 21 O PCM frame synchronization VILmin=-0.3V VILmax= 0.25*VDD_EXT VIHmin= 0.75*VDD_EXT VIHmax= VDD_EXT+0.3 VOHmin= 0.85*VDD_EXT VOLmax= 0.15*VDD_EXT COMMENT l e t l c a i e t u n Q fide n o C USB interface PIN NAME PIN NO.
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M80 Hardware Design CS_D6 100 I CS_D7 81 I CS_ VSYNC 79 I Camera frame synchronization CS_ HSYNC 98 I Camera horizontal synchronization CS_RST 101 O Camera reset CS_MCLK 97 O Camera clock CS_PCLK 99 I Camera pixel clock CS_PWDN 83 O Camera power down VDD_EXT+0.3 VOHmin= 0.85*VDD_EXT VOLmax= 0.15*VDD_EXT l e t l c a i e t u n Q fide n o C VCAMD 58 O Camera digital power VCAMA 105 O Camera analog power PIN NAME PIN NO.
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M80 Hardware Design 87, 88, 89, 90, 91, 92, 102, 103, 104, 106, 110 l e t l c a i e t u n Q fide n o C M80_HD_V1.
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M80 Hardware Design 3.2. Operating modes The table below briefly summarizes the various operating modes in the following chapters. Table 7: Overview of operating modes Mode Function Normal operation GSM/GPRS SLEEP The module will automatically go into SLEEP mode if DTR is set to high level and there is no interrupt (such as GPIO interrupt or data on UART port). In this case, the current consumption of module will reduce to the minimal level.
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M80 Hardware Design 1) Use the EMERG_OFF pin only while failing to turn off the module by the command “AT+QPOWD=1” and the PWRKEY pin. Please refer to Section 3.4.2.2. 3.3. Power supply 3.3.1. Feature of GSM power The unit of GSM transmit in the wireless path is pulse string which is constructed by GSMK bit string and we call it burst. The period of burst is 4.16ms and the last time of burst is 577us. The burst current will reach 1.6A while idle current is as low as tens of milliampere.
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M80 Hardware Design (0.1µF to 1µF) ceramic capacitor should be in parallel with the 100µF capacitor, which is illustrated in Figure 4. The capacitors should be placed close to the M80 VBAT pins. The PCB traces from the VBAT pads to the power source must be wide enough to ensure that there isn’t too much voltage drop occurring in the transmitting burst mode. The width of trace should be no less than 2mm and the principle of the VBAT trace is the longer, the wider.
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M80 Hardware Design l e t l c a i e t u n Q fide n o C Figure 5: Reference circuit of the source power supply input 3.3.4. Monitor power supply To monitor the supply voltage, you can use the “AT+CBC” command which includes three parameters: charging status, remaining battery capacity and voltage value (in mV). It returns the 0-100 percent of battery capacity and actual value measured between VBAT and GND. The voltage is automatically measured in period of 5s.
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M80 Hardware Design receive data depends on the level of RTS and CTS. Then whenever hardware flow is present or not, the URC “RDY” is sent to host controller in the fixed band rate. 3.4.1.1. Power on module using the PWRKEY pin Customer’s application can turn on the module by driving the pin PWRKEY to a low level voltage and after STATUS pin outputs a high level, PWRKEY pin can be released. Customer may monitor the level of the STATUS pin to judge whether the module is power-on or not.
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M80 Hardware Design 1 VBAT 54ms >1s 250ms PWRKEY (INPUT) VIH > 0.6*VBAT VIL<0.1*VBAT VDD_EXT （OUTPUT） l e t l c a i e t u n Q fide n o C EMERG_OFF （INPUT） 800ms STATUS （OUTPUT） Figure 8: Timing of turning on system ① Make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is recommended 30ms. Note: Customer can monitor the voltage level of the STATUS pin to judge whether the module is power-on. After the STATUS pin goes to high level, PWRKEY may be released.
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M80 Hardware Design 3.4.2.1. Power down module using the PWRKEY pin Customer’s application can turn off the module by driving the PWRKEY to a low level voltage for certain time. The power-down scenario is illustrated in Figure 9. The power-down procedure causes the module to log off from the network and allows the software to save important data before completely disconnecting the power supply, thus it is a safe way.
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M80 Hardware Design 3.4.2.2. Power down module using AT command Customer’s application can turn off the module via AT command “AT+QPOWD=1”. This command will let the module to log off from the network and allow the software to save important data before completely disconnecting the power supply, thus it is a safe way.
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M80 Hardware Design 3.4.2.4. Emergency shutdown using EMERG_OFF pin The module can be shut down by driving the pin EMERG_OFF to a low level voltage over 20ms and then releasing it. The EMERG_OFF line can be driven by an Open Drain / Collector driver or a button. The circuit is illustrated as the following figures. EMERG_OFF 4.
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M80 Hardware Design 3.4.3. Restart 3.4.3.1. Restart module using the PWRKEY pin Customer’s application can restart the module by driving the PWRKEY to a low level voltage for certain time, which is similar to the way of turning on module. Before restarting the module, at least 500ms should be delayed after detecting the low level of STATUS. The restart timing is illustrated as the following figure. Delay > 0.
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M80 Hardware Design 3.5. Charging interface Not supported at present. 3.6. Power saving Upon system requirement, there are several actions to drive the module to enter low current consumption status. For example, “AT+CFUN” can be used to set module into minimum functionality mode and DTR hardware interface signal can be used to lead system to SLEEP mode. l e t l c a i e t u n Q fide n o C 3.6.1.
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M80 Hardware Design enter SLEEP mode automatically. In this mode, the module can still receive voice, SMS or GPRS paging from network but the UART port is not accessible. 3.6.3. Wake up module from SLEEP mode When the module is in the SLEEP mode, the following methods can wake up the module.  If the DTR Pin is set low, it would wake up the module from the SLEEP mode. The UART port will be active within 20ms after DTR is changed to low level.  Receiving a voice or data call from network wakes up module.
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M80 Hardware Design MODULE VRTC 1.5K RTC Core Non-chargeable Backup Battery Figure 14: RTC supply from non-chargeable battery l e t l c a i e t u n Q fide n o C MODULE VRTC 1.5K RTC Core Rechargeable Backup Battery Figure 15: RTC supply from rechargeable battery MODULE VRTC 1.5K Large-capacitance Capacitor RTC Core Figure 16: RTC supply from capacitor Coin-type rechargeable capacitor such as XH414H-IV01E from Seiko can be used. M80_HD_V1.
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M80 Hardware Design l e t l c a i e t u n Q fide n o C Figure 17: Seiko XH414H-IV01E Charge Characteristics 3.9. Serial interfaces The module provides three serial ports: UART, Debug Port and Auxiliary UART Port. The module is designed as a DCE (Data Communication Equipment), following the traditional DCE-DTE (Data Terminal Equipment) connection. Autobauding function supports baud rate from 4800bps to 115200bps.
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M80 Hardware Design The Auxiliary UART Port  TXD_AUX: Send data to the RXD of DTE  RXD_AUX: Receive data from the TXD of DTE The logic levels are described in the following table. Table 9: Logic levels of the UART interface Parameter Min Max Unit VIL -0.3 0.25*VDD_EXT V VIH 0.75*VDD_EXT VDD_EXT +0.3 V 0.15*VDD_EXT V VOL VOH l e t l c a i e t u n Q fide n o C 0.
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M80 Hardware Design 4800, 9600, 19200, 38400, 57600, 115200. After setting a fixed baud rate or Autobauding, please send “AT” string at that rate. The UART port is ready when it responds “OK”. Autobauding allows the module to detect the baud rate by receiving the string “AT” or “at” from the host or PC automatically, which gives module flexibility without considering which baud rate is used by the host controller. Autobauding is enabled in default.
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M80 Hardware Design Module (DCE) PC (DTE) UART Port UART port TXD RXD RTS CTS DTR DCD TXD RXD RTS CTS DTR DCD RI RING l e t l c a i e t u n Q fide n o C GND GND Figure 18: Connection of all functional UART port Three lines connection is shown as below. Module(DCE) Host(DTE) controller UART PORT TXD TXD RXD RXD GND GND RTS 0R Figure 19: Connection of three lines UART port UART Port with hardware flow control is shown as below.
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M80 Hardware Design Module(DCE) Host(DTE) controller UART PORT TXD TXD RXD RXD RTS RTS CTS CTS GND GND l e t l c a i e t u n Q fide n o C Figure 20: Connection of UART port associated hardware flow control 3.9.1.3. Software upgrade The TXD, RXD can be used to upgrade software. The PWRKEY pin must be pulled down before the software upgrade. Please refer to the following figures for software upgrade.
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M80 Hardware Design 3.9.2. Debug Port Debug Port  Two lines: DBG_TXD and DBG_RXD  It outputs log information automatically.  Debug Port is only used for software debugging and its baud rate must be configured as 460800bps. Module(DCE) Debug Computer Debug port l e t l c a i e t u n Q fide n o C DBG_TXD TXD DBG_RXD RXD GND GND Figure 22: Connection of software debug 3.9.3.
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M80 Hardware Design 3.9.4. UART Application The reference design of 3.3V level match is shown as below. 1K resistors among the following diagram are used to decrease the output voltage of MCU/ARM. MODULE MCU/ARM VBAT GND /TXD 1K RXD TXD l e t l c a i e t u n Q fide n o C /RXD /RTS /CTS GPIO 1K 1K RTS CTS DTR EINT RI GPIO STATUS voltage level: 3.3V Figure 24: 3.3V level match circuit Note: The above reference design is also suitable for 3V system. M80_HD_V1.
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M80 Hardware Design The reference design of 5V level match is shown as below. The construction of dotted line can refer to the construction of solid line. Please pay attention to direction of connection. Input dotted line of module should refer to input solid line of the module. Output dotted line of module should refer to output solid line of the module. MCU/ARM MODULE VDD_EXT 4.7k VBAT GND 4.7k VCC_MCU 1K /TXD RXD TXD /RXD l e t l c a i e t u n Q fide n o C 4.7k 4.
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M80 Hardware Design The following picture is an example of connection between module and PC. A RS_232 level shifter IC or circuit must be inserted between module and PC, since these three UART ports don’t support the RS_232 level, while support the CMOS level only.
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M80 Hardware Design 3.10. Audio interfaces The module provides two analogy input channels and three analogy output channels.
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M80 Hardware Design For each channel, customer can use AT+QMIC to adjust the input gain level of microphone. Customer can also use “AT+CLVL” to adjust the output gain level of receiver and speaker. “AT+QECHO” is used to set the parameters for echo cancellation control. “AT+QSIDET” is used to set the side-tone gain level. For more details, please refer to document [1]. Table 12: AOUT3 output characteristics Item Condition min type max unit RMS power 8ohm load VBAT=4.
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M80 Hardware Design The differential audio traces have to be placed according to the differential signal layout rule. 3.10.2. Microphone interfaces design AIN1/IN2 channels come with internal bias supply for external electret microphone. A reference circuit is shown in Figure 27.
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M80 Hardware Design 3.10.3. Receiver and speaker interface design Close to speaker GND Differential layout Module 10pF 33pF 10pF 33pF 10pF 33pF ESD ANTI SPK1P l e t l c a i e t u n Q fide n o C SPK1N ESD ANTI GND Figure 28: Receiver interface design of AOUT1 Close to speaker GND Differential layout 10pF Module SPK2P 22uF 33pF ESD ANTI AGND Figure 29: Handset interface design of AOUT2 M80_HD_V1.
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M80 Hardware Design Close to speaker GND Differential layout Module SPK2P Amplifier circuit 10pF 33pF ESD ANTI 10pF 33pF ESD ANTI C1 AGND C2 l e t l c a i e t u n Q fide n o C GND Figure 30: Speaker interface with amplifier design of AOUT2 Texas Instrument’s TPA6205A1is recommended for a suitable differential audio amplifier. There are plenty of excellent audio amplifiers in the market. Note: The value of C1 and C2 depends on the input impedance of audio amplifier. 3.10.4.
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M80 Hardware Design 3.10.5. Loud speaker interface design Close to speaker GND Differential layout 10pF 33pF ESD ANTI 0R Module LOUDSPKP 100pF 0R LOUDSPKN l e t l c a i e t u n Q fide n o C 10pF 33pF ESD ANTI GND Figure 32: Loud speaker interface design M80_HD_V1.
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M80 Hardware Design 3.10.6. Audio characteristics Table 13: Typical electret microphone characteristics Parameter Min Typ Max Unit Working Voltage 1.2 1.5 2.0 V Working Current 200 500 uA External Microphone Load Resistance 2.
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M80 Hardware Design Table 15: Pin definition of the SIM interface Name Pin Function SIM1_VDD 56 Supply power for SIM Card. Automatic detection of SIM card voltage. 3.0V±10% and 1.8V±10%. Maximum supply current is around 10mA.
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M80 Hardware Design 1uF SIM CARD C707 10M006 512 2 SIM1_VDD SIM1_RST Module VCC RST CLK 22R SIM1_CLK 22R SIM1_DATA GND VPP I/O 22R SMF05C l e t l c a i e t u n Q fide n o C GND Figure 34: Reference circuit of the 6 pins SIM card 3.11.2. 6 Pin SIM cassette For 6-pin SIM card holder, it is recommended to use Amphenol C707 10M006 512 2. Please visit http://www.amphenol.com for more information. Figure 35: Amphenol C707 10M006 512 2 SIM card holder M80_HD_V1.
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M80 Hardware Design Table 16: Pin description of Amphenol SIM card holder Name Pin Function SIM_VDD C1 SIM Card Power Supply SIM_RST C2 SIM Card Reset SIM_CLK C3 SIM Card Clock GND C5 Ground VPP C6 Not Connect SIM_DATA C7 SIM Card data I/O l e t l c a i e t u n Q fide n o C 3.11.3. 8 Pin SIM cassette For 8-pin SIM card holder, it is recommended to use Molex 91228. Please visit http://www.molex.com for more information.
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M80 Hardware Design SIM_CLK C3 SIM Card Clock SIM_PRESENCE C4 SIM Card Presence Detection GND C5 Ground VPP C6 Not Connect SIM_DATA C7 SIM Card Data I/O SIM_DETECT C8 Pulled down GND with external circuit. When the tray is present, C4 is connected to C8. 3.12. Camera interface l e t l c a i e t u n Q fide n o C Not supported at present. 3.13. SD card interface Not supported at present. 3.14. PCM interface Not supported at present. 3.15.
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M80 Hardware Design Module (DCE) IO Connector USB_DM USB_DM USB_DP USB_DP GND GND DOWNLOAD PWRKEY l e t l c a i e t u n Q fide n o C Figure 37: Connection of USB download 3.16. ADC The module provides two ADC to measure the value of voltage. Use AT command “AT+QADC” to read the voltage value on ADC1 pin. Use AT command “AT+QEADC” to read the voltage value on ADC0 pin. For details of this AT command, please refer to document [1].
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M80 Hardware Design Table 21: Behaviors of the RI State RI respond Standby HIGH Voice calling Change to LOW, then: (1) Change to HIGH when call is established. (2) Use ATH to hang up the call, change to HIGH. (3) Calling part hangs up, change to HIGH first, and change to LOW for 120ms indicating “NO CARRIER” as an URC, then change to HIGH again. (4) Change to HIGH when SMS is received.
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M80 Hardware Design HIGH RI Data calling establish. On-hook by “ATH”. SMS received LOW Idle Ring Figure 39: RI behavior of data calling as a receiver l e t l c a i e t u n Q fide n o C HIGH RI LOW Idle Calling Talking On-hook Idle Figure 40: RI behavior as a caller HIGH RI 120ms LOW Idle or talking URC or SMS Received Figure 41: RI behavior of URC or SMS received M80_HD_V1.
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M80 Hardware Design 3.18. Network status indication The NETLIGHT signal can be used to drive a network status indication LED. The working state of this pin is listed in Table 22. Table 22: Working state of the NETLIGHT State Module function Off The module is not running. 64ms On/ 800ms Off The module is not synchronized with network. l e t l c a i e t u n Q fide n o C 64ms On/ 2000ms Off The module is synchronized with network. 64ms On/ 600ms Off GPRS data transfer is ongoing.
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M80 Hardware Design VBAT 300R Module 4.7K STATUS 47K l e t l c a i e t u n Q fide n o C Figure 43: Reference circuit of the STATUS M80_HD_V1.
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M80 Hardware Design 4. Antenna interface The Pin 63 is the RF antenna pad. The RF interface has an impedance of 50Ω. Name Pin Function GND 62 ground GND 61 ground RF_ANT 63 RF antenna pad GND 66 ground GND 65 ground 64 ground GND l e t l c a i e t u n Q fide n o C 4.1. RF reference design The RF external circuit is recommended as below: 0R RF_ANT MODULE NM NM Figure 44: Reference circuit of RF M80 provides an RF antenna PAD for customer’s antenna connection.
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M80 Hardware Design 4.2. RF output power Table 24: The module conducted RF output power Frequency Max Min GSM850 33dBm ±2dB 5dBm±5dB EGSM900 33dBm ±2dB 5dBm±5dB DCS1800 30dBm ±2dB 0dBm±5dB PCS1900 30dBm ±2dB 0dBm±5dB l e t l c a i e t u n Q fide n o C Note: In GPRS 4 slots TX mode, the max output power is reduced by 2.5dB. This design conforms to the GSM specification as described in section 13.16 of 3GPP TS 51.010-1. 4.3.
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M80 Hardware Design l e t l c a i e t u n Q fide n o C Figure 45: RF soldering sample M80_HD_V1.
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M80 Hardware Design 5. Electrical, reliability and radio characteristics 5.1. Absolute maximum ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of module are listed in the following table: Table 27: Absolute maximum ratings l e t l c a i e t u n Q fide n o C Parameter Min Max Unit VBAT -0.3 +4.73 V Peak current of power supply 0 2 A RMS current of power supply (during one TDMA- frame) 0 0.7 A Voltage at digital pins -0.3 3.
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M80 Hardware Design IVBAT Voltage drop during transmitting burst Maximum power control level on GSM850 and GSM900. Voltage ripple Maximum power control level on GSM850 and GSM900 @ f<200kHz @ f>200kHz Average supply current 2) mV 50 2 mV mV POWER DOWN mode SLEEP mode @ DRX=5 30 1.
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M80 Hardware Design Table 30: The module current consumption Condition Current Consumption Voice Call GSM850 @power level #5 <300mA,Typical 217mA @power level #12,Typical 102mA @power level #19,Typical 79mA GSM900 @power level #5 <300mA,Typical 235mA @power level #12,Typical 109mA @power level #19,Typical 83mA DCS1800 @power level #0 <250mA,Typical 167mA @power level #7,Typical 92mA @power level #15,Typical 75mA PCS1900 @power level #0 <250mA,Typical 163mA @power level #7,Typical 91mA @power level
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M80 Hardware Design DATA mode, GPRS ( 2 Rx, 3 Tx ) CLASS 12 GSM850 @power level #5 <600mA,Typical 412mA @power level #12,Typical 176mA @power level #19,Typical 102mA EGSM 900 @power level #5 <600mA,Typical 443mA @power level #12,Typical 189mA @power level #19,Typical 110mA DCS 1800 @power level #0 <490mA,Typical 308mA @power level #7,Typical 147mA @power level #15,Typical 97mA l e t l c a i e t u n Q fide n o C PCS 1900 @power level #0 <480mA,Typical 305mA @power level #7,Typical 146mA @power level
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M80 Hardware Design 5.5. Electro-static discharge Although the GSM engine is generally protected against Electrostatic Discharge (ESD), ESD protection precautions should still be emphasized. Proper ESD handling and packaging procedures must be applied throughout the processing, handling and operation of any applications using the module.
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M80 Hardware Design 6. Mechanical dimensions This chapter describes the mechanical dimensions of the module. 6.1. Mechanical dimensions of module l e t l c a i e t u n Q fide n o C Figure 46: M80 top and side dimensions（Unit: mm） M80_HD_V1.
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M80 Hardware Design l e t l c a i e t u n Q fide n o C Figure 47: M80 bottom dimensions（Unit: mm） M80_HD_V1.
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M80 Hardware Design 6.2. Footprint one of recommendation l e t l c a i e t u n Q fide n o C frame line silkscreen Figure 48: Footprint one of recommendation（Unit: mm） M80_HD_V1.
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M80 Hardware Design 6.3. Footprint two of recommendation l e t l c a i e t u n Q fide n o C frame line silkscreen Figure 49: Footprint two of recommendation（Unit: mm） Note：In order to maintain the module, keep about 3mm away between the module and other components in host PCB. M80_HD_V1.
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M80 Hardware Design 6.4. Top view of the module l e t l c a i e t u n Q fide n o C Figure 50: Top view of the module M80_HD_V1.
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M80 Hardware Design 6.5. Bottom view of the module l e t l c a i e t u n Q fide n o C Figure 51: Bottom view of the module M80_HD_V1.
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M80 Hardware Design 7. Storage and Manufacturing 7.1. Storage M80 is distributed in vacuum-sealed bag. The restriction of storage condition is shown as below.
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M80 Hardware Design 7.2. Soldering The squeegee should push the paste on the surface of the stencil that makes the paste fill the stencil openings and penetrate to the PCB. The force on the squeegee should be adjusted so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil at the hole of the module pads should be 0.13mm for M80.
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M80 Hardware Design ℃ Preheat Heating Cooling 250 Liquids Temperature 217 200℃ 200 40s~60s 160℃ 150 70s~120s 100 l e t l c a i e t u n Q fide n o C Between 1~3℃/S 50 0 50 100 150 200 250 300 s Time(s) Figure 53: Ramp-Soak-Spike reflow profile 7.3. Packaging M80 modules are distributed in trays of 20 pieces each. This is especially suitable for the M80 according to SMT processes requirements. The trays are stored inside a vacuum-sealed bag which is ESD protected.
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M80 Hardware Design Appendix A: GPRS coding schemes Four coding schemes are used in GPRS protocol. The differences between them are shown in Table 32. Table 32: Description of different coding schemes Scheme CS-1 CS-2 CS-3 CS-4 Code rate USF Pre-coded USF Radio Block excl.USF and BCS BCS Tail Coded bits Punctured bits Data rate Kb/s l e t l c a i e t u n Q fide n o C 1/2 3 3 181 40 4 456 0 9.05 2/3 3 6 268 16 4 588 132 13.4 3/4 3 6 312 16 4 676 220 15.
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M80 Hardware Design Appendix B: GPRS multi-slot classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependant, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
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