2.4G Module 2.4G Module DKL 1908_V.1 The content of this technical document is subject to change without notice. Please contact UBEC for further information. Version: 0.0 Released Date: 2018/05/08 All rights are strictly reserved. Any portion of this document shall not be reproduced, copied, or transformed to any other forms without prior permission from Uniband Electronic Corp. DS-2472-01
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DKL 1908_V.1 Low Power 2.4GHz DSSS Transceiver Applications RF Remote Control Interactive Wireless Toy and Game Wireless Audio/Video Wireless Consumer Electronics Wireless Keyboard Mouse Wireless Lighting Control Introduction The DKL 1908_V.1 is a 2.4 GHz Direct Sequence Spread Spectrum (DSSS) / Minimum-Shift Keying (MSK) RF transceiver with integrated baseband and MAC in a single chip. Targeting for the low cost and low power applications, the DKL 1908_V.
Features RF/Analog Worldwide 2.
Table of Content Applications ..........................................................................................................................................3 Introduction .........................................................................................................................................3 Features ...............................................................................................................................................4 1. Pin Configuration ...............
4.6. RX ........................................................................................................................................ 31 4.7. Power Saving......................................................................................................................... 31 4.8. Wake-up ............................................................................................................................... 31 5. Package Information .......................................................
Abbreviations ACK ADC CCM CRC DSSS EMI ESD EVM FCF FCS FIFO INT ISM ITU-T I/O I/Q Kbps LNA LO LSB MSB MAC NA NC O-QPSK PA PCB PHY PLL QFN RF RX SPI SFD TBD TX VCO Acknowledgement Analog to Digital Converter Counter Channel Mode Cyclic Redundancy Check Direct Sequence Spread Spectrum Electro Magnetic Interference Electronic Static Discharge Error Vector Magnitude Frame Control Field Frame Check Sequence First In First Out Interrupt Industrial Scientific and Medical International Telecommunication Union - Te
Format Representations of Registers and Their Bits 1. REG0xnn[m] or REG0xnn[p:m] REG: register 0xnn: register number nn: can be numerical numbers (for example:1, 2, or 3, etc) or alphabetical words (for example: A, B, or C, etc) [m]: the bit number [p:m]: bit m to bit p (for example: bit[7:5] means bit 7, bit 6, and bit 5) DS-2472-01
1. Pin Configuration GND_PLL VDD_VCO VDD_PLL XTAL_P 1.1. Device Pin Assignments 16 15 14 13 RF_P 1 12 XTAL_N RF_N 2 11 RESETn 17 SEN VDD_D 4 9 SCLK GND 5 6 7 8 SO 10 SI/SIO 3 INT VDD_RF Figure 1. Pin Assignments (Top View) DS-2472-01
1.2.
2. Electrical Characteristics 2.1. Absolute Maximum Ratings Parameters Min Max Unit Storage temperature -40 +120 ℃ Supply voltage VDD pin to the ground -0.5 +3.6 V Voltage applied to inputs -0.5 VDD+0.5 V 5 sec Short circuit duration, to GND, or VDD Table 2. Absolute Maximum Ratings 2.2. Recommended Operating Conditions Test conditions: VDD = 3 V Parameters Min Ambient Operating Temperature -20 Supply Voltage for VDD 2.1 Logical high input voltage (for DI type pins) 0.
2.4. ESD Characteristics Human-body mode All pins pass 2KV Machine mode All pins pass 200V 2.5. AC Characteristics 2.5.1. Receiver Test conditions: TA = 25℃, VDD_IO = 3 V, LO frequency=2.445 GHz Parameters Test Conditions Min ISM band RF frequency range Recommended operating frequency range for band-edge limitation (for example: FCC/CE regulation) RF sensitivity Typ 2400 2408 Max Unit 2483.
2.6. Power-on and External Reset Characteristics The DKL 1908_V.1 has built-in power-on reset (POR) circuit which automatically resets all digital registers when the power is turned on. For stabilization of the complete circuit after the power-on reset, it is highly recommended to wait at least 3ms before starting the normal operation of the DKL 1908_V.1. For external hardware reset (warm start), external reset pin RESETn is internally pulled high. The DKL 1908_V.
3. Functional Description The DKL 1908_V.1 is composed of the following five blocks: PHY MAC Memory Power Management Interface Lower MAC Interface PHY Power Management Memory Figure 2. Block Diagram of DKL 1908_V.1 3.1. PHY The architecture of PHY is shown in Figure 3. Figure 3. PHY Architecture DS-2472-01
The key features of the DKL 1908_V.1 PHY are: RF frequency ranges from 2400 to 2483.5 MHz with 1MHz programmable resolution. Offset QPSK (O-QPSK) modulation with DSSS : 125kbps and 250kbps. Minimum-Shift Keying (MSK) : 1Mbps, and 2 Mbps Innovative and patented on-fly multi-rate detection For all MSK modes, 4:32 spreading codes of DSSS are used for PHY header including preamble, SFD and Frame Length (FL) but no spreading codes are used for the PHY payload data.
3.1.1. State Machine Control Radio state diagram RES_CMD: External reset pin or SW reset (REG0x34[0]) or REG0x36[2] TX_START: TXFIFO trigger REG0x1B[0] SLEEP_REQ: REG0x35[7] WAKE_UP: External pin wake-up or timed wake-up or wake-up by register REG0x22[6] DKL 1908_V.1 has five radio states designated IDLE, VCO calibration, TX, RX and SLEEP as above Figure. The response times between theses states are listed in the table below. In IDLE state, RF circuit is shutdown.
Response Time to Chip Mode Unit RX TX TX 144 N/A u sec RX N/A 192 u sec STANDBY 1600 * u sec DEEP SLEEP 1600 * u sec POWER DOWN 1600 + Initialization Time * u sec * DKL 1908_V.1 will enter RX mode after wake up from each SLEEP modes. 3.2. MAC The DKL 1908_V.1 MAC provides plenty of hardware-assisted features to relieve the loadings of the host MCU.
3.2.1. MAC Frame Format Figure 6. MAC Frame Format The MAC frame format is composed of a frame control field (FC), a destination address field, a payload field and a frame check sequence field. The frame control field (FC) is one byte in length and contains ACK request (bit0), frame type (bit1) and group ID (bit2). The bit 0 of frame control (FC) field is used for Ack-Request which specifies whether an acknowledgement is required from the recipient device.
1 byte 2 bytes 2 bytes Frame Control Payload Frame Check Sequence MAC header MAC Payload MAC footer PHY header PHY Payload Figure 7. Acknowledgement Frame Format The length of acknowledgement frame is always 5 bytes. Bit 1 of FC field is ‘1’ for ACK frame. The payload field, containing user information of acknowledgement frame, can be configured by REG0x03 and REG0x04. The FCS is calculated over the FCS of the received packet, FC field and the payload field.
3.2.4. RXMAC TXMAC Registers RX Baseband RXFIFO RX PHY filters signals and tracks the synchronization symbols. If a packet passes the filtering, RXMAC Lower MAC Memory performs frame typePHY parsing, address recognition and FCS checking. If the destination address is broadcast address or matches its own identity, configured by REG0x05 to REG0x08, and the FCS check is RXMAC passed, an interrupt is issued at REG0x31[3] to indicate a valid packet is received. Meanwhile, the frame RXFIFO.
3.3. Memory The memory block of the DKL 1908_V.1 is implemented by the SRAM. It is composed of registers and FIFOs, which can be accessed by the SPI interfaces. Figure 10. Memory Space Diagram • • • Registers: 0x00~0x3F (support R/W during sleep) TXFIFO: page0 : 0x41~0x67 (support R/W during sleep) RXFIFO: page1 : 0x40~0x68 FIFOs Registers Interface TX FIFO RX FIFO Lower MAC Figure 11. Memory Block Diagram DS-2472-01
3.3.1. Registers Registers provide control bits and status flags for the DKL 1908_V.1 operations, including transmission, reception, interrupt control, MAC/baseband/RF parameter settings …etc. 3.3.2. FIFOs TXFIFO The TXMAC gets the to-be transmitted data from the 38-byte TXFIFO. The memory space of TXFIFO is from ‘0x041’ to ‘0x67’ of page 0 and contains a FL field, address field, FC field and payload field. The FL field indicat0xes the length of the address field, FC field and the payload field.
3.4. Power Management Almost all wireless sensor network applications require low-power consumption to lengthen battery life. Typical battery-powered device is required to be operated over years without replacing its battery. The DKL 1908_V.1 achieves low active current consumption of both the digital and the RF/analog circuits by controlling the supply voltage and using low-power architecture. The DKL 1908_V.1 has four power saving modes that will be further described in Section 3.4.4.
3.5. Interface 3.5.1. SPI The slave SPI is supported for host MCU to read/write the control registers and FIFO of the DKL 1908_V.1. The features are as below: A simple 3-wire slave SPI (SIO, SCLK and SEN). A simple 4-wire slave SPI (SO, SI, SCLK and SEN) Most significant bit (MSB) of all addresses and data transfers on the SPI is done first. SPI Addressing Format Bit 0 is a one-bit read/write indicator. The other bits, from bit 7 to bit 1, indicate the SPI address. Figure 14.
SPI Characteristics Parameter Symbol SCLK, clock frequency FSCLK Min Max Units 5 MHz Conditions SCLK low pulse duration tCL 100 ns The minimum time SCLK must be low. SCLK high pulse duration tCH 100 ns The minimum time SCLK must be high. SEN setup time tSP 100 ns The minimum time SEN must be low before the first SEN hold time tNS 100 ns The minimum time SEN must be held low after the last positive edge of SCLK. negative edge of SCLK.
Figure 15. Timing Diagram of 4-wire slave SPI tsd tsp thd tch tcl tns SCLK SEN read data SIO A7 A6 A5 A4 A3 A2 A1 0 Q17 Q16 Q15 Q14 Q13 Q12 Q11 Q10 Q27 Q26 Q25 Q24 Q23 Q22 Q21 Q20 write data SIO A7 A6 A5 A4 A3 A2 A1 1 D17 D16 D15 D14 D13 D12 D11 D10 D27 D26 D25 D24 D23 D22 D21 D20 Figure 16. Timing Diagram of 3-wire slave SPI DS-2472-01
3.5.2. Interrupt Signal The DKL 1908_V.1 provides an output interrupt pin (pin 6, INT) with selectable polarity. The DKL 1908_V.1 issues interrupts to the host MCU on three possible events. For each event, the DKL 1908_V.1 sets the corresponding status bit in REG0x31. If the corresponding interrupt mask in REG0x32 is clear (i.e. equals ‘0’), an interrupt will be issued on pin 6. If it is set to ‘1’ (masked), no interrupt will be issued, but the status is still present.
4. Application Guide 4.1. Initialization After DKL 1908_V.1 is powered on, some registers need to be configured before the data transmitting or reception. The procedure is described as below. DKL 1908_V.1 Initialization (4-wire SPI)* Register Note do{Uz2472WriteReg(0x05,0x5c);} while((Uz2472ReadReg(0x05) & Wait power on stable.
Different data rate setting as following table: Data rate Register 125K 1M 250K 2M REG0x38 0x80 0x81 0x82 0x83 If change data rate after initialization, it must do following calibration procedure. REG0x14 0x06 REG0x36 0x20 REG0x37 0x12 Wait 2mS REG0x12 0x6A Wait 8mS REG0x12 0x68 REG0x37 0x02 REG0x36 0x00 REG0x14 0x02 4.2. Change Channel Set RF operation channel by configuring REG0x10. DKL 1908_V.1 will go to RX state after 192us. 4.3.
4.5. TX For TX operation, the TXMAC of DKL 1908_V.1 automatically generates the preamble, Start-of-Frame delimiter and the FCS. The host MCU needs to write all other frame fields into TXFIFO. To send a packet in TX FIFO, there are several steps to follow: Step 1. Fill necessary data in TXFIFO. The format of TXFIFO is as follows: Step 2. Set Ackreq by REG0x1B[2], if an acknowledgement / retransmission is required. The DKL 1908_V.
4.6. RX When a valid packet is received, an interrupt is issued at REG0x31[3]. The MCU host can read the whole packet inside the RXFIFO. The RXFIFO is flushed when the frame length field and the last byte of RXFIFO are read, or when the host triggers a RX flush by REG0x0D[0]. 4.7. Power Saving Standby, Deep-Sleep and Power-Down modes are designed for DKL 1908_V.1. It is only allowed to switch between power saving modes and active mode. The following settings are effective in active mode only.
5. Package Information 5.1. Package Drawing The QFN-16 package outline is given below. QFN-16, 3x3mm2 DS-2472-01
5.2. Package Soldering 5.2.1. Background The DKL 1908_V.1 is housed in a small 16-pin lead-free QFN 3x3 mm2 package. DKL 1908_V.1 can also be packaged as 12 pin or 8 pin SOP package. The packaged part passes the Level 3 pre-condition testing. 5.2.2. Reference Reflow Temperature Profile Figure 18 is the reference temperature profile for the SMD IR reflow. Different equipments may have different optimized reflow conditions for maximum yield.
Appendix A. TX Power Configuration Default output power is 11 dBm. Different output power settings are listed in the table below.
Appendix B. Register Descriptions Register Types Register Type Description R/W Read/Write register WT Write 1 to trigger register, automatically cleared by hardware RC Read to clear register R Read-only register R/W1C Read/Write ‘1’ to clear register B.
REG0x01: PIPE ENABLE Bit Bit Bit Bit Bit Bit Bit Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r PIPEN6 PIPEN5 PIPEN4 PIPEN3 PIPEN2 PIPEN1 PIPEN0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 7 6 5 4 3 2 1 0 Reserved: Maintain as ‘0b0’ PIPEN6: Broadcasting frame enable PIPEN5: Pipe5 enable PIPEN4: Pipe4 enable PIPEN3: Pipe3 enable PIPEN2: Pipe2 enable PIPEN1: Pipe1 enable PIPEN0: Pipe0 enable REG0x02: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r PIPE6 PIPEN5
REG0x03: ACKNOWLEDGEMENT USER INFORMATION LOW BYTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 AUINF7 AUINF6 AUINF5 AUINF4 AUINF3 AUINF2 AUINF1 AUINF0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 7-0 Bit1 Bit 0 AUINF[7:0]: 16-bit User Information of Acknowledgement frame, Low Byte REG0x04: ACKNOWLEDGEMENT USER INFORMATION HIGH BYTE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 AUINF15 AUINF14 AUINF13 AUINF12 AUINF11 AUINF10 AUINF9 AUINF8 R/W-0 R/W-0 R/W-0 R/W-0
REG0x05: PIPE0 ADDRESS 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 P0ADDR7 P0ADDR6 P0ADDR5 P0ADDR4 P0ADDR3 P0ADDR2 P0ADDR1 P0ADDR0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 2 Bit1 Bit 0 Bit 7-0 P0ADDR[7:0]: Pipe0 address[7:0] REG0x06: PIPE0 ADDRESS 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 P0ADDR15 P0ADDR14 P0ADDR13 P0ADDR12 P0ADDR11 P0ADDR10 P0ADDR9 P0ADDR8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 2 Bit1 Bit 0 Bit 7-0 P0ADDR[15:8]: Pipe0
REG0x09: PIPE1 ADDRESS 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 P1ADDR7 P1ADDR6 P1ADDR5 P1ADDR4 P1ADDR3 P1ADDR2 P1ADDR1 P1ADDR0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 2 Bit1 Bit 0 Bit 7-0 P1ADDR[7:0]: Pipe1 address[7:0] REG0x0a: PIPE1 ADDRESS 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 P1ADDR15 P1ADDR14 P1ADDR13 P1ADDR12 P1ADDR11 P1ADDR10 P1ADDR9 P1ADDR8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 2 Bit1 Bit 0 Bit 7-0 P1ADDR[15:8]: Pipe1
REG0x0D: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r r r r r r DISTXW RXFLUSH R-0 R-0 R-0 R-0 R-0 R-0 R/W-0 WT-0 Bit 7 Bit 1 Reserved: Maintain as ‘0b000000’ DISTXW: Disable the function of TX trigger after register wakeup 1: Disable the function of TX trigger after register wakeup 0: Enable the function of TX trigger after register wakeup Bit 0 RXFLUSH: Flush the RX FIFO 1: Flush RX FIFO. RX FIFO data is not modified.
REG0x10: RF CHANNEL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r 1MFRCH6 1MCSCH5 1MCSCH4 1MCSCH3 1MCSCH2 1MCSCH1 1MCSCH0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 Bit 7 Bit 6-0 Reserved: Maintain as ‘0b0’ 1MCSCH: 1 MHz Channel Spacing Channel Number 0100100: 2436 0000000: 2400 MHz 0100101: 2437 0000001: 2401 MHz 0100110: 2438 0000010: 2402 MHz 0100111: 2439 0000011: 2403 MHz 0101000: 2440 0000100: 2404 MHz 0101001: 2441 0000101: 2405 MHz 0101010: 2442 0000110: 2406 MHz 010
REG0x11: VCO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 CALWT1 CALWT0 VCOSB4 VCOSB3 VCOSB2 VCOSB1 VCOSB0 ICTLPA0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 Bit 7-6 Bit 5-1 Bit 0 CALWT[1:0]: VCO calibration wait time 00: 1.25u S 01: 2.
REG0x13: PLL_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 LOCKEN FILTERV1 FILTERV0 LF3R1 LF3R0 LF2R2 LF2R1 LF2R0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 Bit 7 Bit 6-5 Bit 4-3 Bit 2-0 LOCKEN: Lock detector enable 0: Disable 1: Enable (default) FILTERV[1:0]: Filter voltage option 00: 0.875 V (default) 01: 0.9 V 10: 0.925 V 11: 0.
REG0x14: PLL_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r r FILTERI1 FILTERI0 CPI CPVCO PRSI1 PRSI0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 Bit 7-6 Bit 5-4 Bit 3 Bit 2 Bit 1-0 Reserved: Maintain as ‘0b00’ FILTERI[1:0]: Filter current option 00: 12.5u A (default) 01: 25u A 10: 37.
REG0x15: PLL_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 VCORX1 VCORX0 VCOTX1 VCOTX0 LOBRX1 LOBRX0 LOBTX1 LOBTX0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 Bit 7-6 Bit 5-4 Bit 3-2 Bit 1-0 VCORX[1:0]: VCO current option for RX 00: 2.25m A 01: 2.475m A (default) 10: 2.7m A 11: 2.925m A VCOTX[1:0]: VCO current option for TX 00: 2.25m A 01: 2.475m A (default) 10: 2.7m A 11: 2.925m A LOBRX[1:0]: LO buffer current option for RX 00: 1.25m A (default) 01: 1.5m A 10: 1.
REG0x16: PA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 DIV2TX1 DIV2TX0 PAI2 PAI1 PAI0 PABUF1 PABUF0 PAMODE R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 Bit 7-6 Bit 5-3 Bit 2-1 Bit 0 DIV2TX[1:0]: Divide-by-2 current option for TX 00: 1.25m A (default) 01: 1.5m A 10: 1.75m A 11: 2m A PAI[2:0]: PA reference current Iref option 000: 50u A 001: 75u A 010: 100u A 011: 125u A 100: 150u A 101: 175u A 110: 200u A 111: 225u A (default) PABUF[1:0]: PA buffer current option 00: 1.
REG0x17: WAKE UP Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 XTALC1 XTALC0 WAKEC2 WAKEC1 WAKEC0 LDOSM SLEEPM1 SLEEPM0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 WT-0 Bit 7-6 Bit 5-3 Bit 2 Bit 1-0 XTALC[1:0]: Crystal load capacitor control 00: 16p F (default) 01: 20p F 10: 20p F 11: 24p F WAKEC[2:0]: Number of slow clock cycles to wake digital circuit up 000: 5 (default) 001: 6 010: 7 …… LDOSM: Digital LDO sleep mode control 0: Deep sleep and standby mode (default) 1: power down
REG0x18: SLEEP MODE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 SLEEPVM1 SLEEPVM0 SLEEPVMC BTMEN LOOPV1 LOOPV0 LDOD LDODB R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 WT-0 Bit 7-6 Bit 5 Bit 4 Bit 3-2 Bit 1 Bit 0 SLEEPVM[1:0]: Manual voltage supply in sleep mode 00: 1.8~2.3 V 01: 2.3~2.8 V 10: 2.8~3.2 V (default) 11: 3.2~3.
REG0x19: FREQUENCY DIGITAL TUNE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 FDTUNE7 FDTUNE 6 FDTUNE 5 FDTUNE 4 FDTUNE 3 FDTUNE 2 FDTUNE 1 FDTUNE 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 WT-0 Bit 7-0 FDTUNE[7:0]: RF digital frequency tuning 1 LSB reduces the RF frequency by 977 Hz REG0x1A: SLEEP MODE_2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 MIXERV1 MIXERV0 RAMPUD CAPADJ1 CAPADJ0 r LOCKC1 LOCKC0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R-1 R/W-1 WT-1 Bit 7-
REG0x1B: TRANSMIT FIFO CONTROL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 TXRTYN3 TXRTYN2 TXRTYN1 TXRTYN0 r TXACKREQ r TXTRIG R/W-0 R/W-0 R/W-1 R/W-1 R-0 R/W-0 R-0 WT-0 Bit 7-4 Bit 3 Bit 2 Bit 1 Bit 0 TXRTYN: Maximum TX Retry Times 0000: 0 … 0011: 3 (default) … 1111: 15 Reserved: Maintain as ‘0b0’ TXACKREQ: TX FIFO Acknowledgement Request bit Transmit a packet with Acknowledgement request. If Acknowledgement is not received, the DKL 1908_V.1 retransmits up to TXRTYN times.
REG0x1C: Group0 ID Bit 7 G0ID7 R/W-0 Bit 7-0 Bit 6 G0ID6 R/W-0 Bit 5 G0ID5 R/W-0 Bit 4 G0ID4 Bit 3 G0ID3 R/W-0 Bit 2 G0ID2 Bit1 G0ID1 Bit 0 G0ID0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 3 Bit 2 Bit1 Bit 0 G0ID[7:0]: Group0 ID [7:0] REG0x1D: Group1 ID Bit 7 G1ID7 R/W-0 Bit 7-0 Bit 6 G1ID6 R/W-0 Bit 5 G1ID5 R/W-0 Bit 4 G1ID4 G1ID3 R/W-0 G1ID2 G1ID1 G1ID0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 3 Bit 2 Bit1 Bit 0 G1ID[7:0]: Group1 ID [7:0] REG0x1E: Group2 ID Bit 7 G2ID7 R/W-0 Bit 7-
REG0x22: WAKE CONTROL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r REGWAKE r r r r r R R-1 WT-0 R-0 R-0 R-0 R-0 R-0 R-0 Bit 7 Bit 6 Bit 5-0 Reserved: Maintain as ‘0b1’ REGWAKE: Register Triggered Wake-up Signal 1: To wake DKL 1908_V.1 up. Bit is automatically cleared to ‘0’ by hardware.
REG0x24: TX STATUS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 TXRETRY3 TXRETRY2 TXRETRY1 TXRETRY0 r r TXLERR TXNS R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Bit1 Bit 0 Bit 7-4 Bit 3-1 Bit 1 Bit 0 TXRETRY[3:0]: TXFIFO Retry Times Maximum number of retries of the most recent TXFIFO transmission.
REG0x2C: PIPE2 ADDRESS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 P2ADDR7 P2ADDR6 P2ADDR5 P2ADDR4 P2ADDR3 P2ADDR2 P2ADDR1 P2ADDR0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 2 Bit1 Bit 0 Bit 7-0 P2ADDR[7:0]: Pipe2 address[7:0] REG0x2D: PIPE3 ADDRESS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 P3ADDR7 P3ADDR6 P3ADDR5 P3ADDR4 P3ADDR3 P3ADDR2 P3ADDR1 P3ADDR0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 2 Bit1 Bit 0 Bit 7-0 P3ADDR[7:0]: Pipe3 address[7:
REG0x30: RX MAC STATUS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r r RXFFOVFL RXCRCERR GroupID3 GroupID2 GroupID1 GroupID0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 Bit 7-6 Bit 5 Bit 4 Bit 3 Reserved: Maintain as ‘0b00’ RXFFOVFL: RX FIFO Overflow 0: (default) Not overflow 1: Overflow RXCRCERR: RX CRC Error 0: (default) RX CRC correct 1: RX CRC error GroupID3: 1: Group ID 3 matched 0: Group ID 3 not matched Bit 2 GroupID2: 1: Group ID 2 matched 0: Group ID 2 not matched Bit 1 GroupI
REG0x31: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r r r r RXIF r WAKEIF TXNIF R-0 R-0 R-0 R-0 RC-0 R-0 RC-0 RC-0 Bit 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: Maintain as ‘0b0000’ RXIF: RX FIFO Reception Interrupt (1) 0: (default) No RX FIFO reception interrupt occurred 1: An RX FIFO reception interrupt occurred Reserved: Maintain as ‘0b0’ WAKEIF: Wake-up Alert Interrupt (1) 0: (default) No wake-up alert interrupt occurred 1: A wake-up interrupt occurred TXNIF: TX FIFO Transmis
REG0x33: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r r r IRQPOL r r r r R-0 R-0 R-0 R/W-1 R-0 R-0 R-0 R-0 Bit 7-5 Bit 4 Bit 3-0 Reserved: Maintain as ‘0b000’ IRQPOL: Interrupt Edge Polarity 0: (default) Falling edge 1: Rising edge Reserved: Maintain as ‘0b0000’ REG0x34: SOFTWARE RESET Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r r r r RSTTRX RSTPWR RSTBB RSTMAC R-0 R-0 R-0 R-0 WT-0 WT-0 WT-0 WT-0 Bit 7-4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: Maint
REG0x35: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 SLPACK WAKECNT6 WAKECNT5 WAKECNT4 WAKECNT3 WAKECNT2 WAKECNT1 WAKECNT0 WT-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 7 Bit 6-0 SLPACK: Sleep Acknowledgement Place the DKL 1908_V.1 to Power Saving Mode. Bit is automatically cleared to ‘0’ by hardware. WAKECNT[6:0]: System Clock Recovery Time WAKECNT is a 15-bit value.
REG0x38 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0 r r r r CONT_TX BBMODE2 BBMODE 1 BBMODE 0 R -1 R-0 R-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 Bit 7-3 Bit 2-0 Reserved: Maintain as ‘0b00000’ BBMODE [2:0]: Turbo Mode Select 000: 125kbps DSSS-OQPSK 001: 1Mbps MSK 010: 250kbps DSSS-OQPSK (default) 011: 2Mbps MSK 100~111 : Undefined Specification Operation frequency:2408MHz~2475MHz Maximum power: 6.94dBm(EIRP) Statement 1.
Revision History Revision Date 0.0 2018/05/08 Description of Change Initial preliminary version. DS-2472-01
Contact UBEC: Headquarters Address: 6F-1, No. 192, Dongguang Rd., Hsinchu, 300 Taiwan Tel: +886-3-5729898 Fax:+886-3-5718599 Website: http://www.ubec.com.tw Sales Services FAE Services Tel: +886-3-5729898 Fax:+886-3-5718599 E-mail: sales@ubec.com.tw Tel: +886-3-5729898 Fax: +886-3-5718599 E-mail: fae@ubec.com.
FCC Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
OEM Statement a. The module manufacturer must show how compliance can be demonstrated only for specific host or hosts b. The module manufacturer must limit the applicable operating conditions in which t transmitter will be used, and c. The module manufacturer must disclose that only the module grantee can make the te evaluation that the module is compliant in the host.
