2.4GHz Module DKL 1613_V.1 User Manual Single Chip 2.4GHz Module http://www.panchip.
.4GHz Module FEATURES Low Power 16mA TX at 0dBm output power 15mA RX at 1Mbps air data rate 2uA in power down Low Cost BOM Few external components Four Capacitors, One crystal oscillator High Performance Excellent Receiver sensitivity -88dBm@1Mbps -93dBm@250Kbps Programmable Output Power Up to 13dBm TV and STB remote controls Wireless Mouse and keyboard Toys and wireless audio Wireless gamepads Active RFID Smart home automation APPLICATIONS http://www.panchip.
2.4GHz Module GENERAL DESCRIPTION The XN297L is a single chip 2.4GHz transceiver, designed for operation in the worldwide ISM frequency band at 2.400~2.483GHz. The XN297L integrates radio frequency (RF) transmitter and receiver, frequency synthesizer, crystal oscillator, baseband GFSK modem, and other function blocks. The XN297L supports multiple networks and communication with ACK. TX power, frequency channel, and data rate can be set by SPI.
2.4GHz Module 1 Electrical C Characteristics haracteristics Table1 XN297L Electrical Characteristics Symbol Condition at VCC = 3V±5%, T=25℃ Sleep Standby I Standby III Standby Ⅱ TX at -35dBm output power TX at -20dBm output power TX at 0dBm output power TX at 2dBm output power TX at 8dBm output power TX at 13dBm output power Min Parameter Typ 2 30 650 780 Max Unit uA uA uA uA 9 mA 9.5 mA 16 19 30 66 mA mA mA mA RX at 1Mbps 15.
2.4GHz Module 20dB Bandwidth for Modulated Carrier at 250Kbps 500 KHz 0 dBm -87 dBm -93 dBm 10 dBc 1 dBc -18 dBc -23 dBc -28 dBc -32 dBc -35 dBc 2 dBc -8 dBc -18 dBc -24 dBc -28 dBc -32 dBc -35 dBc Receiver Maximum received signal at <0.1% BER Sensitivity (0.1%BER) @1Mbps Sensitivity (0.
2.4GHz Module VSS+0. V 3 * Note: In the channels, such as 2416 and 2432 MHz, integer times of 16MHz Input low level voltage VSS crystal, receiver sensitivity degrades about 2dB; and modulation quality of the emission signal (EVM) falls by 10%. * Note: In 250Kbps mode, payload length should not be more than 16 bytes, because of frequency drift in open-loop transmitting mode.
2.4GHz Module 5 Operational Modes This chapter describes XN297L’s all kinds of working modes, and is used to control the chip into the working mode method. XN297L’s state machine is controlled by chip internal registers configuration values and external signal pin. 5.1 State D Diagram iagram Table 4 shows six kinds of work modes, which gives the corresponding mode of control registers and FIFO registers.
2.4GHz Module mode, the MCU can be sent via SPI configuration commands and CE pin into the other five states. Figure3 State Diagram 5.3 IRQ PIN When the status register TX_DS RX_DR or MAX_RT is 1, reporting and the corresponding interrupt enable bit is 0, IRQ pins interrupts trigger. The MCU writes 1 to the corresponding interrupt source, clear the interrupt. IRQ pins interrupt trigger can be blocked or enabled, report by setting the interrupt enable bit is 1, ban IRQ pins interrupt triggered.
2.4GHz Module 6 DATA FIFO Figure 4 FIFO Block Diagram The XN297L contains TX FIFO and RX FIFO. It is sent via SPI read/write command. It writes TX FIFO in TX mode by W_TX_PAYLOAD and W_TX_NO_ACK instructions. If MAX_RT interruption, data will be cleared in the TX FIFO. It reads PAYLOAD in RX FIFO in receiving mode by R_RX_PAYLOAD, and it reads the length of the PAYLOAD by R_RX_PL_WID instruction. FIFO_STATUS register indicates FIFO states. http://www.panchip.
2.4GHz Module 7 SPI CONTROL The XN297L is controlled by SPI port for read and write registers, and command. The XN297L is a slave terminal, SPI transfer rate depends on the MCU interface speed, and the maximum data transfer rate is 8 Mbps. SPI interface is a standard SPI interface are shown in table 5, you can use the general I/O for MCU simulation SPI interface. CSN pin to 0, SPI interface instructions to be performed. From 1 to 0 a CSN pin changes execute one instruction.
2.4GHz Module W_TX_PAYLOAD 1010 0000 1 to 32/64 FLUSH_TX 1110 0001 0 FLUSH_RX 1110 0010 0 REUSE_TX_PL 1110 0011 0 0101 0000 1 ACTIVATE DEACTIVE R_RX_PL_WID 0110 0000 0 W_ACK_PAYLOAD 1010 1PPP 1 to 32/64 W_TX_PAYLOAD_NO ACK 1011 0000 1 to 32/64 CE_FSPI_ON 1111 1101 1 FIFO after it is read. Used in RX mode. Write TX-payload. A write operation starts at byte 0. Used in TX payload.
2.4GHz Module CE_FSPI_OFF 1111 1100 1 0101 0011 1 1111 1111 0 RST_FSPI_HOLD RST_FSPI_RELS NOP SPI command CE internal logic 0, use the command followed by the data 0x00 With the command followed by data 0x5A, makes the XN297L into reset and maintain With the command followed by data 0xA5, release the XN297 reset and start to work normally No Operation. The R_REGISTER and W_REGISTER commands can operate on single or multi-byte registers.
2.4GHz Module Figure 7 SPI NOP Timing Diagram 8C Control ontrol Registers You can configure and control XN297L by accessing the register map through the SPI by using read and write commands.
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2.4GHz Module MAX_RT 4 0 R/W RX_P_NO 3:1 111 R TX_FULL 0 0 R PLOS_CNT 7:4 0 R ARC_CNT 3:0 0 R ANADATA7 7 0 R ANADATA6 6 0 R ANADATA5 5 0 R ANADATA4 4 0 R ANADATA3 3 0 R ANADATA2 2 0 R ANADATA1 1 0 R ANADATA0 0 0 R 0A RX_ADDR_P0 39:0 0xE7E7E 7E7E7 R/W 0B RX_ADDR_P1 39:0 0xC2C2C 2C2C2 R/W 08 09* OBSERVE_TX DATAOUT Maximum number of TX retransmits interrupt write 1 to clear bit.
2.4GHz Module 0C RX_ADDR_P2 7:0 0xC3 R/W 0D RX_ADDR_P3 7:0 0xC4 R/W 0E RX_ADDR_P4 7:0 0xC5 R/W 0F RX_ADDR_P5 7:0 0xC6 R/W 10 TX_ADDR 39:0 0xE7E7E 7E7E7 R/W 11 RX_PW_P0 Reserved 7 0 R/W RX_PW_P0 6:0 0000000 R/W Reserved 7 0 R/W RX_PW_P1 6:0 0000000 R/W Reserved 7 0 R/W RX_PW_P2 6:0 0000000 R/W 12 13 RX_PW_P1 RX_PW_P2 Receive address data pipe 2 bytes maximum length. Only LSB.
2.4GHz Module 14 15 16 17* RX_PW_P3 Reserved 7 0 R/W RX_PW_P3 6:0 0000000 R/W Reserved 7 0 R/W RX_PW_P4 6:0 0000000 R/W Reserved 7 0 R/W RX_PW_P5 6:0 0000000 R/W FIFO_STATUS N/A 7 0 R TX_REUSE 6 0 R TX_FULL 5 0 R TX_EMPTY 4 1 R N/A N/A 3 2 0 0 R R RX_FULL 1 0 R RX_PW_P4 RX_PW_P5 The data length of data pipe 3’s RX payload.
2.4GHz Module RX_EMPTY 0 1 R N/A TX_PLD 255:0 X W N/A RX_PLD 255:0 X R 19* DEMOD_CAL 7:0 CHIP 7 0 R/W CARR 6:5 00 R/W GAUS_CAL 4:1 0111 R/W 1A* Scramble_en 0 1 R/W RF_CAL2 47:0 N/A 47:46 01 R/W BW_500K 45 0 R/W 0: Available locations in RX FIFO. RX FIFO empty flag. 1: RX FIFO empty. 0: Data in RX FIFO. Written by separate SPI command TX data payload register 2-32 bytes or 164 bytes FIFO.
2.4GHz Module GC_500K 44 1 R/W IRQ_inv_sel 43 0 R/W CLKOUT_Z_sel 42 0 R/W CE_L_sel 41 0 R/W MISO_Z_sel 40 0 R/W IRQ_Z_sel 39 0 R/W PA_ramp_sel 38:37 01 R/W OSC_IC 36 1 R/W CLK_SEL 35:34 10 R/W EN_STBII_RX2T X 33 1 R/W 1: Wide bandwidth The gain of filter 0：Low gain 1：High gain If the output of IRQ(EN_PA)is inverse. 1：The output is inverse 0：The output isn’t inverse If the pin of CLKOUT is output in high resistance. 1：CLKOUT PIN is output in high resistance.
2.4GHz Module BPF_CTRL_BW 32 0 R/W BPF_CTRL_GAIN 31 1 R/W VCOBUF_IC 30:29 01 R/W VCO_CT 28:27 01 R/W CAL_VREF_SEL 26 1 R/W SPI_CAL_EN 25 0 R/W PREAMP_CTM 24:22 011 R/W DA_LPF_BW 21 1 R/W RX_CTM 20:19 01 R/W RCCAL_EN 18 1 R/W 1: Enable 0: Disenable Choose the bandwidth of 1dB receiving intermediate-frequency filter. 1: ×1 0: ×0.85 Choose the gain of receiving intermediate-frequency filter. 1: 5dB 0: 19dB Choose the driving MIXH current.
2.4GHz Module EN_VCO_CAL 17 1 R/W PRE_BC 16:14 100 R/W VCO_CODE_IN 1B 13:10 1000 R/W RCCAL_IN 9:4 010100 R/W CPSEL 3:2 01 R/W DATAOUT_SEL 1 0 R/W RSSI_SEL 0 1 R/W DEM_CAL2 23:0 PIN 23:21 000 R/W 0: Disable The bit to enable VCO’s autocorrenction 1: Enable 0: Disable Choose the prescaler’s direct current 000: ×1 001&010: ×1.5 100&011: ×2 101&110: ×2.
2.4GHz Module EN_RX 20 0 R/W DELAY1 19 0 R/W DELAY0 18 0 R/W TH1 17 1 R/W PTH 16:13 0110 R/W SYNC_SEL 12 1 R/W DECOD_INV 11 1 R/W GAIN1 10:7 1110 R/W GAIN2 6:1 000101 R/W both limit I and Q If both the receiving channel and PLL are open at the same time 1: Open at the same time 0: Open at the different time If the PLL’s open loop is enabled, the enabling of PLL’s open loop state can test the transmitting of carrier drift 1: PLL open loop enables.
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2.4GHz Module The length of time in 1Mbps mode: RX_ACK_TIME×32，the unit is us The length of time in 250kbps mode: RX_ACK_TIME×128，the unit is us 9 Packet Format D Description escription 9.1 Packet FFormat ormat for N Normal ormal Burst Table 7 Packet Format for Normal Burst Preamble (3 byte) Address (3~5 byte) Payload (1~32/64 byte) CRC (0/2 byte) It can choose Address and Payload part to scramble, according to scrambler configuration bits. 9.
2.4GHz Module 11 Package S Size ize Figure 9 QFN20L 0303 Package Size http://www.panchip.com Copyright ©2015 Panchip Microelectronics, Ltd.
2.4GHz Module Specification Operation frequency:2402MHz~2465MHz Maximum power: 6.27dBm(EIRP) Statement 1. The device complies with RF specifications when the device used at 0mm form your body. 2. This product is a category 1 receiver device. 3. The operating temperature of the EUT can’t exceed 55℃ and shouldn’t be lower than -20℃. 4. This product can be used across EU member states. Hereby, DA KAI INDUSTRIES LIMITED.
2.4GHz Module configuration bits. FCC Statement This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
2.4GHz Module OEM Statement The module manufacturer must show how compliance can be demonstrated only for specific host or hosts a. b. The module manufacturer must limit the applicable operating conditions in which t transmitter will be used, and c. The module manufacturer must disclose that only the module grantee can make the te evaluation that the module is compliant in the host.
