MZ-3500 SERVICE MANUAL CODE: OOZMZ 3500SM/E PERSONAL COMPUTER MODEL Z-350 CONTENTS 1. Specifications 2. Software (Memory) Configuration 3. CPU and memory 4. CRT display 5. MFD interface 6. R232C interface 7. Printer interface 8. Other interface 9. Power circuit description 10. Keyboard controller circuit discription 11. Self check functions 12. IPL flow chart 13. Circuit diagram & P.W.
M 7 3500 1. SPECIFICATIONS 1-1. Specification of the main unit (Model 35XX) Outline 1) 2) 3) 4) High speed processing using multi-CPL' Built in mini floppy disk Built in printer interface and RS232C Aerial interface Connection of up to two video displa, mitt (separate graphic display or overlaid display possible on two individual color monitor units) 5) Permits the use of standard CP/M Model 3530 incluse a single double-side, double density mini floppy disk and 64 KB RAM.
MZ3500 1-2. MZ-1K01 (Keyboard) specification Outline MZ1K02 U.S. keyboard (ASCII) MZ1K04 German keyboard MZ1K03: U.K. keyboard (ISO). MZ1K05: French keyboard Keyboard controller 80C49 or 8749 CMOSIC 4049x2,4514 LSI, 1C Sculpture key Keys (98) Mechanical contact key, with life of 10,000,000 operations.
MZ3500 Expansion unit Screw (1) 1-4. MZ-IR03 Outline Optional board used graphic display functions with the Model-3500 series CPU. It includes 32KB of RAM. It is inserted through the slot on the front panel of the PU. The MZ-1U02 expansion box is not required. GDC LSI Graphic controller vinrn HAM Specifications ~~~~~ Graphic functions (Color must be specified for each dot.
MZ3500 1-6. MZ-1R06 Outline Optional board for memory expantion of the MZ-3500 sries CPU. with this option the main memory (RAM) can be expanded up to a maximum of 256 KB. This option plug into the expantion box in slot 1 or 3.
MZ3500 1-7. MZ-1D07 Outline High resolution MZ 3500 series 12 green monitor Video tube Type Non glare green Size 12", 90" deflection Display capacity 640 horizontal dots, 400 vertical lines Vertical 47 8 Hz Weight 7.
MZ3500 1-8.
MZ3500 2. SOFTWARE (MEMORY) CONFIGURATION Memory will be operated under four states of SDO ~ SD3, depending on the hardware and software configurations. In the paragraphs to follow, description will be made for those four states. 2-1. SDO (INITIALIZE STATE) SDO can only exist immediately after power on, and the system executes IPL under this condition and that the system thus loaded will automatically assign memory area for SD1, SD2. and SD3.
M 7. 3500 Operational description (1) Upon reset after power on, the main CPU loads the contents of the initial program loader (IPL) into RAM starting at address 4000H, during which time reset is applied to the sub-CPU. (2) The main CPU then terminates resetting the sub CPU and starts the sub-CPU. At the same time, the ROM IPL is assigned to the sub-CPU. (3) The main CPU then send the memory allocation (state) to SD1, and starts to load DOS from the system floppy disk.
MZ3500 ROM-IPL 1. An 8KB ROM (2764 or mask ROM equivalent) is used 2. 3. 4. 5. Mam CPU logical address (during IPL operation) Logical address of the sub-CPU for the ROM-IPL. When the system reset signal turns from low to high state after power on, the main CPU starts to operate At this stage, the ROM-IPL is addressed.
MZ3500 Operational description (1) As soon as the sub-CPU is started, it initializes the I/O port and waits for program transfer (IOCS) from the main CPU. This IOCS (Input Output Control System) is the program resident at address 4000H-5FFFH. (2) As the main CPU loads the information from sector "1" of track "0" of the floppy disk, it loads the IOCS and bootstrap routine to the sub-CPU. (3) The bootstrap program is loaded next. (4) The bootstrap program determines rnemory allocation.
MZ3500 2-4. SD3 (RAM based BASIC) SD3 is active when "SHARP BASIC" is ececuted via RAM. "SHARP BASIC" is loaded in RAM from the floppy disk.
3. CPU AND MEMORY 3-1. Block diagram 1) Relation between MMR (Main Memory Mapper) and main memory. I RECEI VFR , RAM I (II'TION 1 4- RAN VI ' 64KBV2) °l 1 OPTION 1 . || I '7220 i JK» 2K* J (, , A P M , C {) R MPXR VIIIK1 RAM 32KB V 1 HI O RAM 32KB It Ml DM1 I MO*J OK II K U MO* 400 kl Mil I 1 ION V I D H ) RAM 32KH L si v i (.
MZ3500 3-2. Main CPU and I/O port r^ IX M A I N Connector I PC 2 |~^T 1 A2 A3 "" ~s j^ A4 —££-1 A6 M C P A v~\ P r (jtA. v f^-r-^r-.—r Y 1 ~~> \J> -•> r DL iZ \J I Obr J This paragraph discusses main CPU I/O Port select and addressing. The address output from the main CPU is decoded in the 74LS138 to create the select signal. Table below describes address map and signal functions.
MZ3500 3-3. Sub CPU and I/O port SUB AS6 5 ASS 2 AS4 i Y6 CPU Y4 4G 4_ AST J s07 ~9 S06 _JQ J SOS .Jl SO4 ^ . 012 S03 ,. D15 S 2 HEC3 -C* *. ^ r CKP 1 . CSP 2 . Shown at the left is the circuit used by the CPU to select the I/O ports The out put address from the sub CPU is decoded by the 74LS138to create the select signal. Shown below is the address map and select signals. ......
MZ3500 3-4. Memory mapper (MMR) SP6102R-001 1) Block diagram Memory mapping logic ADDRESS BUS AO . i. is.
MZ3500 2) Memory mapper (MMR) SP6102R-001 signal description Polarity Signal Name 1 ST 2 DO IN IN/OUT 9 D7 10 A15 A13 13 A1 Bidirectional main CPU data bus. (Data bus 0 ~ 7) Main CPU address bus. IN 12 Main CPU DRAM output buffer (LS244) switching strap. Used in the memory mapping logic of the MMR for address output for the DRAM, ROM, and shared RAM. IN (Address bus 13 ~ 15) Main CPU address bus. Used in the I/O port select logic of the MMR to assign device number.
M 7, 3500 Polarity Pin No. IN/OUT Function Signal Name Main CPU 128KB dynamic RAM output buffer (LS244) output enable signal. 32 RF1B OUT 33 RF2B OUT 34 WATB OUT (RAM buffer 1) Signal identical to R F 1 B For option RAM (RAM buffer 2) Wait signal to the mam CPU (One wait cycle 15 applied during the memory fetch cycle of the main CPU.
MX 3500 Polarity IN/OUT Pin No Function Signal Name System reset signal. 57 SYSR IN Used to reset I/O port in the MMR. (System Reset) 58 FD3 IN 59 COAB IN Input from the sytem assignment dip switch. "See the dip switch description, provided separately. Shared RAM select signal. Address of the shared RAM is *F800-#FFFF for the main CPU (Common RAM Address) Select signal for 8KB area allocated to slot 1.
M 7.3500 MAIN CPU I/O PORT IN MEMORY MAPPER ADDKKSS A7 A6 A5|A4|A3|A2|Al|AO H E X UHUS 01 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 KI) FE FF 1 O r\i IT SKQB DO D7 SKI S Dl MS] DO 1)7 D6 D5 D4 D2 Dl DO D4 D3 D2 Dl DO D7 D6 D5 1)4 D3 D2 Dl DO D7 D6 MSO SRQ Bus request from the mam CPU to the sob-CPU 1 1 Sub-CPU reset signal Memory system define M<\3 Bank select signal to memory area of COOO-FFFF.
MZ3500 3-5. Memory (ROMIPL, RAMCOM, S-RAM) select circuit To main CPU 1) ROM-IPL select by the main CPU As ROM IPL turns to low level after power on address bus buffers (LS244, LS367) and data bus buffer (LS245) are enabled. S of the data selector 1C (LS157) is set to a low level to enable input 1A-4A. The 3Y and 2Y outputs of the LS157 then go low so that CE and OE of the ROM-IPL are from main CPU. The contents of the IPL-ROM are then read by the main CPU.
4. CRT DISPLAY 4-1. Specification Ust of high resolution CRT 3KB (characit>-s! Display memory Character display 96KB. max (graphic i Screen structure Use of medium resolution (,RT Option 80 chrs x 25 lines.
Table 1 Summary of video display specification Medium resolution CRT (640 x 200 dots mode) High resolution CRT (640 x 400 dots mode) ^""~-\^ Characters Function ^^\^^ Elements Character s t r u c t u r e Color monitor Green monitor Type of monitor Graphics (option) B/W ASCII Color ASCII 8x8 8 x 20 8x 20 8x10 8x10 5x14 5x14 5x7 (Characters x ines) 40 x 25 mode 80 x 20 40 x 25 640 x 400 80 x 25 80x20 640 x 200 40 x 25 40 x 20 40 x 20 80 x 20 640 x 200 40 x 25 40 x 20 By chara
M7 3500 1) Character display 1.1. Screen structure CRT used Character Medium resolution CRT (640 x 200 dot) fH = 15 7KHz fV = 60Hz High resolution CRT (640 x 400 dot) fH = 20 9KHz ( N e w ) f V = 47 3Hz W Whne 80 x 25 lines 80 x 25 lines - ASCIL 40 x 25 lines 40 x 20 lines Dip switch in the mam unit is used to select assignment of Three basic colors high resolution/medium resolution CRT. Display mode must be chosen by programming. 4) Attribute 1-2.
MZ 3500 6) Screen overlay and displaying on two CRT's As there are two video output channels independent it will be pos screens sible to display two independent screens on separate video display unit Overlay is possible on either Data Address Hex 50 AS AS AS 3 2 1 0 0 0 0 AS DS 2 DS 1 DS 0 1 0 1 1 ;p i 51 0 0 0 1 1 1 52 0 0 1 1 0 1 1 53 0 0 1 1 1 1 54 0 1 0 of Internal S gnat name of CSP Function ECH1 Choice of outputting the character screen on CRT1 0 No 1 Ye
MZ3500 7) ASCII CG Uses an 8KB MROM contains two patterns' 640 x 400 dots ( 8 x 1 6 dots) and 640 x 200 dots ( 8 x 8 dots) #OFFF 8 x 8 d o t pattern (2K byte) For Model 3200 series With 8 x 8 dot format two kinds of patterns coexist Refer to ROM address and data ! x 8 dot pattern (2K byte) #0000 Without lower-case, code on separate information letter descenders #1 FFF Model 3500 8 x 16 dot pattern (4K byte) With lower-case, letter (h i j) descenders #1 000 D7| Address and pattern in picture elemen
MZ3500 2) 20 line display mode 2) 20 line display mode 8 20 \\NS\\\\Mi ASCII With line HL On 18th raster VL Line to the right of element e VL does not join a In the case of graphic symbol display, VL is overlaid to the pattern Without line 10 20 Graphic symbol j I Graphic symbol 9) Cursor Sharp of the cursor: Same as seen in Model 3200 Reverse and blink) 4-2. Video RAM 1) Structure of VRAM GDC1 (for character) 10) Light pen input Incorporates the light pen input connector and its interface.
M 7 3500 2) Read/write from Z 80 to VRAM (1) Timing period for display and V-RAM Read/write. //><-' Range wh°r? GDC can draw. Fly back period H • SYNCJ BLNK- (2) Timing that the Z-80 can read/write VRAM The Z-80 can read/write VRAM when GDC FIFO buffer is either empty or Full, and can be accessed by refreshing during the display period. Number of characters that can be read/write within one raster in any mode.
MZ3500 4) Graphic V R A M memory (MZIR03) • Block Diagram R ASA ^ RAS • A14 • A15 RASB~ RAS • A14 • AlS ... RASC =• RAS • A14 • A15 0000 ~ 3 F F F 4000-7FFF 8000 ~ BFFF 2. Display mode A14 and A15 are not valid and RASA, RASB, RASC are selected together. By the DBIN signal from GDC-2. 08/16 signal is generated by CSP-2. The signal of 08/16 select, after P-5 conversion for RAMA, RAMB output signal then output to VB by serial signal, or sprit the signal to VB and VR. (08/16 select: 08 for 200 rasters.
M Z 3500 (2) 640 x 400 dots display mode B/W: 1 frame Color: 1 frame Option I (48Kbyte) 16 bits structure #4000 # 3 KKK 16K 16K *0000 ( Option II Color can be designated for sach character. i #3FFF #0000 BFFF B/W: 3 frames Color: 1 frame (96K byte) 16 bits s t r u c t u r e #8000 #3FFF 16K #4000 #0000 16K #0000 16bit 16bit 16bit 16bit 5) Synchronize signal timing (1) For 640 x 200 dots display mode X : Y- 1 :2 fH = 15.
MZ3500 (2) 640 x 400 bits display mode fH = 20.92 kHz fV = 47.3 Hz X : Y : 1: 1 GDC-1 (80 digits) Character display (40 digits) 8 bits 16 bits Dot clock (OD) (19 66MHz) (9 83 MHz) 19.66MHz (50.86ns) 9.83MHz (101 92ns) 2XCCLK (4.9152MHz) (2.4575MHz) 4.9152MHz (203.45ns) 24575MHz (406 9ns) - - Horizontal display time HFP GDC-2 graphic) 32 55^s 80 Chr. /40 Chr. 4.88fjs 4^is HS *~ «- - (tREF=0.6ms) 5 Chr. (tREF = 1.23ms) 6 5ys HBP Vertical display time 19.16ms VFP 0.527ms VP 0.
M-3500 CH48 - I 08/16 - 0 For 40 digit display 1 : For 80 digit display There is a 40/80 digit switching signal I/O port in the gate array of CSP1 and CSP2, but, the I/O signal called CH48 is provided apart from the I/O port. I/O port inside CSP1 and CSP2.
MZ3500 4/6. Master slice LSI (CSP-1) SP6102C 002 signal description Priority Signal Name 1 HSYi IN Horizontal synchronizing signal from the GDC1 Also, it becomes the refresh timing signal in the dynamic RAM mode. 2 NABC IN Input from the UPD7220 GDC1. When the GDC1 is in the character display mode, the attribute, blinking timing and line counter ciear signals are multiplexed. 3 CSR IN Input from the GDC1 which is the cursor display input when the GDC1 is in the character display mode.
MZ3500 CSP-1 Block Diagram ASO 1 1 AS1 AS2 1 4 ,. .. o MkRO (bO) (51) Jl J, „ o > J * DSO ' DS1 n x — H I)S2 — to — fO t— (52) 'S3) 1 1 1 ro CO (54) '55,50) 1 I ^. ,r»T , • 5fi . II I I c n n r- Cn <7> ] ~ | X O C X 0 " m O m ? -_ i ^ 0 = 5 ° o re — 3 " fr HSYI K \ 400 1 NABC j 1^ SL1 Line counter/ Line signal generator > RA400 — 1 25 /20 —1 FYD2 BLNK B-VL __ 0/1.. DSP2 ^ .« ". +, i, ..._. . .
MZ3500 46. LSI (CSP-2) SP6012C-003 Signal Description Polarity IN/OUT Signal Name 1 HSY2 IN Horizontal synchronizing signal from GDC2 which also becomes the refresh tirniny . i j r . s ' i in the dynamic RAM mode. 2 BLK2 IN Erase signal input from the GDC2 which is supplied 4T the following times: 1. Horizotal flyback period. 2. Vertical flyback period. 3. Period from the execution of the SYNC SET command to -be execution of the DISP S T A R T command. 4. Line drawing period.
M/3 r >00 Priority Signal Name 36 M32 IN 37 FS OUT Graphic DRAM address multiplexer signal (High order 8 bits I ADS ADI 5] /low 3'der S hi" |ADO A D 7 ] select signal ) 38 DSP2 OUT Display timing signal (In the CSP 2, the signal BLINK from GDC2 is delayed by 2 collor intervals to create this signal ) 39 CAS 2 OUT Graphic D RAM CAS (COLUMN ADDRESS SELECT) signal (Line address selection) 40 Vcc IN Clock input 32MHz, 200 raster + 5V supply CSP 2 Block Diagram S-RAM & CG control signal ge
M 7.3500 4-7. GDC (Graphic display controller) (UPD7220) signal description Polarity Signal Name 1 2XCCLK IN 2 DBIN OUT Memory contro signal supp'ied to the image memory from the GDC, which causes the image memory output data to be sent on the data bus. 3 HSYNC-REF OUT Memory contro' signal sent to the image memory from the GDC, which is the horizontal synchronizing signal.
M Z 3500 Polar, ty Pin No IN/OUT Function Signal Name 35-37 AD13ILCO)AD15ILC2) IN/OUT Provides the following functions based on the operational mode of the GDC (graphic display mode, character display mode 0, character display mode 1). 1. In the graphic display mode and character display mode 0: Bidirectional address/data bus 2. In the character display mode 1 : Line counter output in connected to the character generator ROM or graphic RAM address.
M " 4 8 CG Address Select Circuit When 200 rasters on ASCII in use (only the high order 8 bytes of 16 bytes are set to low level I ASCII C.G.
MZ 3500 4-9. VSYNC From (8255 PB7) CH48 0 40 Digit 1 80 Digu SRES ( F r o m MMR) 40 digit. 16bu/word 80 digit, 8bit/word Master is GDC 40 digit, Sbit'word Master is GDC 1 80 digit, 16bit/word Master is GDC-2 [Circuit description] When more than two UPD7220 GDC's are to be operated in parallel, one must be assigned to the master and the other to the slave in order to mantain synchronous display timing. The master and the slave are determined according to the table below.
MZ3500 4-10. Character VRAM select circuit Lov*/ when 0 300^07FF The signal BLNK is used to address the ASCII RAM within address area of 0000-07FF in transferring the display data from the VRAM to the CG. CS 6 1 1 6( 2 K * 8 ) ASCB V-RAM 2114(!Kx4) First half of attribute *0000 -07PF *0000 -03FF 2114(1K*4) Latter half of attribute #0400 -07FF #0000 -07FF BL'SC BLNK Erase signal TTJ H-SYNC Period that the GDC is enabled to read/write and draw graphic data.
MZ3500 4-12. Read/write from the Z-80 to V-RAM Read/write of the Model 3500 V-RAM is done via the UPD7220GDC. There are two methods used to read/write data. The method (1) is used for the model 3500. (1) Read/write via the 16 byte FIFO. (2) Read/write of V-RAM in the DMA mode without intervention of the FIFO. (Outline of the read/write data via the FIFO; NO YES Set GDC command code Method used to give a command to the GDC. YES Set parameter for the command YES Set parameter for the command.
MZ3500 (Subroutine lo send command and parameter to the GDC via the F I F O ) HL reg — First address of the command code oarametpr B. reg — Q'ty of data. C reg - 60H (graphic GDC), 70H (character GDC) > FIFO Empty? ; COMMAND —• GDC ; Return if parameter not sent. f F I F O Empty? ; PARAMETER — GDC ; Return when all parameters were sent.
M23500 [Explanation] C-COMMAND CODE ) To A p_ PARAMETER ' Display dot, specify the display address of the VRAM and the dot address. Set the command code of the SET mode (set mode plus CLEAR, REPLACE, and COMPLEMENT modes using "WRITE", and specify to start with "VECTE". Dot address is structured on the screen in the following manner. Address 0001 dAD= 0 1 2 3 1 5 6 7 [Dot display program example-1] LD LD INC LD INC LD INC LD INC LD INC LD LD LD LD CALL LD LD LD CALL LD LD LD CALL HL .
M 7. 3500 2) Straight line drawing 00000 0001 0027 0028 0050 VRAM 16 bit structure Example to draw a straight line from (X, Y) = (3, 1) to (X, Y) = (635, 1). Coordinates must be changed to absolute addresses. (3, 1) - absolute address = 0028H Dot address = 2H Displacement between two points when the line draw direction is OA (to the right): X = 635-3 = 632 (=278H), Y=0 Whereas.
M Z 3500 5. MFD INTERFACE 1) Floppy disk nomenclature 5-1. Outline Floppy disk is a disk which is made of a mylar sheet whose surface is coated with magnetic particles and set on the device to write and read data on the surface of the disk It will be necessary to know operating pnciple of the floppy disk unit and operational description, including recording method and format. 5-2. Floppy disk As various recording methods and formats are used for floppy disk (F.D.
Example 2: CE330S (light passing through the notch is sensed and decoded as write protect) (Double side, Double density) Write enabled Write protected Front side Front side -r- nhibit notch Light is interrupted by the label o 0 O 0 Two types of write protection are used and attention must bepaid to the presience of the label because it may cause a wrong result if the label is used improperly.
MZ3500 times the data density of the MFM mode (The unneceb sary clock pulse is eliminated using this method ) (Condition) Clock is written only when there is no data o MFM method (double density) The MFM method writes data on the basis of the condi tion metntioned below, and it yields a data density two 0 Input data £ 0 £ 0 1 0 •'•> 0 1 1 1 0 1 0^0 n n n n n 7 / nnn n(O n n nnn n ' VnVn n nV [ci |D (ci |u ici ,i> ci (0 ;i> (c) \ /\ /\ X"V /\ / Write data C C (C) I) (C) t \ Data that foll
M 7 3500 Shown below is an enlarged view of data format sequence W r i t i n g starts as soon as the index hole comes through the index detect hole 1 Track Sector 02 Sector 01 DATA <[ DATA Firnl ^p IU II) DA I A t INDEX \M Start point Hatched portion is a recording gap 51 ID TT HH SS DL CRC CRC AM DATA AM DATA Data ID section CRC check code CRC CRC Data section CRC check code Size of data section ' Data address mark (or delete address mark) (00) H — 128 bytes (01) H — 256 bytes N
MZ3500 5-3.
M 2 3500 FDC (UPD765) UPD765 block diagram UPD765 pin configuration (top view) R L S t IQ »• 1 RDO » 2 39 WRO »• 3 38 K3LCT/DIR CSO > 4 *O FLTR/STEP AOO DBOo-« > » 5 6 37 36 DB1CX » 7 DB2O4 K DB304 8 ».
MZ3500 UPD765 signal description Function Pin No. Signal name I/O 40 Vcc - +5V 20 GND - 0V 19 0 I Single phase, TTL level clock 1 RESET 1 Set the FDC into an idle state, and all drive unit interface outputs, except PSO, 1 , and WDATA (don't care), are set to low level In addition, INT and DRW outputs are set to low level DB goes into an input state.
MZ350C P,n No Signal name I/O 32. 31 PSO. 1 O 23 RDATA 22 WINDOW Function Signal used to either advance or delay the write data in writi ng under the MFM mode, to obtain tirrung adjustment for reading. The WDATA signal is controlled as shown in the table be ow FM MFM PSO PS1 0 0 0 1 - LATE 225~250ns 1 0 - EARLY 225~250ns 1 1 - - Not changed Not changed 1 Read data from the drive unit consists of clock bits and data bits.
M 7.3 500 5-7. Precompensate Circuit Set the counter to 200ms. (Actually, slightly longer than 200ms.) K K I T E DATA (Fig. 2) PSO PS1 FM MFM Value of LSI 63 0 0 Not changed Not changed 1101 0 1 - LATE(125»is) 1100 1 1 0 - EARLY(125ja) 1110 1 - - - Media is present. (Table!) Media is not present. 5-9. Controls during read, write, seek, and recalibrate Above operations are all controlled via the FDC.
MZ 3500 In the case of the MFM method, need to trace cycle fluctuation is further increased, as a peak shift is apt to occur because there are three write data cycles. (Peak shift). Data read cycles fluctuate as the flux change point is moved forwards or backwards. Write pulse Polarity inversion Read waveform Advanced peak shift Regenerated pulse *— Delayed peak shift H Cb) {VFO circuit): Variable frequency oscillator Polarity inversion f~J Polarity inversion Write pulse J Read waveform j I 6.
MZ3500 2) VFO circuit configuration READ DATA" —» h, Phase detector k. Filter amplifier ^ Window Data separator SEPARATED DATA SEPARATED CLOCK The VFO circuit has the following capabilities. (1) Two modes: MFM and FM. (2) The VFO circuit operation is suspended during the SYNC field located before the ID field and data field. (3) After suspention, the VFO circuit will synchronize with the read data (timing is affected by a speed change in the FDD).
MFM Mode AlMHz _rLTLJT_r B)QA) 1_ Nomal STD Eary n Delay © J~L
MZ3500 FM mode timing chart A 4M B(QA) C(QB) D(QC) WINDOW E F L Normal O P F L Advanced Q O P L K Delayed Q O P Does not trace ± I j 1 1 [ 1 1 1 1 1 1 1 1
I * ~ * oinQle density ~^~^~~~^~~~ 0 ~—~^——^— LJQUOI6 density *" U. o / 1 / 2 c o ,— ^ c UJ o o ~ Q s .. 5 o o o 0 O O 0 0 \ S3 0 \ I o \ \ / o o U, U- U, U. a. s 5 cD - / / * \ u. u. 1/5 U lO U? a) U 10 w / Q U o tQ ^_t OS UJ H . c o ^ (O u 0 02- 1£ CD" L-i O o *#- ca Csl h O O cc m H 8« Q. J2 (J I 2 £ W w T— 1 U,
M/asoo Track 0, sector 1 information (SBACIS) (Fig AA 7 L' 1 ( 1) 00 02 00 00 04 i i 1 00 ! i I / M HF i c | 1 '. OO1 i ' 1 1 48 1 ! i 1 i 041 1 Jv IM 1 No, of sectors m media 1 48 i ' Start address > 1 02 I ! * I , . ; —I 'T '< Oo! 01 i > 1 r u U S I IM' SJ"L tor 01 ' i , N I SUB IOCS BOOT r ; 02 10 01 01 01 10 i No of Track SIDE Sector sectors N j i FF , No of END sectors f 0 . Single density, other than front side, track 0. 1 .
M7 350? o Map information 0 track 10 sector 0 track 9 sector // x 1 / / / / 2 1 7H 129 &0H 130 I 71! 131 FFH 151 FFH 3 1 FFH 22 \ J FFH 4CH FFH / 23 24 FFH 128 blocks are controlled by one sector. OOH-7FH 80H: End of link FEH: Links to next map, and the starting block number. 152 FFH 153 75 76 77 \ \ 126 \ 127 1 iy / 1 ^ \128 FFH 7 EH FFH FEH FFH FFH Indicates the byte position • from the top of directory.
MZ3500 o Block number allocation The program and data areas are located after Track 2 1 block = 2K bytes (8 sector) (Double side) (Single sided) Block No track Block No Front track Reverse Front 2 BO Bl B2 B3 2 BO Bl 3 B4 B5 B6 B7 3 B2 B3 I I 38 B144 6145 B146 B147 38 B72 B73 39 B148 B149 B150 B151 39 B74 B75 2Kx 152 = 304K 2KX 76=152K Each track is blocked in the following manner: 2 sec tor ' 4 6 1 sector 3 5 1 block 1 block 13 15 sector 14 16 sector o Track
MZS500 6. R232C INTERFACE 6-1. General specification Input/output format RS-232C bit serial input/output No of channels 1 channel Code used JIS 7-channel/JIS 8 channel Baud rate Transmission system Half-duplex Synchronization method Start-stop Communication control procedure Non-procedure Data format Stop bif 1/1.5/2, with or without even or odd parity. LSI used 8251 AC or8253C-5 (Programmable interval Timer) 110 to 9600 bits/sec 6-2.
MZ3500 6-3. Block diagram of the interface Control signal Peripheral 6-4. System switch functions ON OFF SW5 Causes an error when the ER signal is low or open during data output. ER signal is disabled. SW6 Always high when power is on to the main unit. The CD signal is set high while data output, but would not be set high when the echo-back function is selected for the host computer. SW7 Causes on error when the PO signal is high during data output. Polarity is inverted. 6-5.
MZ3500 2) Data output control SKNU Command instruction (KTS,RXEN,TXEN) 8251 AC "L"->KTS »- 8251 AC Set counter (200ms) ERROR 101 Stop Output data to 8251AC The 8251 send data when CTS goes low. The 8251 AC would not output, unlessv CTS goes low. Therefore, the state of \ CTS will be checked when the buffer I .becomes empty.
M/3SOO 3) Data input control RCV Command nstruction 8251 AC ( E R .
MZ 3500 6-6. 8253 Controls Baud rate of this interface will be determined by the clock output of the 8253. The 8251 is configured such that its baud rate is 1/16 of the input clock and has the following relation between the 8253 output clock and the baud rate: 1 1 0 .t 300 1760Hz 4800 600 9600 1 200 2400 4800 9600 8253 input frequency: 2457.6kHz 8253 Mode set: Mode 3(rec'angle waveform rate generator) 8253 Parameter 8253 Output frequency Baud rale 1 3 9 6.
M Z 3500 DO~D7 Data Bas RXD Receive Data (IN/OUT) WR Write (IN) RD Read (IN) C/D Control/Data (IN/OUT) CS Chip Select (IN) DSR Data Set Ready (IN) DTR Data Terminal Ready (OUT) RTS Request to Send (OUT) TXC UO O Data bus AA buffer v-v Counter •« t 1 KO
M 2 3500 8251 CLK DTK IN IN OUT CTS 1 N DSK 8251 chip address[0001/xxxx] IN Uix OUT) 2.45MHz clock DATA SET READY READY DATA TERMINAL READY TRANSMITTER DATA CS PO (MPER SUT), ER CD RD TRANSMITTER CLOCK RECEIVE DATA OUT 0 of 8253 SD RECEIVER READY To 3iil>CPU of RECEIVE CLOCK 8253 OUT CLEAR TO SEND OUT Rl S OUT TXD TXRDY N.C. TXE N.C. IN TXC IN RXD RXRDY OUT IN "RXC SYN/BD N.C.
M 7. 3500 7. PRINTER INTERFACE 7-1. Printer interfacing circuit AS 4 • AS 5 AS6 • AS 7 AR SO3 Chip CS 8255 I )fi i >de r rs.
7-3. General description of the parallel interface The 8255 is used for the LSI to control the parallel interface. The 8255 can be set in the following mode. /PORT A: MODE 0 I P O R T B : MODE 1 C: Output 74.
M / 3500 7-6.
M 2 3500 8. OTHER INTERFACES 8-1. Clock circuit 1) Schematic T; 10 * Ii2 u HDH l«"-.r " 1 2) Clock timing READ mode Cn(CO~C2) STB HOLD .
MZ3500 3) ^PD1990AC Block diagram OK O Command specification Data Shift DOUT C1 CO Command 0 0 0 Register hold Holds 40-bit S/R 1Hz Not possible Data retention 0 0 1 Register shift Data input/output [LSB] Output of LSB Possible Shifts in synchronization with the clock 0 1 0 Time set Data of the 40-bit S/R is preset to the time counter. ILSB] Output Not possible Time read Data in the time counter is read to the 40-bit S/R.
8-2.
M/3500 83.
M 7 3500 8 4 System SW1 (DIP SW) (User operative through the cabinet bottom) No Signal name 1 SW1 Function Description Position Polarity ON L OFF H ON L OFF H ON L High resolution CRT (MZ1D02.
MZ3500 DIPSW(B) DIP S W ( A ) • 1 2 3 4 1 2 OFF OFF OFF ON ON ON Switches are set in this manner before shipment of machines this us the single-sided minifloppy disk drive. ON OFF OFF ON ON ON Switches are set in this manner before shipment of machines that use the double-sided minifloppy disk drive.
MZ3500 9, POWER CIRCUIT DESCRIPTION 1. BLOCK DIAGRAM (Block diagram) A. +5V and +12V supplies 1. Functions a. Supply voltage is first rectified in the rectifier circuit and sent out to the switching regulator via the overcurrent detector provided in the overcurrent protect circuit. b. Next, the voltage is converted to the +5/+12V output in the switching regulator and sent out to the noise • Nfilter. c.
M 7,3500 Switching regulator + 5V or Q5 (Switching regulator and constant voltage control circuit) « VR is the+5V or+12V adjusting VR. • D3 is provided to discharge current from Cj after power off.
M23500 c. Power switching circuit As the signal from the oscillator is amplified through Q7 to Q6 to change current to the transformer T2. it causes voltage to appear on the base of Q5 (one of components is cut by D1), so that the transistor Q5 begins to perform switching operation in synchronization with the oscillation frequency. As Q2 is switched, current is supplied to the emitter side of the transistor Q5, which produces smoothed voltage through the capacitor C1 and the coil L2.
MZ3500 10. MZ1K01 KEYBOARD CONTROLLER CIRCUIT DESCRIPTION 10-1. Specification of keyboard control 11) One-step commands uior 1) Input Buffer Capacity: 64 bytes • Key-in data is written to the input buffer first, and is supplied to the CPU, byte by byte. • When an overflow is detected, the overflow code is affired to the key-in data already sent, before being sent to the CPU.
MZS500 10-2. Key search timing Single key entry Bounding / Key n STROBE n n n n n n n 15ms 1 Strobe *~5.5ms M 5ms -» RETURN cvcle n n n n n n n DATA OUT Two key entry /A" Key 1 Key 2 n STROBE n n n -5.5ms—M—•6.5ms —M—5ms —W n RET n n n n n n n n 15ms M 15ms DATA (1) OUT DATA (2) OUT 10-3.
MZ 3500 • Command flag: "0" when succeedeing 8 bits are a key data. "1" when it is a command or a graphic control data. • Data: Positive logic (negative logic on the cable) • Parity: Odd parity up to 27 bit from the correction flag. 2) Interfacing signals CPU level • D(K): Output data from the keyboard. Positive logic • ST(K): D(K) strobe signal. Also use for Active H interrupt to the CPU. • ACK(C): Acknowledge signal form the Active H CPU. Also use for the data transfer interrupt disable signal.
M?3500 10-4.
MZ3500 10-5.
Type of error 0) MDF 1/F error ON 1sec. OFF 4sec. (2.1 SDO read/write error (3) SDO bank alternation error ® AD2 bank alternation error © AD3 bank alternation error CD ROM sum-check error © Option RAM read/write error (Indicated even when the option RAM is not in use) /s~. Option RAM bank alternation error NOTES: 1. The MFD I/F will not be tested, if there is no MFD I/F connected or when the diskette was not inserted in the slot of the drive unit No.2. 2.
MZ 3500 Sector 1, Track 0 information 10 0 AAH 1CH TRACK SIDE SECTOR N NO. OF SECTOR i t i 1 I i i 15 TRACK SIDE SECTOR SECTOR N \ Represent the system media Load address Drive unit specification Start address Test program 50 20 NO. OF SECTOR NO. OF SECTOR NO. OF SECTOR SUB-IOCS -H the end Single dencity (Track 0) No of data transfers = INT [IOCS capacity/1 K] + 1 • Sub-IOCS can be divided into eight blocks.
2) VRAM check Proceed to test for ASCI! and atnbute VRAM [Display] During test penode, display shows under following. (1) Display reviced "U" for entire screen Irom top side. (2) Display blinking "I'' with under! ne for entire screen. (3) Display entire screen by space. Test end 1. Normal VR OK 2. Abnormal VR ER 1) Memory test Sub-IOCS RAM (4000H-5FFF) Shared RAM (2003H-23FFH) Shared RAM (2440H-27FFH) Above are tested.
MZ3500 ( ( Check No. 4 ) Check No. 5 ) Border in black Kff "H" in red "H" in green "H" in white !• "H" in whi ( ( Check No. 7 Check No. 6 ) ( Check No. 8 ) Backroung in red ) Back ground in black Back ground in green } } } } "H" in blue L "H" in blue "H" in red L "H" in green [• "H" in white 4) Speaker test Performance of the speaker and the volume control are tested. Listen carefully to detect any abnormal sound or mulfunction. Adjust the volume control to a suitable listening level.
MZ3500 8) ROM-IPL MAIN CPU CHECKER FLOW CHART 1/2 ( MAIN CUP CHECKERSTAHT A ] c Write "66" »nd~Of~ on Tracki 0.20.
MZ3500 MAIN CPU CHECKER FLOW CHART M? Option HAM read/write check Change bank of the option RAM Error on display C - 100 - HALT
M 7*500 SUB CPU CHECKER FLOW CHART 1/3 ( SUB CPU CHECKER START ^ I CRTmt*f face t«t SeiGDCto«00
MZ3500 SUB CPU CHECKER FLOW CHART 3/3 SUB CPU CHECKER FLOW CHART 2/3 Sei th» timer to 23 hourt. 59 minuiei. 58 **corxii Oc *mb«r 3 III Printer int M»c* tt»t 11-3. Keyboard unit test functions 1) Keyboard controller ROM test (1) After power on in a normal condition, it starts to carry out the ROM self-test. If the alpha/symbol (LOCK) LED were to turn on, it indicates a failure in KBC. If not, KBC is satisfactory.
MZ3500 12. IPL FLOW CHART 12-1. MAIN CPU IPL FLOW CHART 1/2 ( MAIN CPU (PL START ^ J Transfer the program m 1000E-J0400E-. B Jump to 400EH Contents of parameter sector ROM/RAM test S**ect memory location SUM IPL START 1. Kind of MFD Single-side double-dene ity or double side double dencity. 2. Track and sector where IOCS is stored, Loadi vj '. and Truch Number of sectors Note' The sub loader is contained m the leading sector.
MZ3500 MAIN CPU IPL FLOW CHART 2/2 I Check if IOCS program area is smaller than RAM volume. NO I/O SYSTEM LOAD ERROR transfer YES LOAD IOCS SEEK& READ •SEEK, READ ERROR c HALT CPU STOP ERROR \^ Transfer the IOCS program to shared RAM 8000H~-»-F800H~ - BOOT: Program used to start the system. C LOAD BOOT Position of boostrap program on the media: Sector 2 thru 5 of Track 0. LOAD BOOT SSEK& READ ERROR ret rys ^ — 1 C JUMP BOOT ADDRESS ( ^\ ) - 104 - BOOTERROR on disp.
MZ-3500 122. SUB CPU IPL FLOW CHART ( POWER ON SUB CPU IPL A J T,m«, 1 In t,alize8255 A Mode 0.8 Mode 1.
Mz-roo 13-18.
M 7. - 3500 74L593 /^PDI 99OC \l \-' 111 I ! IK H I I ! l\ m M M r^n R m O\ liiiiilv II FY OL Ll HO! I r KOI INI bA (...iml.r 1 Lu LLI LLTLu ID TLTLzJ t-L KO; NL Vc(_ NX LU L^J HI L±J 111 LlJ LJ <. 2 l~l LO S 1 )t |)|N (_S B 74 LS 367 ("- Oil I.
M/-3500 64K /"PD8251 I.2C 1 inC 2 KM.C 1 M>C 1 25 ^ R V T ( ""'C t DIM R 23 DKT^ IX.Q 7 22 J D S K I-7C 8 21 Q 2(i "~K I K mC '-^C TJ^C tit i'-C i*C '*C D»i 310 20 Ihu 28 27 10 18 12 17 RP>C 13 16 R X R 1 » C 14 15 21 U 3V 3^i< uC 1 IIINC 2 T c 3 22 D^T) IMC 4 21 iwC H2C 20 6 It D<^ "k\sC 1 DM we i D^ \^C i, I>lC 7 18 D(.IK2 8 17 5 7 It. H.M, urc 1 U 1> DPvs A\&C 2 11 DI>OI i ^iC H \i ^^^C 1. D \ < \M'C }' DM uiC 10 3 V.
MZ-35OO PARTS GUIDE LI
MZ-3500 li Exteriors PARTS CODE NO 1 CCABC1007ACZZ 2 31 4| !> 6 7 8 9 10 11 12 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 G F T A F 1 0 0 1 A C Z Z HBDGB3004GESA T L A B Z 1 0 0 3 A C Z Z T L A B Z 1 0 0 8 A C Z Z QCNCW1008AC01 Q PWB F 1 0 0 5 A C Z Z V H P G L 9 P R 2//1 GCABA1003ACZZ G F T A U 1 0 0 5 A C Z Z PSPAG1004ACZZ T L A B Z 1 0 1 7 A C Z Z X B P S F 3 0 P 0 6 K O O OUNT-1018ACZZ DUNT-1035ACZZ GCABB1004ACZZ GCOVH1 00 1ACZZ LANGT1003ACZZ LANGT1010ACZZ LCHSM1008ACZZ
oe IE--or ooss-zw
MZ-3500 [2] PWB & Fixing angles NO 1 2 3J 4 5 6 7 8 9 11 12 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 PARTS CODE JKNBM0004PAZZ LANGS1006AC2Z L A N G K 1 0 0 7 A C Z Z OCNCW1 0 0 8 A C 0 2 Q S W - K 1 0 0 7 ACZ Z R V R-A 5 4 5 2 QCZ Z VSP0080P-608N XBPSD30P06KOO DUNTK1082ACZZ DUNTK 083ACZZ DUNTK 0 6 4 ACZ Z DUNTK 060ACZZ GFTAR 003ACZZ G F T A R 0 0 4 AC Z Z LHLDZ 001ACZZ Q C N W — 0 0 3 ACZ Z QCNW- 0 0 4 A C Z Z QCNW- 0 4 7 A C Z Z Q C N W - 0 4 4 ACZ Z X B B S C 2 6 P 0 4 0 0 0 XBBS
M2-3500 13.
MZ-3500 [41 Others NO.
MZ-3500 ,5! CPU PWB NO PARTS CODE 69 70 71 72 VH M 7 4 L S 3 6 7 - 1 VH M 7 4 L S 3 7 3 — 1 VH M 7 4 L S 7 4/- 1 VH M 7 4 L S 7 5/— 1 74 75 76 77 78 79 80 81 82 83 84 85 86 87 V H VH VH VH VH VH VH VH VH VH VH VH VH VH M 7 4 L S 9 3/1 S N 7 4 0 4 N/- 1 S N 7 4 0 6 N/1 S N 7 4 1 5 7 N - 1 SN75188N-1 S N 7 5 1 8 9 A —1 S P 6 1 0 2 C 0 0 2 SP6102C003 S P 6 1 0 2 R 0 0 1 T A 7 3 1 3 A P —1 T C 4 0 4 9 P/— 1 U P 0 1 9 9 0 A C C UPD7220D—1 UPD8255/-1 V H 276 4 / / A C 0 1 V H 2 7 6 4/ / A C 0 2 VH 276 4
MZ-3500 [6j Power supply unit NO.
M2-3500 J9, MZ1K02,1K03,1K04,1K05 (Key unit) 19 19 i <,
MZ-3500 [1Q! MZ1R03 (Graphic board) NO PRICE RANK PARTS CODE 1 DUNTK1025ACZZ 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 * A A A A A S P A K A 1 0 1 3 A C Z Z SPAKC1 0 7 8 A C Z Z X B P S D 4 0 P 0 6 0 0 0 T S E L F 0 0 0 3 P A Z Z LANGT 1 0 0 8 A C Z Z Q SOC Z 6 4 1 6 A C Z Z Q S O C Z 6 4 4 0 A C Z Z RC-C Z 1 0 0 0 Q C Z Z RC-SZ200 1HCZZ VCEAAU1CW107M VCEAAU1CW336M VCEAAU1EW107M VCKYPA1HB33 IK VCTYPA1NX104M VHERD5 6E5/-1 VH i M5 K 4 1 1 6 P-2 VHiM74LSOO
MZ-3500 Index PARTS CODE [C] C C A B C 1 007ACZZ [D] DUNT-1 0 1 8 A C Z Z DUNT-1 0 3 5 A C Z Z D U N T K 1 0 2 5ACZZ D U N T K 1 02 8 A C Z Z DUNTK 1 060ACZZ D U N T K 1 064 A C Z Z D U N T K 1 082ACZZ D U N T K 1 083 ACZZ DUNTK1085ACZZ [G] G C A B A 1 00 1 ACZZ G C A B A l 003ACZZ GCABB1002ACZZ GCABB1004ACZZ G C O V H 1 00 1ACZZ G F T A F 1 001ACZZ G F T A F 1 002ACZZ GFTAR1003ACZZ GFTAR1004ACZZ GFTAU1005ACZZ GLEGG1001ACZZ G L E G P O O 10UCZZ GLEGP1001CCZZ GSTN-100 1ACZZ [H] HBDG83004GESA n [J ] JKNBM00
MZ-3500 NO PARTS CODE S P A K A 0 04 A C Z Z 9- 109 S P A K A 0 09 A C Z Z 9- 110 S P A K A 0 1 3 ACZZ 10 2 S P A K A 0 1 6 A C Z Z 1 11- 2 SPAKA 045ACZZ 9- 111 S P A K A 1 27 A C Z Z 9 112 9 113 SPAKC 0 33ACZZ 9- 113 SPAKC1035ACZZ 9- 113 S P A K C 1 03 7ACZZ S P A K C 1 0 3 9ACZZ 9- 113 10- 3 S P A K C 1 07 8 A C Z Z 11- 3 SPAKC1 082ACZZ 9- 114 S P A K F 1 1 0 4 ACZZ SSAKH3002KCZZ 4- 13 IT] T i N S J 1009ACZZ 11- 4 T iN S M 1 0 1 7ACZZ 11 5 T L A B J 1 769CCZZ 9- 115 TLABZ1002ACZZ 9- 2 T L A B Z 1 003 A
MZ-3500 PARTS CODE VH i 4 1 6 4 - 1 5 0 - H // VH i 825 1 AC//-1 VH i 8253////-1 VHPGL3PR2//-1 VHPGL9PR2//-1 // VRO-RV2EYOO 0J VRD-RV2EY 1 0 1J VRD-RV2EY682 J V R O - S T 2 E Y 100 J H VRD-ST2EY 1 0 1J // // // V R D - S T 2 E Y 1 02 J // // // // // V R D - S T 2 E Y 1 03 J // // V R O - S T 2 E Y 1 04 J // V R O - S T 2 E Y 1 51 J VRD-ST2EY152 J // II V R D - S T 2 E Y 1 82 J VRD-ST2EY220 J // VRD-ST2EY222 J // ii H V R O - S T 2 E Y 2 72 J V R D - S T 2 E Y 3 3 1J // // // // // // // // VR
MZ-3500 PARTS CODE O A E 3 0 1 20524// // O A E 3 0 1 206 5 O// O A E 3 0 1 2 1 8 6 6// OAE30121921// // // // // O A E 3 0 1 2 1 9 4 7// O A E 3 0 1 29460// // // // O A E 3 0 143284// O A E 3 0 1 4 3 5 7 2// // O A E 3 0 1 59870// O A E 3 0 164409// // O A E 3 0 1 6526 2// O A E 3 0 1 6 5 5 7 6// // O A E 3 0 1 67370// O A E 3 0 1 69653/7 // ;/ O A E 3 0 1 7 0008// // O A E 3 0 1 95258/7 OAE30200774// // O A E 3 0 2 13525// O A E 3 0 2 1 69 0 4// O A E 3 0 2 2 1 5 1 7// OAE30221520// O A E 3 02 2 1 546/
SHARP CORPORATION Industrial Instruments Group Reliability & Quality Control Department Yamatokoriyama, Nara 639-11, Japan 1983 January Printed in Japan s