LZ87010 User’s Guide (Advance) 1/15/03
This document is released as Beta-level documentation. SHARP reserves the right to change and amend this documentation as necessary to represent the final Production-level development of this device. Specifications are subject to change without notice. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty.
Table of Contents Preface What’s in This User’s Guide ................................................................................... xiii Chapter 1 – Introduction ..................................................................................... xiii Chapter 2 – System Clocking ............................................................................. xiii Chapter 3 – 8051-Compatible Core ................................................................... xiii Chapter 4 – Internal RAM............
Table of Contents LZ87010 Advance User’s Guide Chapter 1 – Introduction 1.1 Features ........................................................................................................... 1-1 1.2 Description ....................................................................................................... 1-2 1.3 Pin Diagram...................................................................................................... 1-3 1.4 Block Diagram .................................................
LZ87010 Advance User’s Guide Table of Contents Chapter 3 – 8051-Compatible Core 3.1 Theory of Operation ......................................................................................... 3-1 3.2 Registers .......................................................................................................... 3-1 3.2.1 ACC (Accumulator) Register ..................................................................... 3-2 3.2.2 B Register................................................................
Table of Contents LZ87010 Advance User’s Guide Chapter 8 – Enhanced Timers 8.1 Enhanced Timer Signals .................................................................................. 8-3 8.2 Enhanced Timer Theory of Operation .............................................................. 8-3 8.2.1 Reading 16-bit Timer Registers................................................................. 8-3 8.2.2 Writing 16-bit Timer Registers ...................................................................
LZ87010 Advance User’s Guide Table of Contents Chapter 11 – External Memory 11.1 Theory of Operation ..................................................................................... 11-1 11.1.1 Writing to External Memory ................................................................... 11-1 11.1.2 Reading from External Memory............................................................. 11-1 11.2 Signals.................................................................................................
Table of Contents LZ87010 Advance User’s Guide Chapter 15 – I2C Interface 15.1 Theory of Operation ..................................................................................... 15-1 15.1.1 Setting I2C Clock Timing ....................................................................... 15-1 15.2 Interrupt Handling......................................................................................... 15-2 15.2.1 Slave Mode ...........................................................................
List of Figures Preface Figure 1. Multiplexer................................................................................................... xvii Figure 2. Register with Bit Field Named..................................................................... xvii Figure 3. Register with Multiple Bit Fields Named..................................................... xviii Figure 4. Register with Bit Field Numbered...............................................................
List of Figures LZ87010 Advance User’s Guide Chapter 10 – UARTs Figure 10-1. Receive Operation, Modes 1-3 ............................................................ 10-2 Figure 10-2. Receive Operation, Mode 0 ................................................................. 10-3 Figure 10-3. Transmit Operation, Modes 1 - 3 ......................................................... 10-4 Figure 10-4. Transmit Operation, Mode 0 ................................................................
List of Tables Preface Table 1. Register Name ..............................................................................................xvi Table 2. Register Bit Fields .........................................................................................xvi Chapter 1 – Introduction Table 1-1. Signal Descriptions, Listed Alphabetically................................................. 1-5 Table 1-2. Interrupt Sources and Vectors ................................................................
List of Tables LZ87010 Advance User’s Guide Chapter 6 – I/O Ports Table 6-1. I/O Port Signal Descriptions ...................................................................... 6-4 Table 6-2. PORT0, PORT1, PORT3, PORT5, PORT6, PORT7, PORT8 Registers .. 6-5 Table 6-3. General-Purpose I/O Register Bits............................................................ 6-5 Table 6-4. PORT2 and PORT9 Registers .................................................................. 6-6 Table 6-5.
LZ87010 Advance User’s Guide List of Tables Chapter 9 – Watchdog Timer Table 9-1. WDTCTL Register..................................................................................... 9-2 Table 9-2. WDTCTL Register Bits.............................................................................. 9-2 Table 9-3. WDTCNT Register .................................................................................... 9-3 Table 9-4. WDTCNT Register Bits .............................................................
List of Tables LZ87010 Advance User’s Guide Chapter 14 – Analog Outputs (DAC) Table 14-1. DAC Signals.......................................................................................... 14-4 Table 14-2. DACC Register...................................................................................... 14-4 Table 14-3. DACC Register Bits............................................................................... 14-4 Table 14-4. WGCTL0 and WGCTL1 Registers .........................................
Preface The SHARP LZ87010 is a high-performance 8-bit microcontroller. This User’s Guide is the principal technical reference for this device. This document assumes the reader is familiar with 8051 programming. For abridged versions of this User’s Guide, consult the LZ87010 Data Sheet and the single page Product Brief. For details, contact a SHARP representative or see the SHARP Microelectronics of the Americas website at http://www.sharpsma.com.
Preface LZ87010 Advance User’s Guide Chapter 8 – Enhanced Timers This Chapter describes Timers 2, 3, 4, and 5, which are enhanced 16-bit timers providing a total of four counters, four capture units, four PWM units, and eight compare units. Chapter 9 – Watchdog Timer This Chapter describes the LZ87010 Watchdog Timer (WDT). Chapter 10 – UARTS This Chapter describes the LZ87010 UARTs, UART 0 and UART 1. Both are 8051compatible, except that UART1 has a dedicated baud-rate generator.
LZ87010 Advance User’s Guide Preface Terms and Conventions Multiplexed Pins The LZ87010 is manufactured in an LQFP package with 100 pins. Some pins have only one function, but others support two functions. These multiplexed pins have both functions available simultaneously. Pin Names Package pins are named to indicate the signal(s) or functionality available at the pin. If the signal or function is active LOW, the name is prefixed with a lower-case ‘n’, such as nPSWR.
Preface LZ87010 Advance User’s Guide Register Tables All Registers are presented in tabular format. A primary table presents each register’s name, address, permissions, bit names and the register’s contents at reset. Subsequent tables, if present, detail the specific names and function(s) of all bits and bit fields in the register and explain any important variations that may exist. Reading and Writing An important detail to note is that all registers are not perfectly writable and readable.
LZ87010 Advance User’s Guide Preface Numeric Values Binary values are prefixed with 0b; for example, 0b00001000. Hexadecimal values are expressed with UPPERCASE letters and prefixed with 0x; for example, 0x0FBC. All numeric values not specifically identified with the above prefixes as either binary or hexadecimal are decimal values. Registers and bit fields with 0b0 in all bits are referred to as ‘cleared’ or as 0.
Preface LZ87010 Advance User’s Guide Figure 4 is similar to Figure 2 except that Figure 4 references multiple (different) BITFIELDS in the REGISTERNAME register. REGISTERNAME: [BITFIELDNAME, BITFIELDNAME] INPUT f() OUTPUT LZ87010-78 Figure 3. Register with Multiple Bit Fields Named Not all bit fields are named. If a bit field has no name, the Register is shown with numbers indicating the appropriate bit positions, with the least significant bit on the right, as in Figure 4.
Chapter 1 Introduction 1.
Introduction LZ87010 Advance User’s Guide • Interrupt Controller – 8 External Interrupt Pins – 13 Internal Interrupt Sources – 4 Software-Selectable Interrupt Priorities • Watchdog Timer • Flexible Internal Clocking Architecture • Low Power Modes: Active, Idle, Stop • 3.3 V (±10%) Power Supply • 100-Pin LQFP Package 1.2 Description The LZ87010 is a high-performance, feature-rich 8-bit microcontroller based on the 8051 microprocessor architecture.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P0_5/INT5 P0_6/INT6 P0_7/INT7 P6_0/CTIN4 P6_1 P6_2/CTCMP4A P6_3/CTCMP4B P6_4/CTIN5 P6_5 P6_6/CTCMP5A P6_7/CTCMP5B VDD P9_0 P9_1 P9_2 P9_3 P9_4 P9_5 P9_6 P9_7 P1_0/CTIN3 P1_1 P1_2/CTCAP3A P1_3/CTCAP3B P1_4/CTCMP3A P1_5/CTCMP3B P1_6/nPSWR P1_7/nPSEN VSS P5_0/XMD0 P5_1/XMD1 P5_2/XMD2 P5_3/XMD3 P5_4/XMD4 P5_5/XMD5 P5_6/XMD6 P5_7/XMD7 P2_0/XMA8 P2_1/XMA9 P2_2/XMA10 P2_3/XMA11 P2_4/XMA12 P2_5/XMA13 P2_6/XMA14 P2_7/XMA15 VDD RESET P
Introduction LZ87010 Advance User’s Guide 1.
LZ87010 Advance User’s Guide Introduction 1.5 Signal Descriptions Table 1-1. Signal Descriptions, Listed Alphabetically SIGNAL NAME SIGNAL TYPE* PIN NO. PIN TYPE FUNCTIONAL UNIT SHARED WITH ADVREF I 50 I ADC Analog input. Voltage Reference for Analog-toDigital Converter; sets upper limit of conversion range.
Introduction LZ87010 Advance User’s Guide Table 1-1. Signal Descriptions, Listed Alphabetically (Cont’d) SIGNAL NAME SIGNAL TYPE* PIN NO.
LZ87010 Advance User’s Guide Introduction Table 1-1. Signal Descriptions, Listed Alphabetically (Cont’d) SIGNAL NAME SIGNAL TYPE* PIN NO. PIN TYPE FUNCTIONAL UNIT SHARED WITH VDD_CORE PWR 67 PWR Power Core Power Supply. Normally connected only to a 4.7 µF tantalum bypass capacitor. VDDA PWR 47 PWR Power Analog Power, 3.3 V ± 10%.
Introduction LZ87010 Advance User’s Guide 1.6 Functional Description The broad range of features in the LZ87010 allows it to support complex applications, such as the one shown in Figure 1-3. 1.6.1 8051-Compatible Processor Core The LZ87010 processor core is compatible with the industry-standard 8051. The additional features of the LZ87010 have been mapped to unused addresses in the SFR (special function register) memory space.
LZ87010 Advance User’s Guide Introduction 1.6.2 Program Memory Program memory is a 64K × 8 Flash array. On Reset, execution begins at Flash memory address 0. Program memory can also be used for read/write data storage. This memory is shipped from the factory with all bytes set to 0xFF. Initial programming takes place under the control of either an external bulk programmer or the debug interface.
Introduction LZ87010 Advance User’s Guide 1.6.6 Interrupt Controller The interrupt controller arbitrates between 13 interrupt sources, each with its own execution vector. Each of these sources is assigned by software to one of four interrupt priority levels. Eight external interrupt signals (INT[7:0]) are supported, sharing pins with Port 0. INT[0] and INT[1] each have their own interrupt vector, while INT[7:2] share a single vector.
LZ87010 Advance User’s Guide Introduction 1.6.8 I/O Ports Nine 8-bit ports can be assigned to up to 72 of the LZ87010’s 100 pins. Seven of these ports provide general-purpose I/O functions on all pins. Two provide high-current outputs. Most I/O ports are dual-purpose and have both a dedicated function (such as TXD0, the Transmit Data output of UART 0) and a generalized I/O function (such as P3[1]). The read/write ports contain weak internal pull-up resistors with a nominal value of 90 kΩ.
Introduction LZ87010 Advance User’s Guide 1.6.13 Counter/Timer/PWM Six timers are provided: two standard 8051 timers (Timer 0 and Timer 1) and four enhanced timers (Timer 2 through Timer 5).
LZ87010 Advance User’s Guide Introduction The active CPU clock source and clock divisor are chosen under software control. See Figure 1-6. Three main clocks are derived from this divided clock: • CCLK, the core clock, which runs at the divided clock frequency. CCLK halts in both Idle and Stop modes. • SCLK, the State Machine clock, which runs at the same frequency as CCLK. Unlike CCLK, SCLK continues to run in Idle mode, halting only in Stop mode.
Introduction LZ87010 Advance User’s Guide 1.6.15 Reset The RESET pin, when asserted HIGH, drives the entire device to a known state. Shortly after RESET is released, execution proceeds from address 0 in the embedded Flash program memory. A watchdog timer, if enabled, will reset the chip after a period of inactivity. 1.6.16 Power and Ground The LZ87010 is typically operated from a single 3.3 V supply. The device uses 2.5 V for the core, provided by an on-chip voltage regulator.
LZ87010 Advance User’s Guide Introduction 1.7 Register Summary The registers of the LZ87010 are listed in Table 1-7. As in the 8051, registers with addresses ending in 0x0 or 0x8 are bit-addressable. Figure 1-7.
Introduction LZ87010 Advance User’s Guide Figure 1-7.
LZ87010 Advance User’s Guide Introduction Figure 1-7.
Introduction LZ87010 Advance User’s Guide 1.8 Instruction Set Summary The LZ87010 instruction set consists of the 8051 instruction set plus two new instructions: TRAP and MOVC @(DPTR++),A. The TRAP instruction causes the LZ87010 to enter debug mode under software control. Once in debug mode, single-stepping and other debugging features can be used. Debug mode can also be entered under hardware control through the debug interface. The MOVC @(DPTR++),A instruction allows code memory to be written.
LZ87010 Advance User’s Guide Introduction Table 1-3.
Introduction LZ87010 Advance User’s Guide Table 1-3.
LZ87010 Advance User’s Guide Introduction Table 1-3.
Introduction LZ87010 Advance User’s Guide Table 1-5.
LZ87010 Advance User’s Guide Introduction Table 1-6.
Introduction 1. 2. 3. 4. LZ87010 Advance User’s Guide #d is an 8-bit immediate; #dd is a 16-bit immediate. Bottom row gives bytes, cycles. In rightmost column, ‘n’ in ‘Rn’ ranges from 0x0-0x7 for opcodes ending in 0x8-0xF. Opcode 0xA5 is also used for the TRAP instruction (1 byte, 1 cycle). The DPS register controls which instruction is active.
Chapter 2 System Clocking 2.1 Theory of Operation System clocking in the LZ87010 is provided by two sets of clock inputs: high-frequency inputs XTAL1 and XTAL2, and low-frequency subclock inputs XTAL_SUB1 and XTAL_SUB2. These inputs can be used either with crystal oscillators or external clock generators, as shown in Figure 2-1. The high-frequency oscillator operation is guaranteed from 20 MHz to 40 MHz. The lowfrequency oscillator is optimized for 32.768 kHz.
System Clocking LZ87010 Advance User’s Guide 2.1.1 Internal Clocks Internal clocking is shown in Figure 2-2. The individual clock signals are described here. 2.1.1.1 HFCLK This is the output of the high-frequency oscillator on the XTAL1 and XTAL2 pins. It is used by the ADC and the system clock generator. HFCLK halts in Stop mode. 2.1.1.2 SUBCLK This is the output of the 32 kHz subclock oscillator on the XTAL_SUB1 and XTAL_SUB2 pins.
LZ87010 Advance User’s Guide EXTERNAL TO THE LZ87010 System Clocking INTERNAL TO THE LZ87010 XTAL_SUB1 SUB-CLOCK OSCILLATOR SUBCLK XTAL_SUB2 SCLK 1 CLOCK DIVIDER MUX nEN 0 SEL 3 1 STOP ENABLE CCLK DIV IDLE DIVIDEBY 2 PCLK CLKCFG.CLKDIV CLKCFG.CLKSEL nEN XTAL1 XTAL2 HIGHFREQUENCY OSCILLATOR HFCLK ADC CLOCK DIVIDER STOP IDLE 1 1 PCON.PD PCON.IDL ADCCLK DIV 3 CLKCFG.ADCDIV LZ87010-81 Figure 2-2.
System Clocking LZ87010 Advance User’s Guide 2.1.2 Power-Saving Modes During periods when full operation is not required, significant power savings can be achieved by deactivating portions of the LZ87010 using the PCON register. 2.1.2.1 Idle Mode When PCON.IDL is set to ‘1’ by software, the microcontroller enters Idle Mode. In this mode, the processor core is halted (by stopping CCLK), but the peripherals (including the timers) continue to operate.
LZ87010 Advance User’s Guide System Clocking 2.2 Signals Table 2-1 details the system clocking signals. Table 2-1. System Clock Signals SIGNAL NAME SIGNAL PIN PIN FUNCTIONAL TYPE NO. TYPE UNIT DESCRIPTION XTAL_SUB1 I 72 I/O Clock Subclock Crystal When a 32.768 kHz crystal is used, this pin connects to one of the crystal pins. When an external clock generator is used, this pin is the clock input. If the subclock is not needed, this pin should be tied to VDD.
System Clocking LZ87010 Advance User’s Guide 2.3 Registers 2.3.1 CLKCFG (Clock Configuration) Register The CLKCFG (Clock Configuration) register determines the active system clock, the current system clock divider, and the current ADC clock divider. Table 2-2. CLKCFG (Clock Configuration) Register BIT 7 6 5 4 3 2 1 0 FIELD CLKSEL /// CLKADC[2] CLKADC[1] CLKADC[0] CLKDIV[2] CLKDIV[1] CLKDIV[0] RESET 0 0 1 0 1 0 0 0 RW RW RW RW RW RW RW RW RW ADDR 0x94 Table 2-3.
LZ87010 Advance User’s Guide System Clocking 2.3.2 PCON (Power Control) Register The PCON (Power Control) register selects the current power-saving mode (one of: Active, Idle, and Stop), and implements a bit to double the baud rate of UART 0 (in Modes 1 - 3). It also contains two general-purpose read/write bits that can be used by software for any desired purpose. Table 2-6.
Chapter 3 8051-Compatible Core 3.1 Theory of Operation The LZ87010 has an 8051-compatible core that supports the full instruction set of the 8051 architecture. It supports all the 8051 Special Function Registers (SFRs, called simply ‘registers’ in this document), plus a large number of additional functions. The LZ87010 has a ‘machine cycle’ of only two clock cycles. That is, most instructions execute in two system clock (CCLK) cycles, compared with 12 cycles in the original 8051.
8051-Compatible Core LZ87010 Advance User’s Guide 3.2.1 ACC (Accumulator) Register The ACC (Accumulator) register provides an 8-bit value as one of the operands for many processor instructions. Table 3-2. ACC (Accumulator) Register BIT FIELD 7 6 5 4 3 2 1 0 ACC[7] ACC[6] ACC[5] ACC[4] ACC[3] ACC[2] ACC[1] ACC[0] RESET RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW ADDR 0xE0 3.2.
LZ87010 Advance User’s Guide 8051-Compatible Core 3.2.4 DPS (Data Pointer Select) Register The DPS (Data Pointer Select) register determines whether the DPL/DPH or DPL1/DPH1 register pairs are used as the 16-bit DPTR register. It also contains the bit that determines whether opcode 0xA5 is the TRAP or the ‘MOVC @(DPTR++),A’ (program memory write) instruction. Table 3-6.
8051-Compatible Core LZ87010 Advance User’s Guide 3.2.5 PSW (Program Status Word) Register The PSW (Program Status Word) register contains processor status information. Table 3-8. PSW Register BIT 7 6 5 4 3 2 1 0 FIELD CY AC F0 RS1 RS0 OV F1 P RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RO RW ADDR 0xD0 Table 3-9.
Chapter 4 Internal RAM The LZ87010 has two areas of on-chip Data RAM: 256 bytes of scratchpad RAM and 4,096 bytes of MOVX RAM. 4.1 Theory of Operation The LZ87010 has four distinct addressing spaces: 1. A 256-byte data address space containing scratchpad RAM at addresses 0x00-0xFF. 2. A 128-byte data address space containing memory-mapped registers (also called ‘special function registers’) at addresses 0x80-0xFF. This overlaps scratchpad RAM in the memory map.
Internal RAM LZ87010 Advance User’s Guide 4.1.2 MOVX RAM (4,096 Bytes) The 4,096 byte memory space is mapped to addresses 0x0000-0x0FFF and is accessed by the MOVX instruction, which allows 16-bit addresses. The upper 4 bits of the MOVX address are ignored. Any MOVX instruction will thus access the 4KB RAM. Like the 256byte memory, the 4,096 byte MOVX RAM is implemented in high-speed, single-cycleaccess memory.
Chapter 5 Internal Flash The LZ87010 has 64KB of internal Flash memory, mapped as program memory. At Reset, execution begins at address 0x0000 of this memory space. This memory supports zerowait-state execution at full processor speed. The Flash can be written under external control or through the control of on-chip software. Both Mass Erase of the entire Flash and Sector Erase of individual 512-byte sectors is supported.
Internal Flash LZ87010 Advance User’s Guide 5.1.2 Flash Timing Timing of individual Flash operations is controlled by the Flash controller. In normal (readonly) operation, Flash reads have no wait states. When writing is enabled, reads have two wait states. During programming and erasure, the Flash controller generates processor wait states to prevent access to the Flash while an operation is in progress.
LZ87010 Advance User’s Guide Internal Flash 5.2 Registers 5.2.1 FLASHCFG (Flash Configuration) Register The FLASHCFG register configures the operating mode of the Flash memory and determines whether the Info Array is visible or not. Table 5-2. FLASHCFG Register BIT FIELD 7 6 5 4 3 2 1 0 SECURE /// FMAP FMOD[4] FMOD[3] FMOD[2] FMOD[1] FMOD[0] RESET RW 0 0 0 0 0 0 0 1 RO RW RW RW RW RW RW RW ADDR 0x96 Table 5-3.
Internal Flash LZ87010 Advance User’s Guide 5.2.2 FLASHTB (Flash Timebase) Register The FLASHTB (Flash timebase) register calibrates the Flash controller relative to the system clock, so the time-sensitive Flash operations can take place accurately. Table 5-5. FLASHTB Register BIT FIELD 7 6 5 4 3 2 1 0 FTB[7] FTB[6] FTB[5] FTB[4] FTB[3] FTB[2] FTB[1] FTB[0] RESET RW 0 1 1 0 0 0 1 1 RW RW RW RW RW RW RW RW ADDR 0x97 Table 5-6.
Chapter 6 I/O Ports The LZ87010 has seven 8-bit general-purpose I/O ports and two 8-bit high-current output ports. These ports are read and written under software control. Most ports are bitaddressable, allowing individual bits to be set or cleared without disturbing the other bits in the port. Most of the general-purpose I/O pins are shared with other functions.
I/O Ports LZ87010 Advance User’s Guide 6.1 Theory of Operation From the point of view of the world outside the LZ87010, inputs and outputs are asynchronous, as no reference clock is provided. From the LZ87010’s point of view, reads and writes can take place at the rate of one every Peripheral Clock (PCLK) cycle. This is the same as the instruction rate. 6.1.1 General-Purpose I/O Ports The general-purpose I/O ports are Port 0, Port 1, Port 3, Port 5, Port 6, Port 7, and Port 8.
LZ87010 Advance User’s Guide I/O Ports 6.1.2 High-Current Output Ports The high-current output ports are Port 2 and Port 9. Port 2 is bit-addressable; Port 9 is not. These ports are driven continuously in both the HIGH and LOW output states. They can drive a minimum of 12 mA. Figure 6-2 shows an equivalent circuit for a high-current output pin. While the output pins are write-only, the PORT2 and PORT9 registers are read/write. Reading the register will return the last value written.
I/O Ports LZ87010 Advance User’s Guide 6.2 Signals Table 6-1. I/O Port Signal Descriptions SIGNAL SIGNAL NAME TYPE* PIN NO.
LZ87010 Advance User’s Guide I/O Ports 6.3 Registers 6.3.1 General-Purpose I/O Registers The general-purpose I/O registers sample external I/O pins when read by the processor and drive external I/O pins when written by the processor. These bits are set to ‘1’ on Reset (with the exception of PORT3[7:6], which are set to ‘0’) to set the pins HIGH, which is the state that allows the pins to function as inputs. The HIGH state also minimizes power consumption. The PORT0, PORT1, ...
I/O Ports LZ87010 Advance User’s Guide 6.3.2 High-Current Output Registers Writes to the high-current output registers cause the high-current output pins to change state to match the bits in the register. These bits default to ‘1’ on Reset, corresponding to a HIGH output level. Table 6-4. PORT2 and PORT9 Registers BIT 7 6 5 4 3 2 1 0 FIELD D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] RESET 1 1 1 1 1 1 1 1 RW RW RW RW RW RW RW RW RW PORT2: 0xA0 PORT9: 0xA9 ADDR Table 6-5.
Chapter 7 8051-Compatible Timers The LZ87010 includes standard 8051 counter/timers: Timer 0 and Timer 1. Both are 16-bit count-up timers that can be clocked internally by PCLK or externally through the CTIN0 pin (Timer 0) or CTIN1 pin (Timer 1). 7.1 Timer Theory of Operation The timers are controlled by two registers: TCON (timer control) and TMOD (timer mode). Timer data is stored in four registers: TH0 and TL0 for Timer 0 high and low bytes, respectively, and TH1 and TL1 for Timer 1.
8051-Compatible Timers LZ87010 Advance User’s Guide Each timer has a Timer Run bit that acts as a timer enable. The Timer Run bit is TCON.TR0 for Timer 0 and TCON.TR1 for Timer 1. The timer will not run unless the Timer Run bit is set. A second bit, the Gate bit (TMOD.GATE0 or TMOD.GATE1), determines whether the timer runs continuously or is gated by an external signal (INT[0] or INT[1]). If Gate is ‘0’ and Timer Run is ‘1’, the timer will run continuously.
LZ87010 Advance User’s Guide 8051-Compatible Timers 7.1.1.2 Mode 1 Mode 1 is a 16-bit free-running mode. All 16 bits of TH(x) and TL(x) are used for the count. With a 20 MHz PCLK, the counter will overflow every 3.2768 ms (305.18 Hz). See Figure 7-3. 16 n[15:0] TCLK(x) f(n) = n+1 CLK f[15:8] 8 TH(x) 8 TO INTERRUPT CONTROLLER OVF f[7:0] 8 TCON.TF(x) TL(x) 8 LZ87010-102 Figure 7-3.
8051-Compatible Timers LZ87010 Advance User’s Guide 7.1.1.3 Mode 2 Mode 2 is an 8-bit auto-reload mode. TL(x) is the 8-bit counter. TH(x) holds the reload value. Whenever TL(x) overflows to zero, it is reloaded with TH(x). See Figure 7-4. The auto-reload feature allows timers running Mode 2 to generate overflows at the rate of (256 - TH1) PCLK cycles if internal clocking is used (CTIN0 or CTIN1 replace PCLK if external clocking is used).
LZ87010 Advance User’s Guide EXTERNAL TO THE LZ87010 8051-Compatible Timers INTERNAL TO THE LZ87010 TIMER 0 TMOD.CT0 8 PCLK 0 n[7:0] TCLK0 CLK f(n) = n+1 TO INTERRUPT CONTROLLER OVF f[7:0] 1 CTIN0 8 TMOD.GATE0 TCON.TR0 TCON.TF0 TL0 8 INT0 8 TCON.TR1 n[7:0] PCLK f(n) = n+1 CLK TO INTERRUPT CONTROLLER OVF f[7:0] 8 TCON.TF1 TH0 8 TIMER 1 CLOCKING TMOD.CT1 PCLK 0 TCLK1 CTIN1 TO TIMER 1 1 TMOD.
8051-Compatible Timers LZ87010 Advance User’s Guide 7.2 Timer 0 and Timer 1 Signals Table 7-1. Timer 0 and Timer 1 I/O NAME DIRECTION DESCRIPTION CTIN0 In External clock input, Timer 0 CTIN1 In External clock input, Timer 1 EXT0 In Clock enable/disable, Timer 0 EXT1 In Clock enable/disable, Timer1 7.3 Timer 0 and 1 Registers 7.3.1 TCON (Timer 0 and 1 Control) Register Table 7-2.
LZ87010 Advance User’s Guide 8051-Compatible Timers 7.3.2 TMOD (Timer 0 and 1 Mode) Registers Table 7-4. TMOD Register BIT FIELD 7 6 5 4 3 2 1 0 GATE1 CN1 M1[1] M1[0] GATE0 CT0 M0[1] M0[0] RESET RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW ADDR 0x89 Table 7-5. TMOD Register Bits BIT 7 NAME DESCRIPTION Timer 1 Gate Flag When this bit is ‘1’ Timer 1 runs only when the INT[1] pin is GATE1 HIGH. When this bit is ‘0’, Timer 1 runs continuously.
8051-Compatible Timers LZ87010 Advance User’s Guide 7.3.3 Timer Data Registers (TH0, TH1, TL0, TL1) Table 7-7.
Chapter 8 Enhanced Timers The LZ87010 has four enhanced 16-bit timer/counters: Timer 2, Timer 3, Timer 4, and Timer 5. These timers are not 8051-compatible. A top-level block diagram of these timers is given in Figure 8-1.
Enhanced Timers LZ87010 Advance User’s Guide TIMER 2 BLOCK PCLK XTAL_SUB TM3CMP1 CTIN2 CLOCK T2CLK DIVIDER CLOCK SELECT TIMER/COUNTER 16 BITS INTERRUPT CONTROL OVF, CMP, CAP TO INTERRUPT CONTROLLER TO CTCMP2A CTCAP2A INPUT CAPTURE (2) CTCAP2B COMPARE VALUE (2) PWM TO CTCMP2B TIMER 3 BLOCK PCLK XTAL_SUB CTIN3 CLOCK T3CLK DIVIDER CLOCK SELECT TIMER/COUNTER 16 BITS CTCAP3A INPUT CAPTURE (2) CTCAP3B INTERRUPT CONTROL OVF, CMP, CAP COMPARE VALUE (2) PWM TO INTERRUPT CONTROLLER TO CTCMP3A TO C
LZ87010 Advance User’s Guide Enhanced Timers 8.1 Enhanced Timer Signals Table 8-1. Timer 2 - Timer 5 I/O NAME CTIN2, CTIN3, CTIN4, CTIN5 CTCMP2A, CTCMP2B, CTCMP3A, CTCMP3B, CTCMP4A, CTCMP4B, CTCMP5A, CTCMP5B DIRECTION DESCRIPTION In External clock inputs for Timers 2 - 5 Out CTCAP2A, CTCAP2B, CTCAP3A, CTCAP3B In Compare outputs Capture inputs 8.2 Enhanced Timer Theory of Operation 8.2.
Enhanced Timers LZ87010 Advance User’s Guide MOV reg, timer_data_low MOV reg, timer_data_high 8 TMP TMP 8 8 T(x)CNTH T(x)CNTL T(x)CNTH HIGH-BYTE DATA IS MOVED TO A TEMPORARY REGISTER WHEN LOW BYTE IS READ T(x)CNTL HIGH-BYTE IS READ FROM TEMPORARY REGISTER LZ87010-69 Figure 8-2. Reading from Count and Capture Registers 8.2.2 Writing 16-bit Timer Registers Writes also have a mechanism to allow updating while the timer is running.
LZ87010 Advance User’s Guide Enhanced Timers 8.2.3 Timer Clocking Each timer has either three or four clock inputs, as shown in Figure 8-1. These always include PCLK (the peripheral clock, which is always half the core clock), SUBCLK (the 32.768 kHz subclock), and an external clock input. Each timer has its own dedicated clock input pin, CTIN2-CTIN5. Timers 2 and 4 also have the option of using the output of an adjacent timer’s compare unit output.
8-6 1/15/03 1 2 3 (See Note) CTIN(x) TM3CMP1 RESERVED TM5CMP1 RESERVED TIMER 2 TIMER 3 TIMER 4 TIMER 5 INPUT 2 MUX TIMER NOTE 0 PCLK XTAL_SUB 2 T(x)CON.CLK_SEL CLOCK SOURCE CLOCK DIVIDER 3 T(x)CON.DIV (TIMER 2 and TIMER 4) 128 (TIMER 3 and TIMER 5) 32,768 0b111 0b111 16-BIT COUNTER COMPARE, CAPTURE 16 OVF T(x)CNT[H:L] CLR TO COMPARE AND CAPTURE FUNCTIONS CLEAR ON COMPARE T(x)CON.CCL CLEAR COUNTER T(x)CON.
LZ87010 Advance User’s Guide EXTERNAL TO THE LZ87010 Enhanced Timers INTERNAL TO THE LZ87010 TIMER 2 or TIMER 3 COUNT T(x)CNTH T(x)CAP.IED(y) INTERRUPT ENABLE T(x)CNTL T(x)CAP.IIE(y) 2 8 8 1 n TO INTERRUPT CONTROLLER f(n) CTCAP(x)(y) CLK 8 8 PCLK 1 T(x)CAP(y)H T(x)CAP(y)L CAPTURED TIMER COUNT n T(x)STA.CAP(y)_ST CAPTURE STATUS f(n) 00 CAPTURE DISABLED 01 CAPTURE ON RISING EDGE 10 CAPTURE ON FALLING EDGE 11 CAPTURE ON BOTH EDGES LZ87010-98 Figure 8-5.
Enhanced Timers LZ87010 Advance User’s Guide 8.2.6 Compare All four enhanced timers have a dual compare function, where two 16-bit values can be stored and compared against the current timer value. When a match occurs, an external signal and an interrupt can be asserted. Both actions are optional and are independent of one another. The T(x)CMP(y).CMP0 and T(x)CMP(y).CMP1 bit fields determine the output polarity of the compare unit. This is the polarity of the output on a compare match.
LZ87010 Advance User’s Guide Enhanced Timers TO COUNTER UNIT (T(x)CNT) CLEAR ON COMPARE INTERNAL TO THE LZ87010 16-BIT COUNT EXTERNAL TO THE LZ87010 COMPARE 1 UNIT T(x)CMP.CMP1 T(x)CMP1H 2 16 n T(x)CMP1L 8 TCMPOE.TM(x)OE1 = 8 CTCMP(x)B PIN f(n) 16 INTERRUPT ENABLE T(x)CMP.CMP1_EN CLEAR COUNT ON COMPARE T(x)CMP.TC TO INTERRUPT CONTROLLER COMPARE STATUS T(x)STA.CMP1_ST COMPARE 0 UNIT T(x)CMP.PWM PWM MODE SELECT T(x)CMP.CMP0 T(x)CMP0H 2 TCMPOE.
Enhanced Timers LZ87010 Advance User’s Guide Table 8-3. Compare Function TIMER OUTPUT POLARITY SIGNAL REGISTERS STATUS BIT INTERRUPT ENABLE OUTPUT ENABLE CTCMP2A T2CMP.CMP0[1:0] T2CMP0H, T2CMP0L T2STA.CMP0_ST T2CMP.IOE0 TCMPOE[7] CTCMP2B T2CMP.CMP1[1:0] T2CMP1H, T2CMP1L T2STA.CMP1_ST T2CMP.IOE1 TCMPOE[6] CTCMP3A T3CMP.CMP0[1:0] T3CMP0H, T3CMP0L T3STA.CMP0_ST T3CMP.IOE0 TCMPOE[5] CTCMP3B T3CMP.CMP1[1:0] T3CMP1H, T3CMP1L T3STA.CMP1_ST T3CMP.IOE1 TCMPOE[4] CTCMP4A T4CMP.
LZ87010 Advance User’s Guide Enhanced Timers 8.2.7 PWM In PWM mode, a timer’s two compare units are used together to form an output oscillator with controllable frequency and duty cycle. Both compare units control the same pin, CTCMP(x)A. The lower-numbered compare unit is programmed to drive the signal to one state (LOW, for example) on a compare match, and the other compare unit is programmed to drive the signal to the opposite state on a compare match, and to clear the counter.
Enhanced Timers LZ87010 Advance User’s Guide PCLK T(x)CLK T(x)CMP REGISTER T(x)CNT REGISTER 0b11011011 0x02 0x03 0x00 0x01 T(x)CMP1 REGISTER 0x03 T(x)CMP0 REGISTER 0x00 0x02 0x03 0x00 PWM OUTPUT TM(x)CMP0 NOTE: (x) = 2 - 5 LZ87010-50 Figure 8-8.
LZ87010 Advance User’s Guide Enhanced Timers 8.2.8 Timer Interrupts Timer 2 and Timer 3 share interrupt vector 0x003B and interrupt level 7. Interrupt sources are: Overflow, Compare 0, Compare 1, Capture 0, and Capture 1. When any enabled interrupt condition in either of the two timers occurs, the interrupt service routine at 0x003B will be called.
Enhanced Timers LZ87010 Advance User’s Guide 8.3 Enhanced Timer Registers 8.3.1 T2CAP and T3CAP (Capture Control) Registers The two capture control registers, T2CAP and T3CAP, set the operating mode of the Timer 2 and Timer 3 capture units. Both timers have two capture units. These registers select the active edge (rising, falling, both, or none) on the external capture input signal that triggers a capture operation, and selects whether a capture will also generate an interrupt. Table 8-5.
LZ87010 Advance User’s Guide Enhanced Timers 8.3.2 T(x)CAP(y) (Captured Data) Registers When a capture event is triggered by asserting an external capture pin, the current 16-bit timer value is copied into a pair of 8-bit captured data registers, shown in Table 8-8. These registers are read-only. Half of these registers are low-byte registers (with names ending in ‘L’), which contain the lower 8 bits of the compare value.
Enhanced Timers LZ87010 Advance User’s Guide Table 8-13. T3CAP0H Register BIT FIELD RESET RW 7 6 5 4 3 2 1 0 T3CAP0[15] T3CAP0[14] T3CAP0[13] T3CAP0[12] T3CAP0[11] T3CAP0[10] T3CAP0[9] T3CAP0[8] 0 0 0 0 0 0 0 0 RO RO RO RO RO RO RO RO ADDR 0xEB Table 8-14.
LZ87010 Advance User’s Guide Enhanced Timers 8.3.3 T(x)CMP (Compare Control) Registers Each timer has two compare units, T(x)CMP0 and T(x)CMP1, whose operating modes are set in the T(x)CMP registers. The fields in these registers include interrupt enables, output edge selects, and PWM mode select. Table 8-17.
Enhanced Timers LZ87010 Advance User’s Guide 8.3.4 T(x)CMP[1:0][H:L] (Compare Data) Registers There are 16 Compare Data registers (four timers times two compare units times two registers per compare unit): T2CMP0H, T2CMP0L, T2CMP1H, T2CMP1L, T3CMP0H, T3CMP0L, T3CMP1H, T3CMP1L, T4CMP0H, T4CMP0L, T4CMP1H, T4CMP1L, T5CMP0H, T5CMP0L, T5CMP1H, T5CMP1L. All are read/write registers. Half of these registers are low-byte registers (with names ending in ‘L’), which contain the lower 8 bits of the compare value.
LZ87010 Advance User’s Guide Enhanced Timers 8.3.5 T(x)CNTH and T(x)CNTL (Timer Count) Registers The T(x)CNTH (timer count high) and T(x)CNTL (timer count low) registers contain the current value of the 16-bit timers. These registers can be read at any time, but writes to these registers while the timer is running will be ignored. The timers are enabled and disabled in the T(x)CON (timer control) registers, which also contain clock divider, interrupt enable, and other control fields.
Enhanced Timers LZ87010 Advance User’s Guide 8.3.6 T(x)CON (Timer Configuration) Registers The T(x)CON (timer configuration) registers set up the timers, with input clock source, input clock divider, enable/disable/clear control, and overflow interrupt enable fields. The timer should be stopped first (by setting the T(x)CON.CS field to zero) before other changes are made. Table 8-25.
LZ87010 Advance User’s Guide Enhanced Timers 8.3.7 T(x)STA (Timer Status) Registers The T(x)STA (timer status) registers contain status bits for the individual interrupt sources in the Timer unit. These bits are set when the corresponding condition occurs, regardless of whether the interrupt is enabled. Bits in this register remain set until cleared by software. Clearing a bit also clears the associated interrupt. Setting a bit does not cause an interrupt. Table 8-27.
Enhanced Timers LZ87010 Advance User’s Guide 8.3.8 TCMPOE (Timer Compare Output Enable) Register The TCMPOE (timer compare output enable) register determines which compare units are driven onto external pins. By enabling the compare units but disabling output, the compare units can be used to generate interrupts without occupying I/O pins. Table 8-29.
Chapter 9 Watchdog Timer The Watchdog Timer can be used to detect a ‘hung’ system and reset it, causing it to resume operation. If enabled, the Watchdog Timer will reset the system when it counts down to zero. The system software prevents this from occurring by periodically reloading the Watchdog Timer as part of a timer interrupt routine. If the software ceases functioning, the Watchdog Timer will not be reloaded before counting down to zero, and the system will be reset. 9.
Watchdog Timer LZ87010 Advance User’s Guide 9.1.2 Stopping the Watchdog Timer in Idle Mode If enabled, the Watchdog Timer continues to count in Idle mode, which is undesirable unless the system is guaranteed to spend only a short period in Idle mode. During long periods in Idle Mode, the Watchdog Timer might count down all the way to zero. If this happened, it would assert a Reset when Idle mode was exited.
LZ87010 Advance User’s Guide Watchdog Timer 9.2.2 WDTCNT Register Table 9-3. WDTCNT Register BIT FIELD RESET RW 7 6 5 4 3 2 1 0 WDTCD[7] WDTCD[6] WDTCD[5] WDTCD[4] WDTCD[3] WDTCD[2] WDTCD[1] WDTCD[0] 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW ADDR 0xAD Table 9-4. WDTCNT Register Bits BIT NAME DESCRIPTION Counter Data These bits have different read/write functions.
Chapter 10 UARTs 10.1 Theory of Operation The LZ87010 has two UARTs, UART 0 and UART 1. UART 0 is 8051-compatible. UART 1 is almost identical to UART 0, except that in Modes 1 and 3, it derives its serial clock from a dedicated baud rate generator, while UART 0 uses Timer 1. 10.1.1 Receive Operation In modes 1-3, incoming data on the RXD0 or RXD1 pin is signaled by a start bit that pulls the input LOW for one bit period. This is sampled on every cycle of a clock running at 16 times the UART’s baud rate.
UARTs LZ87010 Advance User’s Guide See NOTE 1 INTERNAL TO THE LZ87010 SCON.REN EXTERNAL TO THE LZ87010 NEW RI SCON.RI OLD RI DONE EN RI_IN 16X SERIAL CLOCK SM2 16XCLK SCON.SMOD[2] RECEIVE CONTROL RB8 MODE SAMPLE SCON.SMOD[1:0] START DETECT SHIFT RXD(x) SHIFT DIRECTION TO INTERRUPT CONTROLLER See NOTE 2 IN SHIFT RECEIVE SHIFT REGISTER SAMPLE WE D8 D7 D6 D5 D4 D3 D2 D1 D0 SCON.RB8 SBUF NOTES: 1. DONE = 1 If shifting is complete AND (RI_IN = 0) AND (SM2 = 0) OR (RB8 = 1) 2.
LZ87010 Advance User’s Guide UARTs See NOTE 1 INTERNAL TO THE LZ87010 SCON.REN EXTERNAL TO THE LZ87010 NEW RI SCON.RI OLD RI DONE EN RI_IN 16X SERIAL CLOCK CLK RCV RECEIVE CONTROL MODE SCON.SMOD[1:0] RXD(x) (Transmit and Receive Data) SHIFT DIRECTION TO INTERRUPT CONTROLLER IN SHIFT RECEIVE SHIFT REGISTER SAMPLE WE D7 D6 D5 D4 D3 D2 D1 D0 See NOTE 2 SBUF TXD(x) (Serial Clock) NOTES: 1. Done = 1 If shifting is complete AND (RI_IN = 0) 2.
UARTs LZ87010 Advance User’s Guide INTERNAL TO THE LZ87010 SCON.TB8 SCON.SMOD[1:0] EXTERNAL TO THE LZ87010 SMOD = 0b01 MODE SCON.TI DONE START TRANSMIT CONTROL TO INTERRUPT CONTROLLER SBUF SBUF WRITE 1 CLK 0 STOP D8 D7 D6 D5 D4 D3 D2 D1 D0 START XMIT LOAD TRANSMIT SHIFT REGISTER SERIAL CLOCK SERIAL OUT TXD(x) CLK SHIFT DIRECTION NOTE: In Mode 1, 10 bits are shifted (Start, D7 - D0, Stop). In Modes 2 and 3, 11 bits are shifted (Start, D8 - D0, Stop).
LZ87010 Advance User’s Guide UARTs TO INTERRUPT CONTROLLER INTERNAL TO THE LZ87010 EXTERNAL TO THE LZ87010 SCON.TI DONE CLK PCLK TRANSMIT CONTROL XMIT MODE SCON.SMOD[1:0] START SHIFT DIRECTION SHIFT LOAD RXD(x) (Transmit and Receive Data) TRANSMIT SHIFT REGISTER See NOTE D7 D6 D5 D4 D3 D2 D1 D0 SBUF WRITE SBUF TXD(x) (Serial Clock) NOTE: Serial data is 8 bits in Mode 0 (no START bit, 8 data bits, no STOP bit).
UARTs LZ87010 Advance User’s Guide 10.1.3 Generating Baud Rates Baud-rate generation is mode-dependent, as shown in Figure 10-5 and Figure 10-6. TIMER 1 DIVIDE BY 2 0 1 MUX SEL TCON.SMOD 16x BIT CLOCK (MODES 1 and 3) DIVIDE BY 16 0 PCLK 1 DIVIDE BY 64 2 3 MUX BIT CLOCK SEL 2 SCON.SMOD[1:0] LZ87010-96 Figure 10-5.
LZ87010 Advance User’s Guide UARTs BRGCNTH BRGCNTL 8 8 16 BAUD-RATE GENERATOR 16x BIT CLOCK (MODES 1 and 3) DIVIDE BY 16 0 PCLK 1 DIVIDE BY 64 2 3 MUX BIT CLOCK SEL 2 SCON1.SMOD[1:0] LZ87010-97 Figure 10-6.
UARTs LZ87010 Advance User’s Guide 10.1.3.1 Mode 0 In both UARTs, Mode 0 uses a fixed baud rate equal to PCLK. 10.1.3.2 Modes 1 and 3 UART 0 and 1 have a variable baud rate in these modes. In UART 0, the baud rate is generated by setting Timer 1 to auto-reload mode (Timer Mode 2). The formula for the baud rate is: ( PCON.SMOD + 1 ) × PCLKUART 0 Baud Rate = ------------------------------------------------------------------------32 × ( 256 – TH1 ) For example, if PCLK is 20 MHz (XTAL = 40 MHz) and PCON.
LZ87010 Advance User’s Guide UARTs 10.1.3.3 Mode 2 In Mode 2, both UARTs use a fixed baud rate of PCLK/64. 10.1.3.4 Crystal Selection for RS-232 Baud Rates Modes 1 and 3 can be used to generate standard RS-232 baud rates. Some readily available crystal frequencies are ideal for RS-232 baud-rate generation because they are an exact integer multiple of all the desired RS-232 data rates. For example, a 22.
UARTs LZ87010 Advance User’s Guide Table 10-2. UART 1 Baud Rate Example, Modes 1 and 3 20 MHz XTAL 22.1184 MHz XTAL 40 MHz XTAL BAUD RATE BRGCNT Error BRGCNT Error BRGCNT Error 110 4,681 0.0% 6,283 0.0% 11,363 0.0% 134.5 4,646 0.0% 5,138 0.0% 9,293 0.0% 300 2,082 0.0% 2,303 0.0% 4,166 0.0% 600 1,041 0.0% 1,151 0.0% 2,082 0.0% 1,200 520 0.0% 575 0.0% 1041 0.0% 2,400 259 -0.2% 287 0.0% 520 0.0% 4,800 129 -0.2% 143 0.0% 259 -0.2% 9,600 64 -0.
LZ87010 Advance User’s Guide UARTs 10.2 Signals Table 10-3 details the external signals for the UARTs. Table 10-3. UART Signals SIGNAL NAME SIGNAL TYPE PIN NUMBER PIN TYPE FUNCTIONAL UNIT SHARED WITH RXD0 I 60 I/O UART P3[0] UART 0 Receive Data RXD1 I 63 I/O UART P3[3] UART 1 Receive Data TXD0 O 61 I/O UART P3[1] UART 0 Transmit Data TXD1 O 62 I/O UART P3[2] UART 1 Transmit Data DESCRIPTION 10.3 UART Registers 10.3.
UARTs LZ87010 Advance User’s Guide Table 10-5. SCON and SCON1 Register Bits BIT NAME DESCRIPTION 7 SM[0] Serial Mode Determines the operating mode of the UART. See Table 10-6. 6 SM[1] Serial Mode Determines the operating mode of the UART. See Table 10-6. Serial Mode In Mode 0, this bit must be ‘0’. In other modes, this bit, if ‘1’, will suppress the Receive Data Interrupt if the data is not valid. The definition of ‘valid’ depends on the mode, as described below.
LZ87010 Advance User’s Guide UARTs 10.3.2 SBUF and SBUF1 (Serial Data Buffer) Registers Each UART has a serial buffer register (SBUF for UART 0, and SBUF1 for UART 1), which has different functions on reads and writes. Writing to SBUF or SBUF1 copies the written data to the output section of the UART, where it is shifted out the TXD0 or TXD1 pin as serial data. Reading SBUF or SBUF1 reads the least-significant eight bits of the character most recently received.
UARTs LZ87010 Advance User’s Guide 10.3.3 BRGCNTH and BRGCNTL (Baud Rate Generator Count) Registers The UART 1 baud rate generator is implemented as an auto-reloading 16-bit countdown time clocked by PCLK. When the counter rolls over, it is reloaded with the 16-bit value in the BRGCNTH and BRGCNTL registers.
Chapter 11 External Memory 11.1 Theory of Operation The LZ87010 supports up to 64KB of external memory, using an interface bus consisting of a 16-bit address bus (XMA[15:0]), an 8-bit data bus (XMD[7:0]), a write-enable signal (nPSWR), and an output enable signal (nPSEN). This interface is suitable for glueless operation with asynchronous memory devices such as static RAMs, EPROMs, and EEPROMs. At reset, Flash is enabled and external memory is disabled.
External Memory LZ87010 Advance User’s Guide FLASH XMBNK[2:0] ADDRESS RANGE EXTERNAL MEMORY ADDRESS RANGE 000 0x0000 - 0xDFFF 0xE000 - 0xFFFF 001 0x0000 - 0xBFFF 0xC000 - 0xFFFF 010 0x0000 - 0x9FFF 0xA000 - 0xFFFF 011 0x0000 - 0x7FFF 0x8000 - 0xFFFF 100 0x0000 - 0x5FFF 0x6000 - 0xFFFF 101 110 0x0000 - 0x3FFF 0x0000 - 0x1FFF 0x4000 - 0xFFFF 0x2000 - 0xFFFF 111 NONE 0x0000 - 0xFFFF INTERNAL TO THE LZ87010 EXTERNAL TO THE LZ87010 FLASH MEMORY MEMORY MAP CONTROL XMCFG.XMBNK XMCFG.
LZ87010 Advance User’s Guide External Memory 11.2 Signals All of the external memory signals are shared with I/O ports, as shown in Table 11-1. Port 2, Port 5, and Port 8 are used in their entirety for address and data buses, while two bits of Port 1 provide output enable and write enable signals. The 16-bit address uses two 8-bit ports. One of these, Port 2, is a high-current output port, while the other, Port 8, is a general-purpose I/O port.
External Memory LZ87010 Advance User’s Guide 11.3 Registers The external memory system is controlled by a single register, XMCFG. This register enables external memory, determines how much of the Flash memory is replaced by external memory, and sets the number of wait states to use on memory accesses. Table 11-2.
LZ87010 Advance User’s Guide External Memory 11.4 External Memory Timing When the LZ87010 reads data, the address is asserted first on XMA[15:0], followed by the assertion of the output enable, nPSEN, as shown in Figure 11-2. nPSEN is asserted for one cycle plus the number of wait states specified in the XMCFG register. Figure 11-3 shows a read with one wait state. The data on the XMD[7:0] pins is latched when nPSEN is deasserted.
LZ87010 Advance User’s Guide XMD[7:0] nPSWR nPSEN XMA[15:0] CCLK A1 D1 A2 LZ87010-27 External Memory Figure 11-2.
External Memory XMD[7:0] nPSWR nPSEN XMA[15:0] CCLK A1 D1 A2 LZ87010-71 LZ87010 Advance User’s Guide Figure 11-3.
LZ87010 Advance User’s Guide nPSWR nPSEN XMD[7:0] XMA[15:0] CCLK A1 D1 A2 LZ87010-28 External Memory Figure 11-4.
External Memory nPSWR nPSEN XMD[7:0] XMA[15:0] CCLK A1 D1 A2 LZ87010-72 LZ87010 Advance User’s Guide Figure 11-5.
Chapter 12 Interrupts 12.1 Theory of Operation 12.1.1 Interrupt-Related Registers Many of the registers in the LZ87010 are interrupt-related, containing interrupt enable, status, or priority bits. Table 12-1 is a list of registers with interrupt-related functions. Table 12-1.
Interrupts LZ87010 Advance User’s Guide 12.1.2 Interrupt Vectors The LZ87010 uses 13 different interrupt vectors, each dedicated to a particular use. For example, a Timer 0 interrupt causes the interrupt controller to call the interrupt routine at 0x000B, while a Timer 1 interrupt calls the interrupt routine at 0x001B. Table 12-2 lists all of the interrupt vectors and their sources.
LZ87010 Advance User’s Guide Interrupts 12.1.2.1 Vectors and Status Bits An interrupt vector that is shared between two or more interrupt sources requires a status register so the interrupt handler can determine which interrupt was asserted. For example, Timer 2 has five interrupt sources that are handled by a single vector. The T2STA register contains a bit for each interrupt source, allowing the interrupt handler to determine which sources are active.
Interrupts LZ87010 Advance User’s Guide 12.1.3 Interrupt Sources Most of the functional units in the LZ87010 can assert interrupts. The different interrupt sources are listed in Table 12-3. Table 12-3. Interrupt Summary INTR. PIN ENABLE STATUS ADC IE1.EADC ADCC.STATUS* DAC0 IE1.EDAC0 DAC1 IE1.EDAC1 DESCRIPTION ADC Interrupt Asserted at end of analog conversion. DAC 0, DAC 1 Interrupts Asserted after a pre-selected number of waveform generator outputs, as set in WGCFG(x).
LZ87010 Advance User’s Guide Interrupts 12.1.4 Interrupt Priority There are four interrupt priority levels, given as a two-bit quantity. The LSB is in IP or IP1, while the MSB is in IPH or IPH1. For example, the Timer 0 interrupt priority LSB is in IP1 and its MSB is in IPH1. Interrupt 0b00 is the lowest priority and 0b11 is the highest. Note that this is the reverse of the numbering scheme used for interrupt levels. 12.1.
Interrupts LZ87010 Advance User’s Guide 12.1.5.2 INT[7:2] The external interrupts INT[7:2] consist of six interrupt pins sharing a single vector. The six pins are either all level-triggered on a LOW level or all edge-triggered on a rising edge. See Figure 12-1. The INT[7:2] pins have no status register. Instead, these interrupts are mapped to the same pins as P0[7:2]. Because both functions of dual-function pins are simultaneously active, the state of the interrupt pins can be read by reading P0.
LZ87010 Advance User’s Guide Interrupts 12.2 Signals Table 12-4 shows the interrupt request signals in the LZ87010. Table 12-4. Interrupt Signals SIGNAL NAME SIGNAL TYPE PIN NUMBER PIN TYPE FUNCTIONAL UNIT SHARED WITH INT[7:0] I 83:76 I/O Interrupts P0[7:0] DESCRIPTION Interrupt Request Signals 12.3 Registers This section lists registers that deal primarily with interrupts. Many other registers have some interrupt-related functions.
Interrupts LZ87010 Advance User’s Guide 12.3.2 IE (Interrupt Enable) Register The IE (interrupt enable) register contains a global interrupt enable bit and individual interrupt enable bits for the standard 8051 interrupts. Table 12-7. IE Register BIT FIELD 7 6 5 4 3 2 1 0 EA /// /// ES ET1 EX1 ET0 EX0 RESET RW 0 0 0 0 0 0 0 0 RW RO RO RW RW RW RW RW ADDR 0xA8 Table 12-8. IE Register Bits BIT NAME 12-8 DESCRIPTION 7 EA Enable All Global interrupt enable bit.
LZ87010 Advance User’s Guide Interrupts 12.3.3 IE1 (Interrupt Enable 1) Register The IE1 (Interrupt Enable 1) register contains individual interrupt enable bits for extended interrupts. Table 12-9. IE1 Register BIT FIELD 7 6 5 4 3 2 1 0 EX2 EDAC1 EDAC0 EADC ES1 EI2C ET2T3 ET4T5 RESET RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW ADDR 0xE8 Table 12-10. IE1 Register Bits BIT NAME DESCRIPTION 7 EX2 6 EDAC1 Enable Extended Interrupt 12 (DAC 1) If ‘0’, they are disabled.
Interrupts LZ87010 Advance User’s Guide 12.3.4 IP and IPH (Interrupt Priority) Registers The IP and IPH (Interrupt Priority) registers set the priority of the standard 8051 interrupts. Priority level is a two-bit number, with priority 0b00 being the lowest priority and 0b11 the highest. The least-significant bits of the individual interrupt priorities are in the IP and IP1 registers, while the most-significant bits are in the IPH and IPH1 registers.
LZ87010 Advance User’s Guide Interrupts 12.3.5 IP1 and IPH1 (Interrupt Priority) Registers The IP1 and IPH1 (Interrupt Priority) registers set the priority of the extended interrupts. Priority level is a two-bit number, with priority 0b00 being the lowest priority and 0b11 the highest. The least-significant bits of the individual interrupt priorities are in the IP and IP1 registers, while the most-significant bits are in the IPH and IPH1 registers. Table 12-13.
Chapter 13 Analog Inputs (ADC) 13.1 Theory of Operation The 8 analog inputs AN[7:0] connect to an 8:1 analog multiplexer, which in turn connects to a 12-bit analog-to-digital converter (ADC), using a successive approximation register (SAR) algorithm. Figure 13-1 shows a block diagram of the ADC. The maximum voltage of the ADC is set by the voltage reference signal ADVREF. The maximum conversion rate is 500,000 samples per second (with a 10 MHz ADC clock). The ADC unit is clocked by a divided HFCLK signal.
Analog Inputs (ADC) LZ87010 Advance User’s Guide EXTERNAL TO THE LZ87010 ANALOG INPUTS INTERNAL TO THE LZ87010 AN[7] 7 AN[6] 6 AN[5] 5 AN[4] 4 AN[3] 3 AN[2] 2 AN[1] 1 AN[0] 0 ADCC.START ADCCLK START CLK nPD 12-BIT ADC AIN MUX ADCC.PWEN TO INTERRUPT CONTROLLER DONE DIGITAL OUTPUT ADC[3:0] 0b0000 ADC[11:4] SEL 8 4 4 3 ADCC.SEL ADCDL ADCDH ADCC.STATUS IE1.EADC LZ87010-85 Figure 13-1. ADC Block Diagram 13.2 Signals Table 13-1 details the ADC Signals. Table 13-1.
LZ87010 Advance User’s Guide Analog Inputs (ADC) 13.3 Registers 13.3.1 ADCC (ADC Control) Register The ADCC (ADC Control) register contains the ADC’s configuration and status bits. Table 13-2. ADCC Register BIT 7 6 5 4 3 2 1 0 FIELD PWEN /// /// STATUS START SEL[2] SEL[1] SEL[0] RESET 0 0 0 0 0 0 0 0 RW RW RW R RW RW RW RW RW ADDR 0xC3 Table 13-3. ADCC Register Bits BIT NAME DESCRIPTION Power Enable Allows the ADC to be turned off when not in use to conserve power.
Analog Inputs (ADC) LZ87010 Advance User’s Guide 13.3.2 ADCDH (ADC Data High) Register The ADCDH (ADC Data High) register returns the upper 8 bits of the 12-bit analog-to-digital conversion. Table 13-4. ADCDH Register BIT FIELD RESET RW 7 6 5 4 3 2 1 0 ADCD[11] ADCD[10] ADCD[9] ADCD[8] ADCD[7] ADCD[6] ADCD[5] ADCD[4] 0 0 0 0 0 0 0 0 RO RO RO RO RO RO RO RO ADDR 0xC2 Table 13-5.
LZ87010 Advance User’s Guide Analog Inputs (ADC) 13.3.3 ADCDL (ADC Data Low) Register The ADCDL (ADC Data Low) register returns the lower 4 bits of the 12-bit analog-to-digital conversion. Note that these bits are left-aligned in the register. Table 13-6. ADCDL Register BIT 7 6 5 4 3 2 1 0 FIELD ADCD[3] ADCD[2] ADCD[1] ADCD[0] /// /// /// /// RESET 0 0 0 0 0 0 0 0 RO RO RO RO RO RO RO RO RW ADDR 0xC1 Table 13-7.
Chapter 14 Analog Outputs (DAC) 14.1 Theory of Operation The LZ87010 has two identical 8-bit digital-to-analog converters (DACs), DAC0 and DAC1. Each DAC has an associated waveform generator with 128 bytes of RAM. Figure 14-1 shows a block diagram of one DAC and waveform generator. 14.1.1 Digital-to-Analog Converter (DAC) The DAC is implemented as a pair of 4-bit static sub-ranging DACs with power-down.
Analog Outputs (DAC) LZ87010 Advance User’s Guide EXTERNAL TO THE LZ87010 IVL[2:0] INTERRUPT INTERVAL STEP[2:0] 000 INT DISABLED 000 0 001 1 001 1 010 2 010 2 011 4 011 4 100 8 100 8 101 110 16 32 101 110 16 32 111 64 111 RESERVED INTERNAL TO THE LZ87010 WGCTL(x).IVL STEP SIZE WGCTL(x).STEP WGCTL(x).
LZ87010 Advance User’s Guide Analog Outputs (DAC) 14.1.2 Waveform Generator The waveform generator can send a new value to the DAC automatically, on each cycle of its selected input clock. This clock can be external, on the WFGIN0 or WFGIN1 pin, or internal, using the output of one of the Timer 2-5 Compare units. The waveform generator has a selectable step size and a programmable interrupt rate. See Figure 14-2.
Analog Outputs (DAC) LZ87010 Advance User’s Guide 14.2 Signals Table 14-1 details the DAC and waveform generator signals. Table 14-1.
LZ87010 Advance User’s Guide Analog Outputs (DAC) 14.3.2 WGCTL0 and WGCTL1 (Control) Registers The WGCTL0 and WGCTL1 (Waveform Generator Control) registers select the clock source for the waveform generator, determine whether processor writes go to the waveform generator or directly to the DAC, and start or stop the waveform generator. Table 14-4.
Analog Outputs (DAC) LZ87010 Advance User’s Guide 14.3.3 WGCFG0 and WGCFG1 (Configuration) Registers The WGCFG0 and WGCFG1 (Waveform Generator Configuration) registers control the interrupt interval (the number of waveform generator input clocks between interrupts) and the memory step (the number of bytes added to the waveform generator index after an access). Table 14-7.
LZ87010 Advance User’s Guide Analog Outputs (DAC) 14.3.4 WGINX0 and WGINX1 (Index) Registers The WGINX0 and WGINX1 (Waveform Generator Index) registers hold a pointer to the next byte in waveform memory that will be sent to the DAC. Table 14-11. WGINX Registers BIT 7 6 5 4 3 2 1 0 FIELD /// INDEX[6] INDEX[5] INDEX[4] INDEX[3] INDEX[2] INDEX[1] INDEX[0] RESET RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW WGINX0: 0xCE WGINX1: 0xCF ADDR Table 14-12.
Analog Outputs (DAC) LZ87010 Advance User’s Guide 14.3.6 WGMD0 and WGMD1 (Memory Data) Registers The WGMD0 and WGMD1 (Waveform Generator Memory Data) registers are used to access waveform memory or the DACs. If waveform memory accesses are enabled, (WGCTL(x).WEN = 1) reads and writes go to waveform memory. Otherwise (WGCTL(x).WEN = 0), they go directly to the DAC. Table 14-15.
Chapter 15 2 I C Interface 15.1 Theory of Operation The LZ87010 includes a two-wire I2C serial interface capable of operating in either Master or Slave mode. The two wires are SCL (serial clock) and SDA (serial data). Both are opencollector I/O pins. The interface has a single byte of serial data buffering on receive and transmit. Registers provide control over operating mode, serial clock frequency, and slave-mode address.
I2C Interface See Table 15-2 for sample calculations of the HIGH count. The LOW count is calculated in the same way. Table 15-2. Sample I2C HIGH Period Counts I2C DATA SCL HIGH PCLK (MHz) H_CNT SCL HIGH RATE (kbit/s) REQUIRED MIN. (s) TIME (s) 100 6.6 4 24 4.09 100 9.9 4 37 4.14 400 10 0.6 2 0.60 400 15.3 0.6 6 0.654 400 20 0.6 8 0.66 15.
I2C Interface LZ87010 Advance User’s Guide 15.2.1 Slave Mode In slave-receiver mode, the interface interrupts the processor whenever an address or data byte has been received. The sequence is that the byte is received and acknowledged by the interface, then the processor is interrupted. The ICDATA register will contain a data byte, 7-bit Slave address, or one of the two 10-bit Slave address bytes. Status bits in the ICSTAT and ICDBUG registers allow the processor to determine the type of transfer.
I2C Interface 15.4 Registers 15.4.1 ICCON (I2C Configuration) Register The ICCON register sets the operating mode of the interface and contains the flags used to start a transfer and to set the data direction. Table 15-4. ICCON Register BIT FIELD RESET RW 7 6 5 4 3 2 1 0 RS_P_N R_W_N_CTRL P_TRNSFR S_TRNSFR FS_STD_N I2C_EN MODE[1] MODE[0] 0 0 0 0 1 0 0 0 RW RW RW RW RW RW RW RW ADDR 0xB4 Table 15-5.
I2C Interface LZ87010 Advance User’s Guide 15.4.2 ICSAR (I2C Slave Address) Register The ICSAR register holds the unit address used by the interface when in Slave mode. In 7-bit addressing mode, the entire address is contained in this register, plus a read/write data-direction bit. In 10-bit addressing mode, this register holds the lower 8 address bits, and the upper two bits and the R/W bit are in the ICUSAR register. This register is not used in Master mode. Table 15-6.
I2C Interface 15.4.3 ICUSAR (I2C Upper Slave Address) Register The ICUSAR (I2C Upper Slave Address) Register holds the upper 2 address bits in 10-bit addressing mode, plus a data direction (R/W) bit. This register is not used in Master mode. Table 15-8. ICUSAR Register BIT FIELD RESET RW 7 6 5 4 3 2 1 0 U_AR[4] U_AR[3] U_AR[2] U_AR[1] U_AR[0] S_ADDR[9] S_ADDR[8] R/W 1 1 1 1 0 0 0 0 RW RW RW RW RW RW RW RW ADDR 0xB6 Table 15-9.
I2C Interface LZ87010 Advance User’s Guide 15.4.4 ICDATA (I2C Data) Register The ICDATA register holds the received serial data or the serial data to be transmitted. Table 15-10. ICDATA Register BIT 7 6 5 4 3 2 1 0 FIELD DAT[7] DAT[6] DAT[5] DAT[4] DAT[3] DAT[2] DAT[1] DAT[0] RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW ADDR 0xB7 Table 15-11.
I2C Interface 15.4.5 ICHCNT (I2C Clock High Time) Register The ICHCNT register sets the period for the serial clock HIGH time. Table 15-12. ICHCNT Register BIT 7 6 5 4 3 2 1 0 FIELD H_CNT[7] H_CNT[6] H_CNT[5] H_CNT[4] H_CNT[3] H_CNT[2] H_CNT[1] H_CNT[0] RESET 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW ADDR 0xBC Table 15-13. ICHCNT Register Bits BIT 7:0 15-8 NAME DESCRIPTION H_CNT[7:0] High Count This register sets the SCL HIGH period.
I2C Interface LZ87010 Advance User’s Guide 15.4.6 ICLCNT (I2C Clock Low Time) Register The ICLCNT register sets the period for the serial clock LOW time. Table 15-14. ICLCNT Register BIT FIELD RESET RW 7 6 5 4 3 2 1 0 L_CNT[7] L_CNT[6] L_CNT[5] L_CNT[4] L_CNT[3] L_CNT[2] L_CNT[1] L_CNT[0] 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW ADDR 0xBD Table 15-15. ICLCNT Register Bits BIT 7:0 NAME DESCRIPTION Low Count This register sets the SCL LOW clock time.
I2C Interface 15.4.7 ICDBUG (I2C Debug) Register The ICDBUG register holds real-time status about the current transfer. Table 15-16. ICDBUG Register BIT 7 6 5 4 3 2 1 0 FIELD /// /// I2C_W I2C_R ADDR DATA P_DET S_DET RESET 0 0 0 0 0 0 0 0 RO RO RO RO RO RO RO RO RW ADDR 0xBE Table 15-17. ICDBUG Register Bits 15-10 BIT NAME DESCRIPTION 7:6 /// 5 I2C_W Write in Progress Set to ‘1’ during write transfers on the I2C bus.
I2C Interface LZ87010 Advance User’s Guide 15.4.8 ICSTAT (I2C Status) Register The ICSTAT register gives status about the state of the interface. Table 15-18. ICSTAT Register BIT 7 6 5 4 3 2 1 0 FIELD SLV_ADDR RX_ABRT TX_ABRT IDLE 10_BIT_ADDR OVRFLW FULL_FLG INTR RESET 0 0 0 0 0 0 0 0 RO RO RO RO RO RO RO RO RW ADDR 0xBF Table 15-19.
Chapter 16 Debug Interface 16.1 Theory of Operation The SHARP Debug Interface (SDI) consists of sophisticated on-chip debugging hardware including support for multiple hardware breakpoints and unlimited software breakpoints, plus a 128-element branch trace buffer. A sophisticated trigger mechanism allows breakpoints to be set on ranges of code or data addresses or on data values. Communication to external debuggers is provided over a high-speed, two-wire serial interface, using SDI_CLK and SDI_DATA.
Debug Interface LZ87010 Advance User’s Guide 16.2 Signals The SDI_CLK and SDI_DATA signals provide the serial data stream between the LZ87010 and the debugging unit. Both signals include internal weak pull-up resistors to VDD. Table 16-1. Debug Signal Descriptions SIGNAL NAME 16-2 SIGNAL PIN PIN FUNCTIONAL TYPE NUMBER TYPE UNIT DESCRIPTION SDI_CLK I 70 I Debug SHARP Debug Interface Clock. If no debugger is used, leave this pin unconnected.
Chapter 17 Reset 17.1 Theory of Operation The LZ87010 has an active-HIGH RESET signal with an internal pull-down resistor (with a nominal value of 90 kΩ). The recommended RESET pulse width is 38 HFCLK cycles, starting after VDD and the system oscillators are stable. For debugging, a simple push-button switch between RESET and VDD gives good results without additional circuitry. 17.2 Signals Table 17-1. Reset Signal SIGNAL SIGNAL NAME TYPE RESET I PIN NO.
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