Sequans Module VZM20Q Module Integration Guide SEQUANS Communications 15-55, Boulevard Charles de Gaulle 92700 Colombes, France Phone. +33.1.70.72.16.00 Fax. +33.1.70.72.16.09 www.sequans.com contact@sequans.
Preface Legal Notices Copyright© 2016, SEQUANS Communications All information contained herein and disclosed by this document is confidential and the proprietary property of SEQUANS Communications, and all rights therein are expressly reserved. Acceptance of this material signifies agreement by the recipient that the information contained in this document is confidential and that it will be used solely for the purposes set forth herein.
Document Revision History Revision 01 ii Date November 2016 Product Application First edition of the VZM20Q Module Integration Guide.
About this Guide Purpose and Scope This Application note is intended to help customers who want to deviate from the Sequans’ Reference Designs to successfully integrate and test their product based on module. It presents Integration Guidelines for: • All VZM20Q Interface Requirements • Tips and “how-to”s for troubleshooting Development of the Hardware should follow a process that ensures the solution will be optimum and it is the purpose / goal of this document to reach this.
Reference Documentation 1. DV Tool User Guide 2. Sequans Hardware Platform User Guide 3. mTools Reference Manual 4. Nimbelink™ Evaluation Kit User Manual See http://nimbelink.com/ Changes in this Document This is the first edition of the document.
Documentation Conventions This section illustrates the conventions that are used in this document. General Conventions Note Important information requiring the user’s attention. A condition or circumstance that may cause damage to the equipment or loss of data. Caution A condition or circumstance that may cause personal injury. Warning Italics Italic font style denotes • emphasis of an important word; • first use of a new term; • title of a document.
Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii About this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 Introduction to UART Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 General Notes on UART Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 UART0 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 UART1 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents A.1.1 LTE RF Test Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Appendix B Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction 1 1.1 System Architecture Figure 1-1 provides an overview of the Host to VZM20Q interfacing relationship. The various interfaces are explained in detail later in this document. It provides summary details of: • Digital interfaces between the VZM20Q and the host platform • Power supply requirement (Vbat). Note: VBAT1 range is 3.1 V to 4.5 V. It does not show the VZM20Q local terminations.
INTRODUCTION SYSTEM ARCHITECTURE Figure 1-2: VZM20Q Mounted on Skywire™ 4G LTE CAT M1 Embedded Modem Figure 1-3: Skywire™ 4G LTE CAT M1 Embedded Modem - Bottom View 2 PROPRIETARY SEQUANS Communications MODULE INTEGRATION GUIDE
INTRODUCTION RECOMMENDED DESIGN FLOW Note: 1.2 The hardware design package of VZM20Q reference design is available from your Sequans local contact. Recommended Design Flow To ensure that the customer benefits from the details of this document we recommend to carefully take the following information into account during the design process. 1.2.
INTRODUCTION RECOMMENDED DESIGN FLOW 1.2.4 Optimization When the design returns from the manufacture, it might occur that improvements have to be made to the circuits. It is also recommended to communicate such results to Sequans who can help to verify the implementation. 1.2.5 Functional Validation The test of the design performance should be done in thorough detail. This will ensure the compliance with the test standard as the final design will be subjected to a formal qualification.
Manufacturing Process 2 2.1 Manufacturing Process Overview Note: 2.2 The contents of this section will be provided in a future revision of the document. Module Upgrade Note: MODULE INTEGRATION GUIDE The contents of this section will be provided in a future revision of the document.
3 Hardware Integration Recommendations This chapter provides the information necessary to understand the various interface requirements to interconnect with the VZM20Q, associated software-configurable items for the respective interface and, more generally, good practices for board design when considering the various interface types. Table 3-1 describes the requirements for trace characteristics. Important: Different signals require different special needs.
HARDWARE INTEGRATION RECOMMENDATIONS POWER SUPPLY 3.1 Power Supply 3.1.1 Synthesis of the Power Supplies Table 3-2 and Table 3-3 provide a synthesis of the power supplies and their characteristics. Please see typical voltage values in VZM20Q Datasheet. Note: Each output reference voltage (pads 3, 9, 11) can be either running or powered off depending on the internal software configuration. They should not be used to power external IC or parts that require permanent supply.
HARDWARE INTEGRATION RECOMMENDATIONS SIM INTERFACE 3.1.2 Power Supply Circuit Example 3.1.2.1 Test Points and Measurement Access Test point access is recommended on all supply nets so that the supply voltages can be measured. 3.1.2.2 Special Layout Considerations PLease refer to Section 4.2.2 Power Supply Traces on page 24. 3.1.3 Module Operating Mode Note: The contents of this section will be provided in a future revision of the document. 3.2 SIM Interface 3.2.
HARDWARE INTEGRATION RECOMMENDATIONS HOST COMMUNICATIONS SIGNALS 3.2.2 3.2.3 Other Hardware Considerations • When considering the placement of the SIM connector and Monarch SIM interface, try to keep the distance between them as small as possible. This is to avoid supply trace inductance buildup which could cause unexpected SIM VCC supply drops under specific SIM control situations. If it is unavoidable, then be sure to add 4.
HARDWARE INTEGRATION RECOMMENDATIONS HOST COMMUNICATIONS SIGNALS 3.3.2 General Notes on UART Connections VZM20Q uses the DCE-DTE convention for UART lines. The TXD output from the device at one end of the link connects to the RXD input at the other end of the link and vice versa. Figure 3-1 represents the typical implementation for the UART connection (including hardware flow control in case of high-speed UART). TXD and RXD signals are mandatory for all interfaces. The other signals are optional.
HARDWARE INTEGRATION RECOMMENDATIONS HOST COMMUNICATIONS SIGNALS 3.3.3 UART0 Interface 3.3.3.1 Interface Description Important: • See the Section 3.3.2 General Notes on UART Connections on page 10 for usage of UART0. • If not used, the UART0 signals should be connected to test points. Table 3-4 lists the VZM20Q pins related to the UART0 interface. Table 3-5: UART Interface Signals Pin Name Pin Number Trace Style Direction Electrical Characteristics Notes RXD0 79 Digital Out 1.
HARDWARE INTEGRATION RECOMMENDATIONS HOST COMMUNICATIONS SIGNALS 3.3.3.2 Default Configuration The default software configuration of UART0 is AT Commands mode. The serial link settings are as follows: • Baud rate: 921600 • Data: 8 bits • Parity: None • Stop : 1 bit • Flow control: Hardware (RTS/CTS) 3.3.4 UART1 Interface 3.3.4.1 Interface Description Important: • See the Section 3.3.2 General Notes on UART Connections on page 10 for usage of UART1.
HARDWARE INTEGRATION RECOMMENDATIONS HOST COMMUNICATIONS SIGNALS 3.3.4.2 Default Configuration The default software configuration of UART1 is console mode. Boot traces are sent on this interface as shown on Section 5.4.2 Confirm Module Power-Up Operation (UART1) on page 32. The serial link settings are as follows: • Baud rate: 115200 • Data: 8 bits • Parity: None • Stop : 1 bit • Flow control: None 3.3.5 UART2 Interface 3.3.5.1 Interface Description Important: • See the Section 3.3.
HARDWARE INTEGRATION RECOMMENDATIONS HOST COMMUNICATIONS SIGNALS 3.3.5.2 Default Configuration UART2 default software configuration allows firmware upload when the device is configured in FFH mode, then it switchs in debug mode (enabling DVTool, DMTool).
HARDWARE INTEGRATION RECOMMENDATIONS RF INTERFACE 3.4 RF Interface 3.4.1 RF Signals 3.4.1.1 RF Interface Signals Table 3-8: RF Interface Signals Pin Name Pin Number Trace Style Direction Electrical Characteristics LTE_ANT0 54 RF In/Out RF GNSS_ANT1 44 3.4.1.2 Notes LTE antenna. Special RF routing conditions Reserved Reserved. Do not connect.
HARDWARE INTEGRATION RECOMMENDATIONS RF INTERFACE 3.4.2 Circuit Diagram Example Important: Figure 3-4 should be strictly followed as a topology reference. It is recommended not to deviate from this circuit from your application. More information is provided in this document on the layout constraint which are too very important to abide by. The RF inter-connect called P1 is for example purposes only. Depending on the antenna, interfacing system will dictate the RF inter-connect.
HARDWARE INTEGRATION RECOMMENDATIONS RF INTERFACE 3.4.3 Test Points and Measurement Access 50 Ohm termination points, for example P1 in Figure 3-2, are needed for Engineering and Production teams for the validation of the RF performance. The potential need to optimize the Pi-type matching network in the antenna path means that access to the IOs of this matching network is needed, so that a coaxial cable (usually 1.25mm diameter semi-rigid) can be manually attached for precision impedance measurements.
HARDWARE INTEGRATION RECOMMENDATIONS RF INTERFACE 3.4.4.2 ESD Protection ESD protection is a discretionary requirement and only required if necessary, for higher ESD specifications than those provided by the VZM20Q. It is recommended to select an ESD device with very low capacitance and small size (0201) to prevent further RF matching compensation. 3.4.4.3 Standard Impedance Transmission Lines There are 2 possible methods to design 50 Ohm transmission lines: 1.
HARDWARE INTEGRATION RECOMMENDATIONS RF INTERFACE Figure 3-3: Transmission Line Implementation Examples Figure 3-3 provides examples of both transmission line implementations, specifically showing: a) The clearance from the transmission line to adjacent metal on layer 1. b) The periodic via connections connecting metal-1 layer through to the reference GND layer for the transmission line.
HARDWARE INTEGRATION RECOMMENDATIONS RESET AND ENVIRONMENTAL SIGNALS 3.5 Reset and Environmental Signals Table 3-10 lists the Reset and other environmental signals and the following subsections describe their purpose and termination requirements. Table 3-10: Non-Interfacing Signals Pin Number Direction Electrical Characteristics RESETN 47 Out 1V8 GPIO3/STATUS_LED 2 In/Out 1V8 - GPIO - Optional STATUS_LED. Note that the LED function is currently not available.
HARDWARE INTEGRATION RECOMMENDATIONS GPIO CONTROL INTERFACE 3.6 GPIO Control Interface 3.6.1 Interface Description Several general purpose IOs are available: Table 3-11: GPIOs Signals Pin Number Direction Electrical Characteristics GPIO14/TXD1 78 In/Out 1V8 UART1 TXD (Input) alternate function to GPIO. See Section UART1 Interface. GPIO15/RXD1 80 In/Out 1V8 UART1 RXD (Output) alternate function to GPIO. See Section UART1 Interface.
HARDWARE INTEGRATION RECOMMENDATIONS GPIO CONTROL INTERFACE Table 3-11: GPIOs Signals (Continued) Pin Number Direction Electrical Characteristics GPIO40/POWER_SHDN 90 In/Out 1V8 GPIO, emergency power shutdown signal (Input) in option. In emergency powershutdown mode, 1 kOhm PU needed, pin should be forced low level to trigger emergency shutdown procedure. Note that this feature is currently not available. GPIO2/POWER_MON 6 In/Out 1V8 GPIO or Power monitor (Output) in option.
PCB Layout Rules 4 This section provides general good practices in defining a PCB layout. 4.1 Placement It is good to perform the placement of all the major components blocks before routing any section of the PCB design. The considerations here are: • VZM20Q module • RF interface Initial placement of these parts allows assessment of the PCB floor plan usage and avoids any significant changes to final routed areas of the design if a placement issue is found.
PCB LAYOUT RULES TRACE CHARACTERISTIC DESIGN 4.2 Trace Characteristic Design This section explains some standard design rules when considering different types of signals involved (digital, power supply, RF). 4.2.1 Digital Traces 1. Careful and logical placement of digital signals are required to ensure separation of digital interference between each other and unrelated traces. 2. Consider the flow of ground currents during routing.
PCB LAYOUT RULES TRACE CHARACTERISTIC DESIGN 4.2.3 RF Traces 1. Avoid burying these traces as much as possible, because it increases RF losses compared with routing on the top. 2. Keep as short as possible to help reduce RF losses. 3. Design the impedance of the trace keeping in mind that the footprint of the RF components should be of similar width. This help avoid impedance discontinuities. 4.
PCB LAYOUT RULES TRACE CHARACTERISTIC DESIGN 4.2.5 Grounding 1. Stitch ground areas together with vias where flooded ground remains unterminated. 2. Stitch ground areas together in general to keep common ground impedance the same across the region. 3. RF ground planes should be as large and continuous as possible and not be cut into small islands. Check that strings of vias do not inadvertently create slots in ground or power planes.
Bring-Up and Testing 5 5.1 Introduction The purpose of this chapter is to describe what has to be done for board bring-up, test and qualification. The expectations at this stage of the product’s life are: 1. Consider any inconsistent and potentially hazardous manufacturing faults to be eliminated. 2. Confirm that it is safe to proceed to further detailed calibration and measurement steps. 3. Evaluate board performances. 5.
BRING-UP AND TESTING FUNCTIONAL VERIFICATION WITHOUT ASSEMBLED MODULE 3. LTE RF test equipments Setup a) Shielding box to avoid any RF performances results degradation due to environment b) RF components such as: cable, splitter, 50 Ohm loads corresponding to the RF working band 4. Power supply with current measuring ability 5.3 Functional Verification without Assembled Module Attention: If a fault is discovered, consider the impact of the issue observed on all the manufactured samples.
BRING-UP AND TESTING FUNCTIONAL VERIFICATION WITHOUT ASSEMBLED MODULE • Test voltage values Test the DC nature of the voltage with an oscilloscope before connecting the DUT. Once the DC source is confirmed, you can power the DUT and measure accurately the test points voltage with a multimeter. At this stage, only VBAT1 can be tested. Check at each voltage test point, as illustrated on Figure 5-2, that the voltage value corresponds to what is expected.
BRING-UP AND TESTING FUNCTIONAL VERIFICATION WITHOUT ASSEMBLED MODULE 5.3.2 RF Path 5.3.2.1 Test Procedure Important: Those tests should be run or supervised by engineers with RF measurement preparation and test experience. • RF path check To avoid any issue on RF extra path (from the VZM20Q module antenna output to the board antenna connector), the purpose of this part is to check its integrity. It corresponds to losses between VZM20Q pin 54 and/or pin 44 and the antenna ports of the board.
BRING-UP AND TESTING FUNCTIONAL VERIFICATION WITH ASSEMBLED MODULE 5.4 Functional Verification with Assembled Module Attention: If a fault is discovered, consider the impact of the issue observed on all manufactured samples. The purpose of this section is to validate the assembly process of the module. This test covers: 1. VZM20Q pins and features: a) Power supply b) UART1 console output during power-up operation c) SIM Interface d) GPIOs 2. Nominal power consumption 3. VZM20Q boot 5.4.
BRING-UP AND TESTING FUNCTIONAL VERIFICATION WITH ASSEMBLED MODULE 5.4.1.2 Troubleshooting • Excessive current draw Check all VZM20Q voltage supplies. Confirm that there is no VZM20Q supply short circuits. Voltage should read according to the nominal requirement. • No current draw or current less than expected a) Check the external power supply wiring b) Check for dry joint between VZM20Q pin(s) and the power supply source. 5.4.
BRING-UP AND TESTING FUNCTIONAL VERIFICATION WITH ASSEMBLED MODULE 5.4.3 GPIOs 5.4.3.1 Procedure This section helps to confirm a GPIO’s behavior. Use the mTools command AT+SMGT. The first 32-bits triplet of parameters is a bitmask to address the GPIO, the second 32-bits triplet of parameters is the bitmask of the value to drive on the GPIO, and the third 32-bits triplet provides the expected polarity setting for the GPIO. Refer to mTools Reference Manual for more detail on this command.
BRING-UP AND TESTING FUNCTIONAL VERIFICATION WITH ASSEMBLED MODULE 5.4.4 SIM Communication 5.4.4.1 Procedure Confirmation of SIM behavior: Insert the following command to verify the SIM is working properly. Send AT commands , as described in mTools Reference Manual. Response will display +SMST=, where can be: OK: Test completed with a positive status. NO SIM: No SIM card was detected. NOK: Test completed and detected a problem. 5.4.4.
BRING-UP AND TESTING LTE RF PERFORMANCE TEST 5.5 LTE RF Performance Test The purpose of this part is to check LTE RF performances of module in non-signaling mode. This test allows validation of TX and RX path using mTools firmware. For this part, the board has to be used in FFH mode. 5.5.1 Test Configuration The test configuration is as follows: 'ĞŶĞƌĂƚŽƌ sdŽŽů ,ŽƐƚ ƉƉůŝĐĂƚŝŽŶ ^ĞƋƵĂŶƐ ĚƌŝǀĞƌ ^ĞƌǀŝĐĞ ŶĂůLJnjĞƌ hd h ZdϮ ^ĞƋƵĂŶƐ͛ DŽĚƵůĞ ^ƉůŝƚƚĞƌ Figure 5-4: RF Performance Test Configuration 1.
BRING-UP AND TESTING LTE RF PERFORMANCE TEST 5.5.2 Procedure 1. Apply the power from the local Host to the VZM20Q. 2. Launch DVTool on UART2. Guidelines for using DVTool can be found in document 4G-EZ DV Tool User Manual. a) Ensure that the external RF losses from VZM20Q to MXA / MXG are configured into DVTool b) Perform the Rx and TX Screening 3.
Hardware Test Preparation A A.1 RF Interfaces Preparation A.1.1 LTE RF Test Preparation Note: The list of the test equipment compatible with the tests is to be found in Section 1.2 of 4G-EZ DV Tool User Manual. To ensure that the RF test platform will provide the most reliable interface for testing. The following setup is proposed when measuring RF characteristics of the VZM20Q System.
RF INTERFACES PREPARATION Figure A-1: Shield Box Cavity View Figure A-2 shows the required configuration for calibration and screening. It consists of: 38 • 1 x ZN2PD2-50-S + power splitter if the signal analyzer and the signal generator are two distinct equipments. R&S® CMW500 for instance allows the use of a single bidirectional RF port and prevents the need of a power splitter.
RF INTERFACES PREPARATION Figure A-2: Configuration for Calibration and Screening MODULE INTEGRATION GUIDE PROPRIETARY SEQUANS Communications 39
Abbreviations B AC Alternate Current ACLR Adjacent Channel Leakage Ratio LTE_ANT0 Antenna 0 for LTE AT Command Modem-type commands prefixed with AT characters ATR Answer To Reset (SIM) BOM Bill Of Material cDRX Connected Discontinuous Reception CLI Command Line Interface CMOS Complementary Metal Oxide Semiconductor COM Communication CPU Central Processing Unit CS Chip Select dB decibel DC Direct Current DL Downlink DRX Discontinuous Reception DUT Device Under Test DVM Dig
EM Electromagnetic EMI Electromagnetic interference FFF Firmware From Flash module boot mode FFH Firmware From Host module boot mode FS File System FW Firmware GND Ground GNSS Global Navigation Satellite System, such as GPS, GLONASS, IRNSS, BeiDou-2tf, or GALILEO. GPIO General Purpose Input/Output GPS Global Positioning System (see GNSS) HW Hardware IC Integrated Circuit IMEI International Mobile Equipment Identity IT Interrupt LNA Low-Noise Amplifier LTE Long-Term Evolution.
PMIC Power Management Integrated Circuit PPS Protocol and Parameters Selection (SIM) PS Power Supply PS-P Power supply state. See section Operating Modes. PS-PA Power supply state. See section Operating Modes.
