C a l l i o p e P l a t f o r m - M o d u l e S P 150 Q Datasheet SEQUANS Communications 15-55 Boulevard Charles de Gaulle 92700 Colombes, France Phone. +33.1.70.72.16.00 Fax. +33.1.70.72.16.09 www.sequans.com contact@sequans.
Preface Legal Notices Copyright ©2018, SEQUANS Communications All information contained herein and disclosed by this document is confidential and the proprietary property of SEQUANS Communications, and all rights therein are expressly reserved. Acceptance of this material signifies agreement by the recipient that the information contained in this document is confidential and that it will be used solely for the purposes set forth herein.
Document Revision History Revision ii Date Product Application 01 July 2018 First edition. 02 September 2018 Second edition. 03 October 2018 Third edition. Refer to Changes in this Document on page iii.
About this Datasheet Purpose and Scope The SP150Q is a complete LTE module including base-band, RF and memory, for the design of connected consumer electronics devices, tablet and laptop computers, machine-to-machine devices, and other devices with embedded LTE connectivity on Sprint® network and its roaming partners (www.sprint.com). This document provides technical information about SP150Q LGA module. SP150Q is based on Sequans’ Calliope platform.
References [1] Core technology specifications: • 3GPP E-UTRA 21 series Release 10 (EPS) • 3GPP E-UTRA 22 series Release 10 (IMEI) • 3GPP E-UTRA 23 series Release 10 (NAS, SMS) • 3GPP E-UTRA 24 series Release 10 (NAS) • 3GPP E-UTRA 31 series Release 10 (UICC) • 3GPP E-UTRA 33 series Release 10 (security) • 3GPP E-UTRA 36 series Release 10 (RAN) • 3GPP2 C.S0015-A v1.0 (SMS) • IETF, RFC 3261, 4861, 4862, 6434 For more information, see • ftp://ftp.3gpp.org/Specs/latest/Rel-10/21_series/ • ftp://ftp.3gpp.
Documentation Conventions This section illustrates the conventions that are used in this document. General Conventions Note Important information requiring the user’s attention. Caution A condition or circumstance that may cause damage to the equipment or loss of data. Warning A condition or circumstance that may cause personal injury. Italics Italic font style denotes • emphasis of an important word; • first use of a new term; • title of a document.
Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii About this Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents 3.12 RF Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Chapter 4 Signals and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1 SP150Q Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 4.2.1 4.2.2 Notes on SP150Q Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Features 1 1.1 Features Description Sequans SP150Q module includes Calliope Category 1 baseband, a complete triple band RF front end, memory and required circuitry to meet 3GPP E-UTRA (Long Term Evolution - LTE, Release 10 set of specifications) and Sprint LTE UE specifications. For more information on the core technology specifications see the section References on page 2. The term SP150Q module refers to the hardware and the associated embedded software.
PRODUCT FEATURES FEATURES DESCRIPTION Table 1-2 on page 2 provides detail for the LTE-related features of the SP150Q. SP150Q’s ECCN and part number are detailed in the Section 3.1 ECCN and Part Number on page 9. Table 1-1: General Features • JTAG General interfaces • USIM • SPI • GPIO • USB 2.0 Host or Device • UART (x3) • SDIO Host • PCM/I2S Supported Frequency Bands • LTE Band 25 • LTE Band 26 • LTE Band 2 • LTE Band 5 • LTE Band 12 Operation voltages • Vbat (operational range from 3.3 V to 4.
PRODUCT FEATURES FEATURES DESCRIPTION Table 1-2: LTE Features (Continued) PHY • One UL and two DL transceivers • Category 1 UE • FDD • Normal and extended cyclic prefix • Modulation - DL: QPSK, 16QAM, 64QAM - UL: QPSK, 16QAM • All coding schemes corresponding to modulations • All channel coding (turbo-coding with interleaver, tail biting convolutional coding, block and repetition coding) and CRC lengths • Channels 5, 10, 15, and 20 MHz • Sounding (including in special subframes) • Control and data in spec
PRODUCT FEATURES FEATURES DESCRIPTION Table 1-2: LTE Features (Continued) RRC • MIB and all SIBs • Intra and inter-frequency measurements and handover • Up to 8 Data Radio Bearers supported • MFBI (Multi-Frequency Band Indicator).
PRODUCT FEATURES TDM-PCM INTERFACE SPECIFICATION 1.2 TDM-PCM Interface Specification The features of the SP150Q’s TDM-PCM controller include: • Support of PCM slave mode with PCM_CLK input and PCM_FS input.
2 Regulatory Approval Attention FCC-ID: 2AAGMSP150Q (limited modular approval) This above identified LTE radio module is not intended to be provided to end-users but is for installation by OEM integrators only.
REGULATORY APPROVAL change to this modular approval or a separate host approval with different FCC-ID; Compliance with Unwanted Emission Limits for Digital Device If the OEM host integration fully complies with the above described reference design and can completely inherit and rest on compliance of the existing modular approval the OEM remains still responsible to show compliance of the overall end-product with the FCC limits for unwanted conducted and radiated emissions from the digital device (unintenti
REGULATORY APPROVAL • Maximum Antenna Gain The user instructions of end-products equipped with standard external antenna connectors for the modular radio transmitter providing the option to connect other antennae than those which may or may not be bundled with the end-product must list the maximum allowed antenna gain values as derived from those given above, accounting for the cable attenuations of the actual installation.
Physical Characteristics 3 3.1 ECCN and Part Number The ECCN (Export Control Classification Number) of the SP150Q will be provided in a future revision of this document. The orderable part number of the SP150Q module is: • S150R53QRZ for Engineering samples, first revision with RF untested • S150R53QRA for Engineering samples, second revision • S150R53QRB for mass production modules compliant with specifications listed in Section 3.
PHYSICAL CHARACTERISTICS ELECTRICAL OPERATING CONDITIONS 3.2 Electrical Operating Conditions 3.2.1 Detailed Information Table 3-1: Electrical Operating Conditions for SP150Q Direction Minimum Typical Maximum VBAT1 In 3.3 V 4.42 V SIM_VCC (1.8 V or 3.0 V) Out 1.62 V 1.8 V 1.98 V 2.7 V 3.0 V 3.3 V 1V8 See note below. Out 1.71 V 1.8 V 1.89 V VCC1_PA In 3.3 V 3.8 V 4.42 V VCC2_PA In 3.3 V 3.4 V 4.
PHYSICAL CHARACTERISTICS ENVIRONMENTAL OPERATING CONDITIONS 3.3 Environmental Operating Conditions 3.3.1 Temperature Note: 3.3.2 11 The temperatures listed here are ambient.
PHYSICAL CHARACTERISTICS AUXILIARY ADC SPECIFICATION 3.4 Auxiliary ADC Specification Table 3-3: Aux ADC Specification Value Performance Specification Description AUX_ADC voltage range Typical 0 AUX_ADC resolution AUX_ADC ENOB including noise and distortion AUX_ADC tolerance AUX_ADC tolerance after calibration. Please contact Sequans’ technical support for details on AUX_ADC calibration.
PHYSICAL CHARACTERISTICS I/O CHARACTERISTICS 3.6 I/O Characteristics The voltage and current characteristics of the various IO pads of the SP150Q versus IO bank supply voltage are illustrated in the tables below. Caution: Note that the Voh values in the tables below do not apply to GPIOs configured in open drain mode. GPIOs can be individually configured in open drain mode. When in open drain mode they either drive the line to Vol, or leave it floating, to be pulled up by an external pull-up resistance.
PHYSICAL CHARACTERISTICS I/O CHARACTERISTICS • The Maximum values for Iol and Ioh represent the maximal values for the pad type. They are provided for information only. Table 3-5: DC Characteristics for Digital IOs, Voltage 1.8 V Parameter Drive Strength Min. Nom. Max. Unit VIL Input Low Voltage -0.3 0.63 V VIH Input High Voltage 1.17 3.6 V VT Threshold Point 0.79 0.87 0.94 V VT+ Schmitt Trigger Low to High Threshold Point 1 1.12 1.
PHYSICAL CHARACTERISTICS I/O CHARACTERISTICS Table 3-5: DC Characteristics for Digital IOs, Voltage 1.8 V (Continued) Parameter Drive Strength RPD Pull-down Resistor Min. Nom. Max. 52 90 167 kOhm 0.45 V VOL Output Low Voltage 1.35 VOH Output High Voltage IOL Low Level Output Current at VOL(max) IOH High Level Output Current at VOH(max) Unit V 2 mA 1.2 2.2 3.6 mA 4 mA 2.3 4.3 7.1 mA 8 mA 4.6 8.6 14.3 mA 2 mA 1.0 2.4 4.6 mA 4 mA 2.0 4.7 9.2 mA 8 mA 4.0 9.4 18.
PHYSICAL CHARACTERISTICS I/O CHARACTERISTICS Table 3-6: DC Characteristics for Digital IOs, Voltage 1.8 V - DDR IO Pins (BIDIR_DDR Type) (Continued) Parameter Drive Strength VOH Output High Voltage (IOH=-0.1mA) Min. Nom. Max. 0.9 * VDDQ IOL Low Level Output Current at VOL(max) IOH High Level Output Current at VOH(max) Unit V 2 mA 2.00 mA 4 mA 4.00 mA 8 mA 8.00 mA 10 mA 10.00 mA 2 mA 2.00 mA 4 mA 4.00 mA 8 mA 8.00 mA 10 mA 10.
PHYSICAL CHARACTERISTICS PACKAGE DESCRIPTION 3.7 Package Description 3.7.1 Module Footprint The dimensions marked in Figure 3-1are listed in Table 3-8. Figure 3-1: Top and Side View of the SP150Q Table 3-8: SP150Q Outline Dimensions Mark Minimum (mm) Nominal (mm) Maximum (mm) A 22.43 22.53 22.63 B 22.56 22.66 22.76 C Not available 1.47 1.55 D Not available Not available 0.
PHYSICAL CHARACTERISTICS PACKAGE DESCRIPTION Figure 3-2: Bottom Side View of the SP150Q Pads Attention: T1 to T30 pads are used as both GND and thermal drops. Table 3-9: SP150Q Dimensions and Tolerances Mark Dimension and tolerance (mm) L 22.53 ± 0.1 W 22.66 ± 0.1 A1 12 ± 1.0 A2 4.125 ± 0.5 A3 10.8 ± 1.0 A4 4.725 ± 0.5 A5 0.6 ± 0.
PHYSICAL CHARACTERISTICS PACKAGE DESCRIPTION Table 3-9: SP150Q Dimensions and Tolerances (Continued) Mark Dimension and tolerance (mm) A6 1.2 ± 0.1 A7 0.6 ± 0.05 B1 0.9 ± 0.1 B2 0.325 ± 0.05 B3 0.6 ± 0.05 B4 19.2 ± 0.2 B5 18 ± 0.2 B6 1.075 ± 0.1 B7 1.675 ± 0.15 C1 6.125 ± 0.5 C2 6.8 ± 0.5 C3 1.2 ± 0.01 C4 0.5 ± 0.05 D1 0.5 ± 0.05 D2 0.9 ± 0.1 D3 7 ± 0.5 D4 6.725 ± 0.5 D5 18.9 ± 0.2 D6 15.9 ± 0.
PHYSICAL CHARACTERISTICS PACKAGE DESCRIPTION 3.7.2 Marking Information Note: The marking information can be either laser marking or high temperature label. Figure 3-3: SP150Q Marking Description Table 3-10: Marking Details Symbol Description a Sequans’ logo b RoHS logo c S/N 2D barcode d Model: SP150Q e IMEI: 2D barcode f Calliope logo g FCC ID: Will be provided in a future revision of this document.
PHYSICAL CHARACTERISTICS PACKAGE DESCRIPTION Table 3-10: Marking Details (Continued) Symbol Description i S/N: SPAYYMMDDNNNNSSS (16 digits) SPA: is immovable (3 digits) YYMMDD: Manufacturing Date (YY:Year, MM:Month, DD:Day) NNNN: panel counter (from0001~9999) SSS: Piece location on panel (from001~020) j Made in PRC 21 PROPRIETARY SEQUANS Communications SP150Q DATASHEET
PHYSICAL CHARACTERISTICS PACKING INFORMATION 3.8 Packing Information The SP150Q is delivered in Tape-and-Reel. One reel can hold up to 1000 (one thousand) pieces. Each reel is included in a box, and a carton can contain three boxes. This is represented on Figure 3-4.
PHYSICAL CHARACTERISTICS STORAGE CONDITIONS 3.9 Storage Conditions 1. Calculated shelf life in sealed bag : 12 months at < 40°C and < 90% RH. 2. After the moisture barrier bag (MBB) is opened, devices that will be subjected to reflow solder or other high temperature process must be: a) mounted within 168 hours under factory conditions = 30°C/60%RH, or b) Stored as per J-STD-033. 3.
PHYSICAL CHARACTERISTICS MOUNTING CONSIDERATIONS 3.10 Mounting Considerations This section provides reflow information. Figure 3-5: Reflow Profile The SP150Q can support up to 3 reflows with 250°C maximum. Table 3-11: Reflow Parameters Parameter Peak package body temperature Setting Will be provided in a future revision of the document.
PHYSICAL CHARACTERISTICS COMPONENT RELIABILITY 3.11 Component Reliability Table 3-12: SP150Q Reliability Figures Test Item Test Method Test Conditions Test Result ESD - Direct Discharge (ANT GND) IEC 61000-4-2 M.2 board. See detail inTable 3-13 below. PASS. See details inTable 3-14 and Table 3-15 below. ESD Direct Discharge HBM MIL-STD-883J / Method 3015.8 ±500V to ±2000V with 500V steps MM ANSI/ESD S5.
PHYSICAL CHARACTERISTICS COMPONENT RELIABILITY Table 3-13: SP150Q ESD Test Conditions (IEC 61000-4-2 Standard) Test Parameter Description Discharge Voltage Direct Discharge Indirect Discharge Air 8 kV Contact 4 kV HCP 4 kV VCP 4 kV Polarity Positive / Negative Discharge Impedance 330 Ohm Discharge Capacitance 150 pF Number of Discharge Minimum 10 times at all test point for Air condition. Minimum 25 times at all test point for Contact condition.
PHYSICAL CHARACTERISTICS RF PERFORMANCE 3.12 RF Performance This section presents the module’s performance in LTE Band 25, Band 26, Band 2, Band 5 and Band 12. Note: The values presented in Table 3-16 and Table 3-17 are currently estimated performance results. They will be updated with measures done on parts S150R53QRB. Note: UE complies with 3GPP 36.521-1 Table 6.2.2.5-1: UE Power Class test requirements, including 0.7 dB for measurement errors.
PHYSICAL CHARACTERISTICS RF PERFORMANCE The results for the typical sensitivity levels are measured under the following test conditions: SP150Q DATASHEET • 2 receive paths • Tx power @ 23 dBm. UL allocation: 20RB, offset 5 for Band 12, and full allocation for Band 25/2 and Band 26/5.
Signals and Pins 4 4.1 SP150Q Pinout Table 4-1 lists the function and main information for SP150Q pads. The pads listed in Table 4-2 are connected to ground. Refer also to Figure 4-1 that represents the typical implementation for UART hardware flow control. Table 4-1: Pinout Pad # Pad Name Alternate Function Comments 2 NETWORK_LED 3 1V8 4 USB_EXT_VBUS_VLD WAKE_2 In 5 FFF_FFH GPIO_18 In 6 ACTIVITY_LED GPO_2 Out 7 MODULE_ON_IND GPIO_19 Out Module “ON” Indicator.
SIGNALS AND PINS SP150Q PINOUT Table 4-1: Pinout (Continued) Pad # Pad Name Alternate Function Direction (HW) Comments 14 SIM_CLK Out 15 USB_D- In/Out 16 SIM_DETECT In 17 SIM_IO In/Out 18 SIM_VCC Out 19 SDIO_HOST_D2 GPO_6 In / Out 21 SDIO_HOST_CLK GPO_9 Out 23 SDIO_HOST_CMD GPO_8 In/Out 25 SDIO_HOST_D1 GPO_5, WAKE_3 In / Out 27 SDIO_HOST_D0 GPO_4 In / Out 29 SDIO_HOST_D3 GPO_7 In / Out 35 PCM_RXD GPIO_10 In PCM receive data. See details in Section 4.2.
SIGNALS AND PINS SP150Q PINOUT Table 4-1: Pinout (Continued) Pad # Pad Name Alternate Function Direction (HW) Comments 49 JTAG_TRSTN In 50 JTAG_TMS In 51 JTAG_TDI In 52 JTAG_TCK In 54 ANT0 In / Out 56 UART0_SOUT 57 AUX_ADC 58 UART0_SIN GPIO_34 In 59 SPI_SDI GPIO_44 Out 60 SPI_CS_N_1 GPIO_47 Out 61 SPI_CLK GPIO_43 Out 67 SPI_SDO GPIO_45 In Data from SPI device to SP150Q module.
SIGNALS AND PINS SP150Q PINOUT Table 4-1: Pinout (Continued) Pad # Pad Name Alternate Function UART3_CTS 84 SQN3223_GPIO_41 In / Out 85 SQN3223_GPIO_39 In / Out 88 SQN3223_GPIO_24 In / Out 89 SQN3223_GPIO_25 In / Out 90 SQN3223_GPIO_40 In / Out 91 SQN3223_GPIO_26 In / Out 92 SQN3223_GPIO_20 In / Out 93 SQN3223_GPIO_23 In / Out 94 SQN3223_GPIO_22 In / Out 95 SQN3223_GPIO_21 In / Out 96 WAKE_1 97 VCC1_PA In 98 VCC2_PA In 99 VCC2_PA In 100 DNC Do Not Connect, res
SIGNALS AND PINS SP150Q PINOUT Table 4-1: Pinout (Continued) Pad # 108 Pad Name Alternate Function VBAT1 Direction (HW) Comments In Table 4-2: Ground Pads Pad # Pad Name Comment 1 20 22 24 26 28 30 31 32 33 34 42 43 45 46 53 55 62 63 64 65 66 68 69 70 71 72 73 74 86 87 GND All GND pads shall be connected to the same copper. T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 GND All GND pads shall be connected to the same copper.
SIGNALS AND PINS NOTES ON SP150Q SIGNALS 4.2 Notes on SP150Q Signals 4.2.1 High-Speed UARTs Flow Control Signals SP150Q DATASHEET • UART2_CTS: UART2 flow control, Clear-To-Send, active low, of the SP150Q. To be connected to the RTS of the remote UART device. Provision a 1 kOhm pull-down on CTS pin when flowcontrol is not used. If it is connected to an external component (like a RS232 driver), the user should make sure that this component will present a low level to the SP150Q. See Figure 4-1.
SIGNALS AND PINS NOTES ON SP150Q SIGNALS Figure 4-1 represents the typical implementation for the hardware flowcontrol. ^ĞƋƵĂŶƐ ^/ ZĞŵŽƚĞ ĞǀŝĐĞ ^/E Zy ^Khd dy d^ d^ Zd^ Zd^ 'E 'E 'E 'E Figure 4-1: UART Flow Control Note: 35 High-Speed UART can be used as low-speed UART, given a specific software registers configuration and the setting of the CTS signal to 0. Please contact Sequans customer support for details.
SIGNALS AND PINS NOTES ON SP150Q SIGNALS 4.2.2 I2S/PCM Interface Signals • PCM_RXD: PCM receive data. PCM data block is 8-bits or 16-bits. Only one data block is received per frame. Receive time-slot offset is programmable by using the RX_SLOT register. For instance, if RX_SLOT=5, then the 8-bit data block is received from time-slot #5 to #12. Bit-order is configurable. • PCM_CLK: PCM clock input, from 128 kHz to 8192 kHz Sequans PCM interface takes PCM_CLK as an input in both master and slave modes.
SIGNALS AND PINS POWER SUPPLIES ENVIRONMENT 4.3 Power Supplies Environment Figure 4-3 illustrates the connections between the power supplies of the SP150Q. W ^WϭϱϬY s dϭ s d WD/ s ϮͺW W s ϭͺW Figure 4-2: SP150Q Power Supplies Diagram 4.4 Power-up Sequence Note: After each module boot, the modem will issue +SYSSTART URC. The following timing requirement applies to the signals VBAT1, MODULE_PWR_EN and RESET_N. It must be respected for proper SP150Q’s behavior.
SIGNALS AND PINS POWER-UP SEQUENCE s dϭ DK h> ͺWtZͺ E ƚƐϭ Z ^ dͺE tĂƌŵ ƐƚĂƌƚ Figure 4-4: VBAT1, MODULE_PWR_EN and RESET_N Signals Timing Requirement for Warm Start s dϭ DK h> ͺWtZͺ E ƚŚϭ Z ^ dͺE ZĞƐĞƚ ĐLJĐůĞ Figure 4-5: VBAT1, MODULE_PWR_EN and RESET_N Signals Timing Requirement for Reset Cycle The timing minimum values are listed in Table 4-3.
SIGNALS AND PINS LOW POWER MODE 4.5 Low Power Mode The SP150Q integrates several mechanisms to support power consumption optimization during operation and during low-power mode. SP150Q can be woken from low power mode through: • USB resume signaling (when the host supports it) • USB plug / unplug event (reported by the signal USB_EXT_VBUSVLD) • SDIO interrupt on SDIO_HOST_D1 • Two dedicated input signal WAKE_0 and WAKE_1 Note: Wake from activity on the UARTx interfaces is not possible directly.
SIGNALS AND PINS LOW POWER MODE The signals involved in the low-power mode of the SP150Q are listed in Table 4-4. Note: Each signal’s pull (up or down) is determined by register. It can be modified by software. Table 4-4: Signals Related to Low-Power Mode Signal Name Drive Description SDIO_HOST_D1 Open-drain Possible wakeup by SDIO Host activity. See important note below. USB_EXT_VBUSVLD Open-drain Possible wakeup by USB activity.
SIGNALS AND PINS LOW POWER MODE Important Notes 1. SDIO_HOST_D1 This signal is muxed with WAKE_3, which is transition configurable. To trigger an interrupt, the designer must map WAKE_3 signal to a dedicated GPIO. The pulse on GPIO must be long enough (typically 8 ms) to be detected in any mode. This feature might not be activated in the software release preloaded in the module. Please contact Sequans technical support if you intend to use it. 2.
A Acronyms Acronym Definition ADC Analog to Digital Converter CPU Central Processing Unit DL Downlink ECCN Export Control Classification Number ECM Ethernet Control Model, USB interface EEM Ethernet Emulation Model, USB interface ENOB Effective number of bits ESD Electro-static discharge ETSI European Telecommunications Standard Institute FFF Firmware from Flash. Specific load and boot mode for the module. FFH Firmware from Host. Specific load and boot mode for the module.
Acronym Definition IMS Instant Messaging Service IP Internet Protocol JTAG Joint Test Action Group LGA Large Grid Array LTE Long Term Evolution, or 4G. Standard is developed by the 3GPP www.3gpp.org.
Acronym Definition UL Uplink USB Universal Serial Bus VCP Vertical Coupling Plane SP150Q DATASHEET PROPRIETARY SEQUANS Communications 44