21-S3-C9228/P9228-112002 USER'S MANUAL S3C9228/P9228 8-Bit CMOS Microcontroller Revision 1
S3C9228/P9228 8-BIT CMOS MICROCONTROLLERS USER'S MANUAL Revision 1
Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
Preface The S3C9228/P9228 Microcontrollers User's Manual is designed for application designers and programmers who are using the S3C9228/P9228 microcontrollers for application development. It is organized in two main parts: Part I Programming Model Part II Hardware Descriptions Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure.
Table of Contents Part I — Programming Model Chapter 1 Product Overview SAM88RCRI Product Family ................................................................................................................... 1-1 S3C9228/P9228 Microcontroller .............................................................................................................. 1-1 OTP.................................................................................................................................................
Table of Contents (Continued) Chapter 4 Control Registers Overview ................................................................................................................................................. 4-1 Chapter 5 Interrupt Structure Overview ................................................................................................................................................. 5-1 Interrupt Processing Control Points..................................................................
Table of Contents (Continued) Part II — Hardware Descriptions Chapter 7 Clock Circuit Overview ................................................................................................................................................. 7-1 System Clock Circuit ....................................................................................................................... 7-1 CPU Clock Notation .....................................................................................................
Table of Contents (Continued) Chapter 11 Timer 1 One 16-Bit Timer Mode (Timer 1) ............................................................................................................ 11-1 Overview ......................................................................................................................................... 11-1 Function Description........................................................................................................................
Table of Contents (Concluded) Chapter 16 Electrical Data Overview ................................................................................................................................................. 16-1 Chapter 17 Mechanical Data Overview ................................................................................................................................................. 17-1 Chapter 18 S3P9228 OTP Overview ....................................................................
List of Figures Figure Number Title Page Number 1-1 1-2 1-3 1-4 1-5 1-7 1-8 1-9 1-10 1-11 1-12 Block Diagram.................................................................................................................... 1-3 S3C9228 44-QFP Pin Assignments .................................................................................... 1-4 S3C9228 42-SDIP Pin Assignments ................................................................................... 1-5 Pin Circuit Type B ....................
List of Figures (Continued) Figure Number Title Page Number 5-1 5-2 5-3 S3C9-Series Interrupt Type ................................................................................................ 5-1 Interrupt Function Diagram ................................................................................................. 5-2 S3C9228/P9228 Interrupt Structure .................................................................................... 5-5 6-1 System Flags Register (FLAGS).....................
List of Figures (Continued) Figure Number Title Page Number 10-1 10-2 Basic Timer Control Register (BTCON) .............................................................................. 10-2 Basic Timer Block Diagram ................................................................................................ 10-4 11-1 11-2 11-3 11-4 11-5 11-6 Timer 1 Control Register (TACON).....................................................................................
List of Figures (Concluded) Figure Number Title Page Number 16-1 16-2 16-3 16-4 16-5 16-6 16-7 16-8 Stop Mode Release Timing When Initiated by an External Interrupt.................................... 16-5 Stop Mode Release Timing When Initiated by a RESET..................................................... 16-6 Input Timing for External Interrupts..................................................................................... 16-8 Input Timing for RESET............................................
List of Tables Table Number Title Page Number 1-1 Pin Descriptions ................................................................................................................. 1-6 6-1 6-2 6-3 6-4 6-5 6-6 Instruction Group Summary................................................................................................ 6-2 Flag Notation Conventions ................................................................................................. 6-5 Instruction Set Symbols....................
List of Programming Tips Description Page Number Chapter 2: Address Spaces Addressing the Common Working Register Area ..................................................................................... 2-4 Standard Stack Operations Using PUSH and POP .................................................................................. 2-6 Chapter 5: Interrupt Structure How to clear an interrupt pending bit.....................................................................................................
List of Register Descriptions Register Identifier ADCON BTCON CLKCON FLAGS INTPND1 INTPND2 LMOD LPOT OSSCON P0CON P0INT P0PUR P0EDGE P1CON P1INT P1PUR P1EDGE P2CON P2PUR P3CON P3INT P3PUR P3EDGE P4CONH P4CONL P5CONH P5CONL P6CON SIOCON STPCON SYM TACON TBCON WTCON Full Register Name Page Number A/D Converter Control Register.............................................................................. 4-5 Basic Timer Control Register .......................................................................
List of Instruction Descriptions Instruction Mnemonic ADC ADD AND CALL CCF CLR COM CP DEC DI EI IDLE INC IRET JP JR LD LDC/LDE LDCD/LDED LDCI/LDEI NOP OR POP PUSH RCF RET RL RLC RR RRC SBC SCF SRA STOP SUB TCM TM XOR Full Instruction Name Page Number Add With Carry ...................................................................................................... 6-11 Add ........................................................................................................................
S3C9228/P9228 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device. A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements.
PRODUCT OVERVIEW S3C9228/P9228 FEATURES CPU LCD Controller/Driver • SAM88RCRI CPU core • 16 segments and 8 common terminals Memory • • 3, 4, and 8 common selectable Internal resistor circuit for LCD bias • • 8192 × 8 bits program memory (ROM) 264 × 8 bits data memory (RAM) (Including LCD data memory) Instruction Set • 41 instructions • Idle and Stop instructions added for power-down modes 8-bit Serial I/O Interface • 8-bit transmit/receive mode • 8-bit receive mode • LSB-first or MSB-fi
S3C9228/P9228 PRODUCT OVERVIEW BLOCK DIAGRAM TAOUT/ P0.0 T1CLK/ P0.1 8-Bit Timer/ CounterA 8-Bit Timer/ CounterB P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P0.4 P0.5 P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT P2.0/SCK/SEG1 P2.1/SO/SEG0 P2.2/SI P2.3 RESET X IN XT IN XOUT XT OUT 16-Bit Timer/ Counter1 I/O Port 0 Watchdog Timer Basic Timer Port I/O and Interrupt Control I/O Port 1 SAM88RCRI CPU Watch Timer LCD Driver/ Controller COM0-COM3/P6.3-P6.0 COM4-COM7/ SEG19-SEG16/P5.
PRODUCT OVERVIEW S3C9228/P9228 44 43 42 41 40 39 38 37 36 35 34 P0.5 P0.4 P0.3/BUZ/INT P0.2/INT P0.1/T1CLK/INT P0.0/TAOUT/INT COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 S3C9228 (44-QFP) 33 32 31 30 29 28 27 26 25 24 23 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4 RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.0/SCK SEG2/P3.1/INTP SEG3/P3.0/INTP SEG4/P4.0 SEG5/P4.
S3C9228/P9228 PRODUCT OVERVIEW (42-SDIP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C9228 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT VDD VSS XOUT XIN TEST XTIN XTOUT RESET P2.3 P2.2/SI SEG0/P2.1/SO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.
PRODUCT OVERVIEW S3C9228/P9228 PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins P0.0 P0.1 P0.2 P0.3 I/O 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. E-4 39(3) 40(4) 41(5) 42(6) TAOUT/INT T1CLK/INT INT BUZ/INT P0.4-P0.5 O 1-bit programmable output port. C 43-44 P1.0 P1.1 P1.2 P1.3 I/O 1-bit programmable I/O port.
S3C9228/P9228 PRODUCT OVERVIEW Table 1-1. Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins – VDD, VSS – Power input pins for internal power block – 5,6(11,12) XOUT, XIN – Main oscillator pins for main clock – 7,8(13,14) XTOUT, XTIN – Sub oscillator pins for sub clock – 11,10(17,16) – TEST – Chip test input pin Hold GND when the device is operating – 9(15) – RESET I RESET signal input pin.
PRODUCT OVERVIEW S3C9228/P9228 PIN CIRCUIT DIAGRAMS VDD Pull-Up Resistor RESET Noise Filter Figure 1-4. Pin Circuit Type B VDD Data Output Output Disable VSS Figure 1-5.
S3C9228/P9228 PRODUCT OVERVIEW VDD VDD Pull-up Resistor Pull-up Enable Open-Drain I/O Data Output Disable External Interrupt Input Figure 1-7. Pin Circuit Type E-4 VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data Output Disable Circuit Type E I/O ADEN ADSELECT Data To ADC Figure 1-8.
PRODUCT OVERVIEW S3C9228/P9228 VLC1 VLC2 VLC3 SEG/COM Out Output Disable VLC4 VLC5 VSS Figure 1-9.
S3C9228/P9228 PRODUCT OVERVIEW VDD Pull-up Resistor VDD Pull-up Enable Open-Drain EN Data I/O LCD Out EN COM/SEG Output Disable Circuit Type H-23 Figure 1-10. Pin Circuit Type H-32 VDD VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data I/O LCD Out EN COM/SEG Output Disable Circuit Type H-23 Figure 1-11.
PRODUCT OVERVIEW S3C9228/P9228 VDD VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data I/O Port Enable (LMOD.5) LCD Out EN COM/SEG Output Disable Circuit Type H-23 Figure 1-12.
S3C9228/P9228 2 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C9228/P9228 microcontroller has three kinds of address space: — Program memory (ROM) — Internal register file — LCD display register file A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file.
ADDRESS SPACES S3C9228/P9228 PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H–0001H) are an interrupt vector address. The program reset address in the ROM is 0100H. (Decimal) 8,192 (Hex) 1FFFH 8K bytes Internal Program Memory Area 256 Program Start 2 1 0 0100H 0002H Interrupt Vector 0001H 0000H Figure 2-1.
S3C9228/P9228 ADDRESS SPACES REGISTER ARCHITECTURE The upper 72 bytes of the S3C9228/P9228's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 184 bytes of internal register file (00H–B7H) is called the general purpose register space.
ADDRESS SPACES S3C9228/P9228 COMMON WORKING REGISTER AREA (C0H–CFH) The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file.
S3C9228/P9228 ADDRESS SPACES SYSTEM STACK S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file. STACK OPERATIONS Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction.
ADDRESS SPACES S3C9228/P9228 + PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SP,#0B8H ; SP ← B8H (Normally, the SP is set to 0B8H by the ; initialization routine) SYM WTCON 20H R3 ; ; ; ; Stack address 0B7H ← Stack address 0B6H ← Stack address 0B5H ← Stack address 0B4H ← R3 20H WTCON SYM ; ; ; ; R3 ← Stack address 0B4H 20H ← Stack address 0B5H WTCON ← S
S3C9228/P9228 3 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.
ADDRESSING MODES S3C9228/P9228 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2).
S3C9228/P9228 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register.
ADDRESSING MODES S3C9228/P9228 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory dst OPCODE REGISTER PAIR Points to Rigister Pair Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in Instruction OPERAND Figure 3-4.
S3C9228/P9228 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File CFH Program Memory 4-Bit Working Register Address dst OPCODE Sample Instruction: OR src R6, @R2 4 LSBs . . . . OPERAND Point to the Woking Register (1 of 16) Value used in Instruction C0H OPERAND Figure 3-5.
ADDRESSING MODES S3C9228/P9228 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File CFH . . . .
S3C9228/P9228 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of –128 to +127.
ADDRESSING MODES S3C9228/P9228 INDEXED ADDRESSING MODE (Continued) Register File Program Memory 4-Bit Working Register Address XS (OFFSET) dst src OPCODE NEXT 3 Bits Point to Working Register Pair (1 of 8) Register Pair 16-Bit address added to offset LSB Selects + 8-Bits 16-Bits Program Memory or Data Memory 16-Bits OPERAND Value used in Instruction Sample Instructions: LDC R4, #04H[RR2] LDE R4,#04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4.
S3C9228/P9228 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Program Memory 4-Bit Working Register Address XLH (OFFSET) XLL (OFFSET) dst src OPCODE Register File NEXT 3 Bits Register Pair Point to Working Register Pair (1 of 8) 16-Bit address added to offset LSB Selects + 8-Bits 16-Bits Program Memory or Data Memory 16-Bits OPERAND Value used in Instruction Sample Instructions: LDC R4, #1000H[RR2] #1000H) LDE R4, #1000H[RR2] ; The values in the program address (RR2 + are loaded into
ADDRESSING MODES S3C9228/P9228 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
S3C9228/P9228 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address Figure 3-11.
ADDRESSING MODES S3C9228/P9228 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR.
S3C9228/P9228 4 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1.
CONTROL REGISTERS S3C9228/P9228 Table 4-1.
S3C9228/P9228 CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Page 0) Register Name Mnemonic Address (Page 0) Decimal R/W Hex Locations D8H-B9H are not mapped.
CONTROL REGISTERS S3C9228/P9228 Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register bit or bit function Full Register name mnemonic Register address (hexadecimal) D5H FLAGS - System Flags Register Bit Identifier RESET Value Read/Write .7 .7 .6 .5 .4 .3 .2 .1 .0 x R/W x R/W x R/W x R/W x R/W x R/W 0 R/W 0 R/W Carry Flag (C) .
S3C9228/P9228 CONTROL REGISTERS ADCON — A/D Converter Control Register D0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R R/W R/W R/W .7-.6 Not used for the S3C9228/P9228 .5-.4 A/D Input Pin Selection Bits .3 .2-.1 .0 0 0 AD0 (P1.0) 0 1 AD1 (P1.1) 1 0 AD2 (P1.2) 1 1 AD3 (P1.
CONTROL REGISTERS S3C9228/P9228 BTCON — Basic Timer Control Register DCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.4 Watchdog Timer Enable Bits 1 0 1 0 Any other value .3-.2 .1 .
S3C9228/P9228 CONTROL REGISTERS CLKCON — System Clock Control Register D4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6-.5 Oscillator IRQ Wake-up Function Bit 0 Enable IRQ for main or sub oscillator wake-up in power down mode 1 Disable IRQ for main or sub oscillator wake-up in power down mode Bits 6-5 0 .4-.3 .2-.
CONTROL REGISTERS S3C9228/P9228 FLAGS — System Flags Register D5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value x x x x – – – – R/W R/W R/W R/W – – – – Read/Write .7 Carry Flag (C) 0 .6 .5 .4 .3-.
S3C9228/P9228 CONTROL REGISTERS INTPND1 — Interrupt Pending Register 1 D6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 .3 P1.3's Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) P1.2's Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) P1.
CONTROL REGISTERS S3C9228/P9228 INTPND2 — Interrupt Pending Register 2 D7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R/W R/W R/W R/W .7-.6 Not used for S3C9228/P9228 .5 P3.1 (INTP) Interrupt Pending Bit .4 .3 .2 .1 .0 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) P3.
S3C9228/P9228 CONTROL REGISTERS LMOD — LCD Mode Control Register FEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – 0 0 0 0 0 0 0 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6 COM Pins High Impedance Control Bit .5 .4 .3-.2 .1-.
CONTROL REGISTERS S3C9228/P9228 LPOT — LCD Port Control Register D8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – 0 0 0 0 0 0 0 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6-.4 SEG4-SEG19 and COM0-COM3 Selection Bit .3 .2 .1 .0 SEG4-7 SEG8-11 SEG12-15 SEG16-19/ COM7-COM4 COM0-3 P4.0-P4.3 P4.4-P4.7 P5.0-P5.3 P5.4-P5.7 P6.0-P6.
S3C9228/P9228 CONTROL REGISTERS OSCCON — Oscillator Control Register D3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 – 0 Read/Write – – – – R/W R/W – R/W .7-.4 Not used for S3C9228/P9228 .3 Main Oscillator Control Bit .2 0 Main oscillator RUN 1 Main oscillator STOP Sub Oscillator Control Bit 0 Sub oscillator RUN 1 Sub oscillator STOP .1 Not used for S3C9228/P9228 .
CONTROL REGISTERS S3C9228/P9228 P0CON – Port 0 Control Register EBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-14 P0.3/BUZ/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (BUZ output) P0.
S3C9228/P9228 CONTROL REGISTERS P0INT –Port 0 Interrupt Enable Register EDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Enable Bit .2 .1 .0 0 Disable interrupt 1 Enable interrupt P0.2's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt P0.1's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt P0.
CONTROL REGISTERS S3C9228/P9228 P0PUR –Port 0 Pull-up Resistors Enable Register ECH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Pull-up Resistor Enable Bit .2 .1 .0 4-16 0 Disable pull-up resistor 1 Enable pull-up resistor P0.2's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P0.
S3C9228/P9228 CONTROL REGISTERS P0EDGE –Port 0 Interrupt Edge Selection Register EEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Edge Setting Bit .2 .1 .0 0 Falling edge interrupt 1 Rising edge interrupt P0.2's Interrupt State Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt P0.
CONTROL REGISTERS S3C9228/P9228 P1CON – Port 1 Control Register EFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-18 P1.3/AD3/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (ADC mode) P1.
S3C9228/P9228 CONTROL REGISTERS P1INT –Port 1 Interrupt Enable Register F1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Enable Bit .2 .1 .0 0 Disable interrupt 1 Enable interrupt P1.2's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt P1.1's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt P1.
CONTROL REGISTERS S3C9228/P9228 P1PUR –Port 1 Pull-up Resistors Enable Register F0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Pull-up Resistor Enable Bit .2 .1 .0 4-20 0 Disable pull-up resistor 1 Enable pull-up resistor P1.2's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P1.
S3C9228/P9228 CONTROL REGISTERS P1EDGE –Port 1 Interrupt Edge Selection Register F2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Edge Setting Bit .2 .1 .0 0 Falling edge interrupt 1 Rising edge interrupt P1.2's Interrupt State Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt P1.
CONTROL REGISTERS S3C9228/P9228 P2CON – Port 2 Control Register F3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-22 P2.3 Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not available P2.
S3C9228/P9228 CONTROL REGISTERS P2PUR –Port 2 Pull-up Resistors Enable Register F4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P2.3's Pull-up Resistor Enable Bit .2 .1 .0 0 Disable pull-up resistor 1 Enable pull-up resistor P2.2's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P2.
CONTROL REGISTERS S3C9228/P9228 P3CON – Port 3 Control Register F5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3-.2 P3.1/SEG2/INTP Configuration Bits .1-.0 4-24 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not available P3.
S3C9228/P9228 CONTROL REGISTERS P3INT –Port 3 Interrupt Enable Register F7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Interrupt Enable Bit .0 0 Disable interrupt 1 Enable interrupt P3.
CONTROL REGISTERS S3C9228/P9228 P3PUR –Port 3 Pull-up Resistors Enable Register F6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Pull-up Resistor Enable Bit .0 4-26 0 Disable pull-up resistor 1 Enable pull-up resistor P3.
S3C9228/P9228 CONTROL REGISTERS P3EDGE –Port 3 Interrupt Edge Selection Register F8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W .7-.4 Not used for S3C9228/P9228 .1 P3.1's Interrupt State Setting Bit .0 0 Falling edge interrupt 1 Rising edge interrupt P3.
CONTROL REGISTERS S3C9228/P9228 P4CONH – Port 4 Control Register High Byte F9H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-28 P4.7/SEG11 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P4.
S3C9228/P9228 CONTROL REGISTERS P4CONL–Port 4 Control Register Low Byte FAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 P4.3/SEG7 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P4.
CONTROL REGISTERS S3C9228/P9228 P5CONH – Port 5 Control Register High Byte FBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-30 P5.7/SEG19/COM4 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P5.
S3C9228/P9228 CONTROL REGISTERS P5CONL – Port 5 Control Register Low Byte FCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 P5.3/SEG15 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P5.
CONTROL REGISTERS S3C9228/P9228 P6CON – Port 6 Control Register High Byte FDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-32 P6.3/COM0 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P6.
S3C9228/P9228 CONTROL REGISTERS SIOCON — SIO Control Register E1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W R/W – Read/Write .7 .6 .5 .4 .3 .2 .1 .0 SIO Shift Clock Selection Bit 0 Internal clock (P.
CONTROL REGISTERS S3C9228/P9228 STPCON – Stop Control Register E0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 Stop Control Bits 1 0 1 0 0 Other values 1 0 1 Enable Stop instruction Disable Stop instruction NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP instruction will not execute.
S3C9228/P9228 CONTROL REGISTERS SYM — System Mode Register DFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 Global Interrupt Enable Bit .2-.
CONTROL REGISTERS S3C9228/P9228 TACON — Timer 1/A Control Register BBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W R/W – Read/Write .7 .6-.4 .3 .2 .1 .
S3C9228/P9228 CONTROL REGISTERS TBCON — Timer B Control Register BAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – 0 0 0 0 0 0 – Read/Write – R/W R/W R/W R/W R/W R/W – .7 Not used for S3C9228/P9228 .6-.4 Timer B Clock Selection Bits .3 .2 .1 .
CONTROL REGISTERS S3C9228/P9228 WTCON — Watch Timer Control Register DAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W R/W – Read/Write .7 .6 .5-.4 .3-.2 .1 .0 4-38 Watch Timer Clock Selection Bit 0 Select main clock divided by 27 (fx/128) 1 Select sub clock (fxt) Watch Timer Interrupt Enable Bit 0 Disable watch timer interrupt 1 Enable watch timer interrupt Buzzer Signal Selection Bits 0 0 0.
S3C9228/P9228 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H. VECTOR SOURCES S1 0000H 0001H S2 S3 Sn NOTES: 1. The SAM88RCRI interrupt has only one vector address (0000H-0001H). 2. The number of Sn value is expandable. Figure 5-1.
INTERRUPT STRUCTURE S3C9228/P9228 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine.
S3C9228/P9228 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source's pending flag is cleared to "0" by software. 4. Interrupt priority must be determined by software polling method.
INTERRUPT STRUCTURE S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: — Timer 1/A interrupt — Timer B interrupt — SIO interrupt — Watch Timer interrupt — Four external interrupts for port 0 — Four external interrupts for port 1 — Two external interrupts for port 3 5-4 S3C9228/P9228
S3C9228/P9228 INTERRUPT STRUCTURE Vector Enable/Disable Pending Sources INTPND1.0 P0.0 External Interript INTPND1.1 P0.1 External Interript INTPND1.2 P0.2 External Interript INTPND1.3 P0.3 External Interript INTPND1.4 P1.0 External Interript INTPND1.5 P1.1 External Interript INTPND1.6 P1.2 External Interript INTPND1.7 P1.3 External Interrupt INTPND2.0 Timer 1/A Interrupt INTPND2.1 Timer B Interrupt INTPND2.2 SIO Interrupt INTPND2.3 Watch Timer Interrupt INTPND2.4 P3.
INTERRUPT STRUCTURE Programming Tip — S3C9228/P9228 How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD • • • INTPND1, #11111011B ; Clear P0.2's interrupt pending bit INTPND2, #11110111B ; Clear watch timer interrupt pending bit IRET 2.
S3C9228/P9228 6 SAM88RCRI INSTRUCTION SET SAM88RCRI INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file.
SAM88RI INSTRUCTION SET S3C9228/P9228 Table 6-1.
S3C9228/P9228 SAM88RCRI INSTRUCTION SET Table 6-1.
SAM88RI INSTRUCTION SET S3C9228/P9228 FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 – FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register.
S3C9228/P9228 SAM88RCRI INSTRUCTION SET INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Table 6-3.
SAM88RI INSTRUCTION SET S3C9228/P9228 Table 6-4. Instruction Notation Conventions Notation cc Actual Operand Range Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, ..., 14) R Register or working register reg or Rn (reg = 0–255, n = 0–15) Register pair or working register pair reg or RRp (reg = 0–254, even number only, where p = 0, 2, ...
S3C9228/P9228 SAM88RCRI INSTRUCTION SET Table 6-5.
SAM88RI INSTRUCTION SET S3C9228/P9228 Table 6-5.
S3C9228/P9228 SAM88RCRI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
SAM88RI INSTRUCTION SET S3C9228/P9228 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
S3C9228/P9228 ADC — SAM88RCRI INSTRUCTION SET Add With Carry ADC dst,src Operation: dst ¨ dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands.
SAM88RI INSTRUCTION SET ADD — S3C9228/P9228 Add ADD dst,src Operation: dst ¨ dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
S3C9228/P9228 AND — SAM88RCRI INSTRUCTION SET Logical AND AND dst,src Operation: dst ¨ dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
SAM88RI INSTRUCTION SET S3C9228/P9228 CALL — Call Procedure CALL dst Operation: SP @SP SP @SP PC ¨ ¨ ¨ ¨ ¨ SP – 1 PCL SP –1 PCH dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
S3C9228/P9228 CCF — SAM88RCRI INSTRUCTION SET Complement Carry Flag CCF Operation: C ¨ NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected.
SAM88RI INSTRUCTION SET CLR — S3C9228/P9228 Clear CLR dst Operation: dst ¨ "0" The destination location is cleared to "0". Flags: No flags are affected.
S3C9228/P9228 COM — SAM88RCRI INSTRUCTION SET Complement COM dst Operation: dst ¨ NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
SAM88RI INSTRUCTION SET CP — S3C9228/P9228 Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
S3C9228/P9228 DEC — SAM88RCRI INSTRUCTION SET Decrement DEC dst Operation: dst ¨ dst – 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is –128(80H) and result value is +127(7FH); cleared otherwise. D: Unaffected. H: Unaffected.
SAM88RI INSTRUCTION SET DI — S3C9228/P9228 Disable Interrupts DI Operation: SYM (2) ¨ 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: No flags are affected.
S3C9228/P9228 EI — SAM88RCRI INSTRUCTION SET Enable Interrupts EI Operation: SYM (2) ¨ 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: No flags are affected.
SAM88RI INSTRUCTION SET IDLE — S3C9228/P9228 Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: opc Example: The instruction IDLE stops the CPU clock but not the system clock.
S3C9228/P9228 INC — SAM88RCRI INSTRUCTION SET Increment INC dst Operation: dst ¨ dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is –128(80H); cleared otherwise. D: Unaffected. H: Unaffected.
SAM88RI INSTRUCTION SET IRET — S3C9228/P9228 Interrupt Return IRET IRET Operation: FLAGS ¨ @SP SP ¨ SP + 1 PC ¨ @SP SP ¨ SP + 2 SYM(2) ¨ 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred).
S3C9228/P9228 JP — SAM88RCRI INSTRUCTION SET Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ¨ dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair.
SAM88RI INSTRUCTION SET JR — S3C9228/P9228 Jump Relative JR cc,dst Operation: If cc is true, PC ¨ PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed (See list of condition codes).
S3C9228/P9228 LD — SAM88RCRI INSTRUCTION SET Load LD dst,src Operation: dst ¨ src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected.
SAM88RI INSTRUCTION SET LD — S3C9228/P9228 Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD 6-28 R0,#10H → R0,01H → 01H,R0 → R1,@R0 → @R0,R1 → 00H,01H → 02H,@00H → 00H,#0AH → @00H,#10H → @00H,02H → R0,#LOOP[R1]→ #LOOP[R0],R1→ R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 0
S3C9228/P9228 SAM88RCRI INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ¨ src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src 1.
SAM88RI INSTRUCTION SET LDC/LDE — S3C9228/P9228 Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
S3C9228/P9228 SAM88RCRI INSTRUCTION SET LDCD/LDED — LDCD/LDED dst,src Operation: dst ¨ src Load Memory and Decrement rr ¨ rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.
SAM88RI INSTRUCTION SET LDCI/LDEI — S3C9228/P9228 Load Memory and Increment LDCI/LDEI dst,src Operation: dst ¨ src rr ¨ rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.
S3C9228/P9228 NOP — SAM88RCRI INSTRUCTION SET No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 FF When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
SAM88RI INSTRUCTION SET OR — S3C9228/P9228 Logical OR OR dst,src Operation: dst ¨ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3C9228/P9228 POP — SAM88RCRI INSTRUCTION SET Pop From Stack POP dst Operation: dst ¨ @SP SP ¨ SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
SAM88RI INSTRUCTION SET S3C9228/P9228 PUSH — Push To Stack PUSH src Operation: SP ¨ SP – 1 @SP ¨ src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No flags are affected.
S3C9228/P9228 RCF — SAM88RCRI INSTRUCTION SET Reset Carry Flag RCF RCF Operation: C ¨ 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 CF Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
SAM88RI INSTRUCTION SET RET — S3C9228/P9228 Return RET Operation: PC ¨ @SP SP ¨ SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: No flags are affected.
S3C9228/P9228 RL — SAM88RCRI INSTRUCTION SET Rotate Left RL dst Operation: C ¨ dst (7) dst (0) ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise.
SAM88RI INSTRUCTION SET RLC — S3C9228/P9228 Rotate Left Through Carry RLC dst Operation: dst (0) ¨ C C ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise.
S3C9228/P9228 RR SAM88RCRI INSTRUCTION SET — Rotate Right RR dst Operation: C ¨ dst (0) dst (7) ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise.
SAM88RI INSTRUCTION SET RRC — S3C9228/P9228 Rotate Right Through Carry RRC dst Operation: dst (7) ¨ C C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1".
S3C9228/P9228 SBC — SAM88RCRI INSTRUCTION SET Subtract With Carry SBC dst,src Operation: dst ¨ dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand.
SAM88RI INSTRUCTION SET SCF — S3C9228/P9228 Set Carry Flag SCF Operation: C ¨ 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: opc Example: The statement SCF sets the carry flag to logic one.
S3C9228/P9228 SRA — SAM88RCRI INSTRUCTION SET Shift Right Arithmetic SRA dst Operation: dst (7) ¨ dst (7) C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 6 0 C Flags: C: Z: S: V: D: H: Set if the bit shifted from the LSB position (bit zero) was "1".
SAM88RI INSTRUCTION SET STOP — S3C9228/P9228 Stop Operation STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input.
S3C9228/P9228 SUB — SAM88RCRI INSTRUCTION SET Subtract SUB dst,src Operation: dst ¨ dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Z: S: V: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise.
SAM88RI INSTRUCTION SET TCM — S3C9228/P9228 Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result.
S3C9228/P9228 TM — SAM88RCRI INSTRUCTION SET Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: D: H: Unaffected.
SAM88RI INSTRUCTION SET S3C9228/P9228 XOR — Logical Exclusive OR XOR dst,src Operation: dst ¨ dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3C9228/P9228 7 CLOCK CIRCUITS CLOCK CIRCUITS OVERVIEW The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency, is determined by CLKCON register settings.
CLOCK CIRCUITS S3C9228/P9228 SUB OSCILLATOR CIRCUITS MAIN OSCILLATOR CIRCUITS XIN XTIN XOUT XTOUT 32.768 kHz Figure 7-1. Crystal/Ceramic Oscillator XIN Figure 7-4. Crystal/Ceramic Oscillator XTIN XOUT XTOUT Figure 7-2. External Oscillator XIN R XOUT Figure 7-3. RC Oscillator 7-2 Figure 7-5.
S3C9228/P9228 CLOCK CIRCUITS CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When the fx is selected as system clock).
CLOCK CIRCUITS S3C9228/P9228 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following functions: — Oscillator IRQ wake-up function enable/disable — Oscillator frequency divide-by value CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release (This is called the “IRQ wake-up” function). The IRQ “wake-up” enable bit is CLKCON.7.
S3C9228/P9228 CLOCK CIRCUITS OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions: — System clock selection — Main oscillator control — Sub oscillator control OSCCON.0 register settings select Main clock or Sub clock as system clock. After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0". The main oscillator can be stopped or run by setting OSCCON.3.
CLOCK CIRCUITS S3C9228/P9228 SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the system clock. OSCCON .3 start or stop main clock oscillation, and OSCCON.
S3C9228/P9228 CLOCK CIRCUITS STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B". Stop Control Register (STPCON) E0H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .
CLOCK CIRCUITS S3C9228/P9228 NOTES 7-8
RESET and POWER-DOWN S3C9228/P9228 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C9228/P9228 into a known operating status.
RESET and POWER-DOWN S3C9228/P9228 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But the watch timer and LCD controller will not halted in stop mode if the sub clock is selected as watch timer clock source. The data stored in the internal register file are retained in stop mode.
S3C9228/P9228 RESET and POWER-DOWN Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release stop mode. That is, you had better use the idle instruction instead of stop one when sub clock is selected as the system clock.
RESET and POWER-DOWN S3C9228/P9228 HARDWARE RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values: — A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively. — An 'x' means that the bit value is undefined following RESET.
RESET and POWER-DOWN S3C9228/P9228 Table 8-1.
RESET and POWER-DOWN S3C9228/P9228 NOTES 8-6
S3C9228/P9228 9 I/O PORTS I/O PORTS OVERVIEW The S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.
I/O PORTS S3C9228/P9228 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2.
S3C9228/P9228 I/O PORTS PORT 0 Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P0.0-P0.3): TAOUT,T1CLK, BUZ, INT — High-nibble pins (P0.4-P0.
I/O PORTS S3C9228/P9228 Port 0 Control Register (P0CON) EBH, Page 0, R/W MSB .7 .6 P0.3/BUZ (INT) .5 .4 P0.2 (INT) .3 .2 .1 .0 LSB P0.1/T1CLK P0.0/TAOUT (INT) (INT) P0CON bit-pair pin configuration settings: Schmitt trigger input mode (T1CLK) Push-pull output mode 00 01 10 11 N-channel open-drain output mode Alternative function (TAOUT, BUZ) Figure 9-2. Port 0 Control Register (P0CON) Port 0 Interrupt Control Register (P0INT) EDH, Page 0, R/W MSB .7 .6 .5 Not used .4 .3 .2 .1 .
S3C9228/P9228 I/O PORTS Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND1 bit configuration settings: 0 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) 1 Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0) Port 0 Interrupt Edge Selection Register (P0EDGE) EEH, Page 0, R/W MSB .7 .6 .5 .4 .3 .
I/O PORTS S3C9228/P9228 PORT 1 Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0. P1.0-P1.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P1.0-P1.3): AD0-AD3, INT Port 1 Control Register (P1CON) Port 1 has a 8-bit control register: P1CON for P1.0-P1.3.
S3C9228/P9228 I/O PORTS Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT) Not used P1INT bit configuration settings: 0 1 Disable interrupt Enable interrupt Figure 9-8. Port 1 Interrupt Control Register (P1INT) Port 1 Interrupt Pending Bits (INTPND1.7-.4) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.
I/O PORTS S3C9228/P9228 Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT) Not used P1EDGE bit configuration settings: 0 Falling edge detection Rising edge detection 1 Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE) Port 1 Pull-up Control Register (P1PUR) F0H, Page 0, R/W MSB .7 .6 .5 Not used .4 .3 .2 .1 .0 P1.3 P1.2 P1.1 P1.
S3C9228/P9228 I/O PORTS PORT 2 Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0. P2.0-P2.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P2.0-P2.3): SCK, SO, SI, SEG0-SEG1 Port 2 Control Register (P2CON) Port 2 has a 8-bit control register: P2CON for P2.0-P2.3.
I/O PORTS S3C9228/P9228 Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W MSB .7 .6 .5 Not used .4 .3 .2 .1 .0 P2.3 P2.2 P2.1 P2.0 LSB P2PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor Figure 9-13.
S3C9228/P9228 I/O PORTS PORT 3 Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0. P3.0-P3.1 can serve as inputs (with or without pullup, and high impedance input), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P3.0-P3.1): SEG2-SEG3, INTP Port 3 Control Register (P3CON) Port 3 has a 8-bit control register: P3CON for P3.
I/O PORTS S3C9228/P9228 Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.1 P3.0 (INTP) (INTP) Not used P3INT bit configuration settings: 0 1 Disable interrupt Enable interrupt Figure 9-15. Port 3 Interrupt Control Register (P3INT) Port 3 Interrupt Pending Bits (INTPND2.5-.4) D7H, Page 0, R/W MSB .7 .6 Not used .5 .4 P3.0 (INTP) .3 .2 SIO P3.0 (INTP) Watch Timer .1 .
S3C9228/P9228 I/O PORTS Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.1 P3.0 (INTP) (INTP) Not used P3EDGE bit configuration settings: 0 1 Falling edge detection Rising edge detection Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE) Port 3 Pull-up Control Register (P3PUR) F6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 Not used .1 .0 P3.1 P3.
I/O PORTS S3C9228/P9228 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: — Low-nibble pins (P4.0-P4.3): SEG4-SEG7 — High-nibble pins (P4.4-P4.
S3C9228/P9228 I/O PORTS PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: — Low-nibble pins (P5.0-P5.3): SEG12-SEG15 — High-nibble pins (P5.4-P5.
I/O PORTS S3C9228/P9228 PORT 6 Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: — Low-nibble pins (P6.0-P6.3): COM0-COM3 Port 6 Control Register (P6CON) Port 6 has a 8-bit control register: P6CONH for P6.0-P6.3.
S3C9228/P9228 (Preliminary Spec) 10 BASIC TIMER BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
BASIC TIMER S3C9228/P9228 (Preliminary Spec) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addressable using Register addressing mode. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of f xx/4096.
S3C9228/P9228 (Preliminary Spec) BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to “00H”, automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.
BASIC TIMER S3C9228/P9228 (Preliminary Spec) RESET or STOP Bit 1 Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to Disable) Data Bus fXX/4096 Clear fXX/1024 fXX DIV fXX/128 MUX 8-Bit Up Counter (BTCNT, Read-Only) OVF fXX/16 R Start the CPU (note) Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). Figure 10-2.
S3C9228/P9228 11 TIMER 1 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers. — One 16-bit timer mode (Timer 1) — Two 8-bit timers mode (Timer A and B) OVERVIEW The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate TACON setting.
TIMER 1 S3C9228/P9228 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer) — Select the timer 1 input clock frequency — Clear the timer 1 counter, TACNT and TBCNT — Enable the timer 1 interrupt TACON is located in page 0, at address BBH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H".
S3C9228/P9228 TIMER 1 BTCON.0 TACON.6-.4 1/512 R TACON.3 Data Bus 1/256 TACON.2 fxx (XIN or XT IN) DIV 1/64 1/8 1/1 fxt M U LSB TBCNT MSB Clear TACNT R TACON.1 Match X 16-Bit Comparator T1CLK LSB MSB TBDATA TADATA Buffer Buffer INTPND2.0 T1INT TAOUT Match Signal Counter clear signal TBDATA TADATA Data Bus NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) Figure 11-2.
TIMER 1 S3C9228/P9228 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.
S3C9228/P9228 TIMER 1 TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. A reset clears TBCON to "00H".
TIMER 1 S3C9228/P9228 Timer B Control Register (TBCON) BAH, R/W MSB .7 Not used .6 .5 .4 .3 .2 .1 .
S3C9228/P9228 TIMER 1 FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.0) and the timer B match interrupt pending condition (INTPND2.1) must be cleared by software in the application's interrupt service by means of writing a "0" to the INTPND2.0 and INTPND2.1 interrupt pending bit.
TIMER 1 S3C9228/P9228 BTCON.0 R TACON.6-.4 1/512 1/256 TACON.3 Data Bus TACON.2 fxx (XIN or XT IN) 1/64 DIV M LSB MSB 1/8 U TACNT (8-Bit Up-Counter) R 1/1 X TACON.1 Match 8-Bit Comparator fxt T1CLK/ P0.1 Clear LSB INTPND2.0 TAINT TAOUT MSB TADATA Buffer Match Signal Counter Clear Signal TADATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) Figure 11-5.
S3C9228/P9228 TIMER 1 BTCON.0 R TBCON.6-.4 1/512 1/256 fxx (XIN or XTIN) DIV 1/64 TBCON.3 Data Bus M U 1/8 TBCON.2 LSB MSB TBCNT (8-Bit Up-Counter) R X TBCON.1 Match 1/1 8-Bit Comparator fxt Clear LSB INTPND2.1 TBINT MSB TBDATA Buffer Match Signal Counter Clear Signal TBDATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) Figure 11-6.
TIMER 1 S3C9228/P9228 NOTES 11-10
S3C9228/P9228 12 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt, then set the WTCON.6 to “1”. The watch timer overflow interrupt pending condition (INTPND2.
WATCH TIMER S3C9228/P9228 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode. A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock.
S3C9228/P9228 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM WTCON.7 WTCON.6 WT INT Enable BUZ (P0.3) WTCON.6 WTCON.5 8 MUX WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTINT fW/64 (0.5 kHz) fW/32 (1 kHz) fW/16 (2 kHz) fW/8 (4 kHz) Enable/Disable Selector Circuit INTPND2.3 WTCON.0 Clock Selector fW 32.768 kHz Frequency Dividing Circuit fW/27 fW/213 fW/214 fW/215 (1 Hz) fLCD = 2048 Hz fxt fx/128 fX = Main clock (where fx = 4.19 MHz) fxt = Sub clock (32,768 Hz) fW = Watch timer frequency Figure 12-2.
WATCH TIMER S3C9228/P9228 NOTES 12-4
S3C9228/P9228 13 LCD CONTROLLER/DRIVER LCD CONTROLLER/DRIVER OVERVIEW The S3C9228/P9228 microcontroller can directly drive an up-to-128-dot (16segments x 8 commons) LCD panel.
LCD CONTROLLER/DRIVER S3C9228/P9228 LCD CIRCUIT DIAGRAM 16 Port Latch SEG15/P5.3 Display RAM (Page1) SEG Control 160 16 MUX or Data BUS 4 LPOT 8 COM Control or selector COM Control LMOD LCD Voltage Control Port Latch Port 3 Control 2 Figure 13-2. LCD Circuit Diagram 13-2 SEG0/P2.1 fLCD Timing Controller Port Latch Selector COM7/SEG16/P5.4 COM4/SEG19/P5.7 COM3/P6.0 COM0/P6.3 P3.1/INTP/SEG2 P3.
S3C9228/P9228 LCD CONTROLLER/DRIVER LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0–SEG19 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use.
LCD CONTROLLER/DRIVER S3C9228/P9228 LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode. It has the following control functions.
S3C9228/P9228 LCD CONTROLLER/DRIVER LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET, a LPOT values are cleared to "0". LCD Port Control Register D8H, R/W MSB .7 .6 .5 .4 .3 .2 .1 Not used .0 LSB SEG0/P2.1 selection bit: 0 = SEG port 1 = Normal I/O port SEG4-SEG19 and COM0-COM3 selection bits: SEG1/P2.0 selection bit: 000 = P4.0-P6.3: LCD signal pins 0 = SEG port 001 = P4.0-P4.3: Normal I/O, P4.4-P6.
LCD CONTROLLER/DRIVER S3C9228/P9228 LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias 1/4 Bias 1/3 Bias S3C9228/P9228 S3C9228/P9228 S3C9228/P9228 VDD LMOD.4 VDD LMOD.4 VLC1 VLC2 VLC3 VLC4 VLC5 VSS VDD LMOD.4 VLC1 R R R R R VLC2 VLC3 VLC4 VLC5 VSS VLC1 R R R R R VLC2 VLC3 VLC4 VLC5 VSS R R R R R Figure 13-6. Internal Voltage Dividing Resistor Connection COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
S3C9228/P9228 LCD CONTROLLER/DRIVER COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 FR VDD VSS 1 Frame S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 COM0 VDD VLC1 VLC2 (VLC3) VLC4 VSS COM1 VDD VLC1 VLC2 (VLC3) VLC4 VSS COM2 VDD VLC1 VLC2 (VLC3) VLC4 VSS SEG0 VDD VLC1 VLC2 (VLC3) VLC4 VSS + VDD SEG0-COM0 + 1/4VLCD 0V - 1/4VLCD -VLCD Figure 13-7.
LCD CONTROLLER/DRIVER S3C9228/P9228 SEG0 SEG1 0 1 2 3 0 1 2 3 COM0 VDD VSS 1 Frame COM1 COM2 COM0 COM3 VDD VLC1(VLC2) VLC3(VLC4) VSS VDD COM1 COM2 COM3 VLC1(VLC2) VLC3(VLC4) VSS VDD VLC1(VLC2) VLC3(VLC4) VSS VDD VLC1(VLC2) VLC3(VLC4) VSS SEG0 VDD VLC1(VLC2) VLC3(VLC4) VSS SEG1 VDD VLC1(VLC2) VLC3(VLC4) VSS + VLCD COM0-SEG0 + 1/3 VLCD 0V - 1/3 V LCD - VLCD Figure 13-8.
S3C9228/P9228 SEG2 LCD CONTROLLER/DRIVER SEG1 SEG0 0 1 2 0 1 2 COM0 VDD VSS 1 Frame COM0 VDD VLC1(VLC2) VLC3(VLC4) VSS COM1 VDD VLC1(VLC2) VLC3(VLC4) VSS COM2 VDD VLC1(VLC2) VLC3(VLC4) VSS SEG0 VDD VLC1(VLC2) VLC3(VLC4) VSS SEG1 VDD VLC1(VLC2) VLC3(VLC4) VSS COM1 COM2 + VLCD COM0-SEG0 + 1/3 VLCD 0V - 1/3 VLCD - VLCD Figure 13-9.
LCD CONTROLLER/DRIVER S3C9228/P9228 NOTES 13-10
S3C9228/P9228 14 A/D CONVERTER 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values.
A/D CONVERTER S3C9228/P9228 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit × 10-bit + set-up time = 50 clocks, 50 clock × 1.
S3C9228/P9228 A/D CONVERTER Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only MSB .9 .8 .7 .6 .5 .4 .3 .2 LSB (ADDATAH) MSB - - - - - - .1 .0 LSB (ADDATAL) Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range VSS to VDD.
A/D CONVERTER S3C9228/P9228 VDD Analog Input Pin (VSS ≤ ADC input ≤ VDD) AD0-AD3 C 101 S3C9228 Figure 14-4.
S3C9228/P9228 15 SERIAL I/O INTERFACE SERIAL I/O INTERFACE OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer.
SERIAL I/O INTERFACE S3C9228/P9228 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module.
S3C9228/P9228 SERIAL I/O INTERFACE SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock. SIO Pre-scaler Register (SIOPS) E3H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Baud rate = (fXX/4)/(SIOPS + 1) Figure 15-2.
SERIAL I/O INTERFACE S3C9228/P9228 SERIAL I/O TIMING DIAGRAM (SIO) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Transmit Complete SIO INT Set SIOCON.3 Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Transmit Complete SIO INT Set SIOCON.3 Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.
S3C9228/P9228 16 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by an external interrupt — Stop mode release timing when initiated by a Reset — I/O capacitance — A.C.
ELECTRICAL DATA S3C9228/P9228 Table 16-1. Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Conditions Rating Unit Supply voltage VDD – – 0.3 to + 6.5 V Input voltage VIN – 0.3 to VDD + 0.3 V Output voltage VO – 0.3 to VDD + 0.
S3C9228/P9228 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics (Continued) (TA = – 25°C to + 85°C, VDD = 2.0 V to 5.
ELECTRICAL DATA S3C9228/P9228 Table 16-2. D.C. Electrical Characteristics (Concluded) (TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V) Parameter Symbol Supply current (1) IDD1 IDD2 Conditions Min Typ Max Unit – 6.0 12.0 mA Run mode: VDD = 5 V ± 10% 8.0 MHz Crystal oscillator C1 = C2 = 22pF 4.19 MHz 3.0 6.0 VDD = 3 V ± 10% 8.0 MHz 2.5 5.0 4.19 MHz 1.5 3.0 Idle mode: VDD = 5 V ± 10% 8.0 MHz 1.3 3.0 Crystal oscillator C1 = C2 = 22pF 4.19 MHz 1.0 2.0 VDD = 3 V ± 10% 8.
S3C9228/P9228 ELECTRICAL DATA Table 16-3. Data Retention Supply Voltage in Stop Mode (TA = – 25 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 2.0 – 5.5 V Data retention supply current IDDDR – – 1 µA Stop mode, TA = 25 °C VDDDR = 2.0 V Idle Mode (Basic Timer Active) ~ ~ Stop Mode Normal Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instruction 0.8 VDD tWAIT NOTE: tWAIT is the same as 16 x 1/BT clock.
ELECTRICAL DATA S3C9228/P9228 RESET Occurs Oscillation Stabilization TIme ~ ~ Stop Mode Normal Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction RESET 0.8 VDD 0.2 VDD NOTE: tWAIT tWAIT is the same as 16 × 1/BT clock. Figure 16-2. Stop Mode Release Timing When Initiated by a RESET Table 16-4.
S3C9228/P9228 ELECTRICAL DATA Table 16-5. A.C. Electrical Characteristics (TA = – 25°C to + 85°C, VDD = 2.0 V to 5.
ELECTRICAL DATA S3C9228/P9228 Table 16-6. A/D Converter Electrical Characteristics (TA = – 25°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Conditions Min Typ Max Unit – 10 – bit VDD = 5.12 V – – ±3 LSB Resolution Total accuracy Integral linearity error ILE fxx = 8 MHz – – ±2 Differential linearity error DLE f CON = fxx/4 – – ±1 Offset error of top EOT – ±1 ±3 Offset error of bottom EOB – ±0.
S3C9228/P9228 ELECTRICAL DATA tRSL RESET 0.2 VDD Figure 16-4. Input Timing for RESET tKCY tKL tKH SCK 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI 0.2VDD tKSO SO Output Data Figure 16-5.
ELECTRICAL DATA S3C9228/P9228 Table 16-7. Main Oscillation Characteristics (TA = – 25°C to + 85°C) Oscillator Clock Configuration Crystal C1 XIN Parameter Test Condition Min Typ Max Units 2.7 V – 5.5 V 0.4 – 8 MHz 2.0 V – 5.5 V 0.4 – 4 2.7 V – 5.5 V 0.4 – 8 2.0 V – 5.5 V 0.4 – 4 2.7 V – 5.5 V 0.4 – 8 2.0 V – 5.5 V 0.4 – 4 Frequency 5.0 V 0.4 – 2 Frequency 3.0 V 0.
S3C9228/P9228 ELECTRICAL DATA Table 16-9. Main Oscillation Stabilization Time (TA = – 25 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal fx > 1 MHz – – 30 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage ranage. – – 10 ms External clock XIN input high and low width (tXH, tXL) 62.5 – 1250 ns 1/fx tXL tX XIN VDD-0.1 V 0.1 V Figure 16-6.
ELECTRICAL DATA S3C9228/P9228 Table 16-10. Sub Oscillation Stabilization Time (TA = – 25 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit – – – 10 s 5 – 15 µs Crystal External clock XTIN input high and low width (tXH, tXL) 1/fxt tXTL tXTH XTIN VDD-0.1 V 0.1 V Figure 16-7.
S3C9228/P9228 ELECTRICAL DATA Instruction Clock fx (Main/Sub oscillation frequency) 2 MHz 8 MHz 1.0 MHz 4 MHz 400 kHz 6.25 kHz (main)/8.2 kHz(sub) 400 kHz (main)/32.8 kHz(sub) 1 2 2.7 5.5 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 16-8.
ELECTRICAL DATA S3C9228/P9228 NOTES 16-14
S3C9228/P9228 17 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package. #22 0.2 5 42-SDIP-600 +0 - 0 .1 .05 0-15 15.24 14.00 ± 0.2 #42 (1.77) NOTE: 1.00 ± 0.1 5.08 MAX 39.10 ± 0.2 0.1 3.30 ± 0.3 0.2 39.50 MAX 0.50 ± 3.50 ± #21 0.51 MIN #1 1.78 Dimensions are in millimeters. Figure 17-1.
MECHANICAL DATA S3C9228/P9228 13.20 ± 0.3 0-8 10.00 ± 0.2 10.00 ± 0.2 + 0.10 - 0.05 0.10 MAX 44-QFP-1010B 0.80 ± 0.20 13.20 ± 0.3 0.15 #44 #1 + 0.10 0.35 - 0.05 0.80 0.05 MIN (1.00) 2.05 ± 0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 17-2.
S3C9228/P9228 S3P9228 OTP 18 S3P9228 OTP OVERVIEW The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. 44 43 42 41 40 39 38 37 36 35 34 P0.5 P0.4 P0.3/BUZ/INT P0.2/INT P0.1/T1CLK/INT P0.0/TAOUT/INT COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.
S3P9228 OTP S3C9228/P9228 S3C9228 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (42-SDIP) COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT SDAT/P1.2/AD2/INT SCLK/P1.3/AD3/INT VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET /RESET P2.3 P2.2/SI SEG0/P2.1/SO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.
S3C9228/P9228 S3P9228 OTP Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P1.2 SDAT 3 (9) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P1.3 SCLK 4 (10) I/O Serial clock pin. Input only pin. TEST VPP(TEST) 9 (15) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.
S3P9228 OTP S3C9228/P9228 Table 18-4. D.C. Electrical Characteristics (TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V) Parameter Symbol Supply current (1) IDD1 IDD2 Conditions Min Typ Max Unit – 6.0 12.0 mA Run mode: VDD = 5 V ± 10% 8.0 MHz Crystal oscillator C1 = C2 = 22pF 4.19 MHz 3.0 6.0 VDD = 3 V ± 10% 8.0 MHz 2.5 5.0 4.19 MHz 1.5 3.0 Idle mode: VDD = 5 V ± 10% 8.0 MHz 1.3 3.0 Crystal oscillator C1 = C2 = 22pF 4.19 MHz 1.0 2.0 VDD = 3 V ± 10% 8.0 MHz 0.8 1.6 4.
S3C9228/P9228 S3P9228 OTP Instruction Clock fx (Main/Sub oscillation frequency) 2 MHz 8 MHz 1.0 MHz 4 MHz 400 kHz 6.25 kHz (main)/8.2 kHz(sub) 400 kHz (main)/32.8 kHz(sub) 1 2 2.7 5.5 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 18-3.
S3P9228 OTP S3C9228/P9228 NOTES 18-6
S3C9228/P9228 19 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used.
DEVELOPMENT TOOLS S3C9228/P9228 IBM-PC AT or Compatible RS-232C SMDS2+ Target Application System PROM/OTP Writer Unit RAM Break/Display Unit BUS Probe Adapter Trace/Timer Unit SAM8 Base Unit Power Supply Unit POD TB9228 Target Board EVA Chip Figure 19-1.
S3C9228/P9228 DEVELOPMENT TOOLS TB9228 TARGET BOARD The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system. TB9228 To User_VCC OFF REV.0 '2002.03.
DEVELOPMENT TOOLS S3C9228/P9228 Table 19-1. Power Selection Settings for TB9228 "To User_VCC" Settings Operating Mode Comments To User_VCC Off On TB9228 VCC Target System The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system. VSS VCC SMDS2/SMDS2+ To User_VCC Off On TB9228 External VCC VSS Target System The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
S3C9228/P9228 DEVELOPMENT TOOLS SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 19-2. The SMDS2+ Tool Selection Setting "SW1" Setting SMDS2 Operating Mode SMDS2+ R/W R/W Target Board SMDS2+ Table 19-3.
DEVELOPMENT TOOLS S3C9228/P9228 J101 42-SDIP P6.2 P6.3 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.1 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 J102 44-QFP 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 P6.1 P6.0 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P3.0 P3.1 P2.0 NC NC NC NC P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.
S3C9228/P9228 DEVELOPMENT TOOLS Target Board Target System J101 50-Pin DIP Connector 1 J101 42 1 42 21 22 Target Cable for Connector Part Name: AP42SD Order Code: SM6538 21 22 Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package Target Board Target System J102 44 1 44 22 23 Target Cable for 50-pin Connector Part Name: AP50D-A Order Code: SM6305 22 23 50-Pin Connector 50-Pin Connector 1 J102 Figure 19-5.
DEVELOPMENT TOOLS S3C9228/P9228 NOTES 19-8
S3C9228/P9228 1 PRODUCT OVERVIEW PRODUCT OVERVIEW SAM88RCRI PRODUCT FAMILY Samsung's SAM88RCRI family of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device. A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements.
PRODUCT OVERVIEW S3C9228/P9228 FEATURES CPU LCD Controller/Driver • SAM88RCRI CPU core • 16 segments and 8 common terminals Memory • • 3, 4, and 8 common selectable Internal resistor circuit for LCD bias • • 8192 × 8 bits program memory (ROM) 264 × 8 bits data memory (RAM) (Including LCD data memory) Instruction Set • 41 instructions • Idle and Stop instructions added for power-down modes 8-bit Serial I/O Interface • 8-bit transmit/receive mode • 8-bit receive mode • LSB-first or MSB-fi
S3C9228/P9228 PRODUCT OVERVIEW BLOCK DIAGRAM TAOUT/ P0.0 T1CLK/ P0.1 8-Bit Timer/ CounterA 8-Bit Timer/ CounterB P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P0.4 P0.5 P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT P2.0/SCK/SEG1 P2.1/SO/SEG0 P2.2/SI P2.3 RESET X IN XT IN XOUT XT OUT 16-Bit Timer/ Counter1 I/O Port 0 Watchdog Timer Basic Timer Port I/O and Interrupt Control I/O Port 1 SAM88RCRI CPU Watch Timer LCD Driver/ Controller COM0-COM3/P6.3-P6.0 COM4-COM7/ SEG19-SEG16/P5.
PRODUCT OVERVIEW S3C9228/P9228 44 43 42 41 40 39 38 37 36 35 34 P0.5 P0.4 P0.3/BUZ/INT P0.2/INT P0.1/T1CLK/INT P0.0/TAOUT/INT COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 PIN ASSIGNMENTS 1 2 3 4 5 6 7 8 9 10 11 S3C9228 (44-QFP) 33 32 31 30 29 28 27 26 25 24 23 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.6 SEG9/P4.5 SEG8/P4.4 RESET P2.3 P2.2/SI SEG0/P2.1/SO SEG1/P2.0/SCK SEG2/P3.1/INTP SEG3/P3.0/INTP SEG4/P4.0 SEG5/P4.
S3C9228/P9228 PRODUCT OVERVIEW (42-SDIP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S3C9228 COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT P1.2/AD2/INT P1.3/AD3/INT VDD VSS XOUT XIN TEST XTIN XTOUT RESET P2.3 P2.2/SI SEG0/P2.1/SO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.0 SEG11/P4.7 SEG10/P4.
PRODUCT OVERVIEW S3C9228/P9228 PIN DESCRIPTIONS Table 1-1. Pin Descriptions Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins P0.0 P0.1 P0.2 P0.3 I/O 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output and software assignable pull-ups. E-4 39(3) 40(4) 41(5) 42(6) TAOUT/INT T1CLK/INT INT BUZ/INT P0.4-P0.5 O 1-bit programmable output port. C 43-44 P1.0 P1.1 P1.2 P1.3 I/O 1-bit programmable I/O port.
S3C9228/P9228 PRODUCT OVERVIEW Table 1-1. Pin Descriptions (Continued) Pin Names Pin Type Pin Description Circuit Number Pin Numbers Share Pins – VDD, VSS – Power input pins for internal power block – 5,6(11,12) XOUT, XIN – Main oscillator pins for main clock – 7,8(13,14) XTOUT, XTIN – Sub oscillator pins for sub clock – 11,10(17,16) – TEST – Chip test input pin Hold GND when the device is operating – 9(15) – RESET I RESET signal input pin.
PRODUCT OVERVIEW S3C9228/P9228 PIN CIRCUIT DIAGRAMS VDD Pull-Up Resistor RESET Noise Filter Figure 1-4. Pin Circuit Type B VDD Data Output Output Disable VSS Figure 1-5.
S3C9228/P9228 PRODUCT OVERVIEW VDD VDD Pull-up Resistor Pull-up Enable Open-Drain I/O Data Output Disable External Interrupt Input Figure 1-7. Pin Circuit Type E-4 VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data Output Disable Circuit Type E I/O ADEN ADSELECT Data To ADC Figure 1-8.
PRODUCT OVERVIEW S3C9228/P9228 VLC1 VLC2 VLC3 SEG/COM Out Output Disable VLC4 VLC5 VSS Figure 1-9.
S3C9228/P9228 PRODUCT OVERVIEW VDD Pull-up Resistor VDD Pull-up Enable Open-Drain EN Data I/O LCD Out EN COM/SEG Output Disable Circuit Type H-23 Figure 1-10. Pin Circuit Type H-32 VDD VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data I/O LCD Out EN COM/SEG Output Disable Circuit Type H-23 Figure 1-11.
PRODUCT OVERVIEW S3C9228/P9228 VDD VDD Pull-up Resistor Pull-up Enable Open-Drain EN Data I/O Port Enable (LMOD.5) LCD Out EN COM/SEG Output Disable Circuit Type H-23 Figure 1-12.
S3C9228/P9228 2 ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C9228/P9228 microcontroller has three kinds of address space: — Program memory (ROM) — Internal register file — LCD display register file A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file.
ADDRESS SPACES S3C9228/P9228 PROGRAM MEMORY (ROM) Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H–0001H) are an interrupt vector address. The program reset address in the ROM is 0100H. (Decimal) 8,192 (Hex) 1FFFH 8K bytes Internal Program Memory Area 256 Program Start 2 1 0 0100H 0002H Interrupt Vector 0001H 0000H Figure 2-1.
S3C9228/P9228 ADDRESS SPACES REGISTER ARCHITECTURE The upper 72 bytes of the S3C9228/P9228's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 184 bytes of internal register file (00H–B7H) is called the general purpose register space.
ADDRESS SPACES S3C9228/P9228 COMMON WORKING REGISTER AREA (C0H–CFH) The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file.
S3C9228/P9228 ADDRESS SPACES SYSTEM STACK S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file. STACK OPERATIONS Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction.
ADDRESS SPACES S3C9228/P9228 + PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SP,#0B8H ; SP ← B8H (Normally, the SP is set to 0B8H by the ; initialization routine) SYM WTCON 20H R3 ; ; ; ; Stack address 0B7H ← Stack address 0B6H ← Stack address 0B5H ← Stack address 0B4H ← R3 20H WTCON SYM ; ; ; ; R3 ← Stack address 0B4H 20H ← Stack address 0B5H WTCON ← S
S3C9228/P9228 3 ADDRESSING MODES ADDRESSING MODES OVERVIEW Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.
ADDRESSING MODES S3C9228/P9228 REGISTER ADDRESSING MODE (R) In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2).
S3C9228/P9228 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register.
ADDRESSING MODES S3C9228/P9228 INDIRECT REGISTER ADDRESSING MODE (Continued) Register File Program Memory Example Instruction References Program Memory dst OPCODE REGISTER PAIR Points to Rigister Pair Program Memory Sample Instructions: CALL JP @RR2 @RR2 Value used in Instruction OPERAND Figure 3-4.
S3C9228/P9228 ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE (Continued) Register File CFH Program Memory 4-Bit Working Register Address dst OPCODE Sample Instruction: OR src R6, @R2 4 LSBs . . . . OPERAND Point to the Woking Register (1 of 16) Value used in Instruction C0H OPERAND Figure 3-5.
ADDRESSING MODES S3C9228/P9228 INDIRECT REGISTER ADDRESSING MODE (Concluded) Register File CFH . . . .
S3C9228/P9228 ADDRESSING MODES INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of –128 to +127.
ADDRESSING MODES S3C9228/P9228 INDEXED ADDRESSING MODE (Continued) Register File Program Memory 4-Bit Working Register Address XS (OFFSET) dst src OPCODE NEXT 3 Bits Point to Working Register Pair (1 of 8) Register Pair 16-Bit address added to offset LSB Selects + 8-Bits 16-Bits Program Memory or Data Memory 16-Bits OPERAND Value used in Instruction Sample Instructions: LDC R4, #04H[RR2] LDE R4,#04H[RR2] ; The values in the program address (RR2 + #04H) are loaded into register R4.
S3C9228/P9228 ADDRESSING MODES INDEXED ADDRESSING MODE (Concluded) Program Memory 4-Bit Working Register Address XLH (OFFSET) XLL (OFFSET) dst src OPCODE Register File NEXT 3 Bits Register Pair Point to Working Register Pair (1 of 8) 16-Bit address added to offset LSB Selects + 8-Bits 16-Bits Program Memory or Data Memory 16-Bits OPERAND Value used in Instruction Sample Instructions: LDC R4, #1000H[RR2] #1000H) LDE R4, #1000H[RR2] ; The values in the program address (RR2 + are loaded into
ADDRESSING MODES S3C9228/P9228 DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.
S3C9228/P9228 ADDRESSING MODES DIRECT ADDRESS MODE (Continued) Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions: JP CALL C,JOB1 DISPLAY ; ; Where JOB1 is a 16-bit immediate address Where DISPLAY is a 16-bit immediate address Figure 3-11.
ADDRESSING MODES S3C9228/P9228 RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. The instructions that support RA addressing is JR.
S3C9228/P9228 4 CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs. System and peripheral registers are summarized in Table 4-1.
CONTROL REGISTERS S3C9228/P9228 Table 4-1.
S3C9228/P9228 CONTROL REGISTERS Table 4-1. System and Peripheral Control Registers (Page 0) Register Name Mnemonic Address (Page 0) Decimal R/W Hex Locations D8H-B9H are not mapped.
CONTROL REGISTERS S3C9228/P9228 Bit number(s) that is/are appended to the register name for bit addressing Name of individual Register bit or bit function Full Register name mnemonic Register address (hexadecimal) D5H FLAGS - System Flags Register Bit Identifier RESET Value Read/Write .7 .7 .6 .5 .4 .3 .2 .1 .0 x R/W x R/W x R/W x R/W x R/W x R/W 0 R/W 0 R/W Carry Flag (C) .
S3C9228/P9228 CONTROL REGISTERS ADCON — A/D Converter Control Register D0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R R/W R/W R/W .7-.6 Not used for the S3C9228/P9228 .5-.4 A/D Input Pin Selection Bits .3 .2-.1 .0 0 0 AD0 (P1.0) 0 1 AD1 (P1.1) 1 0 AD2 (P1.2) 1 1 AD3 (P1.
CONTROL REGISTERS S3C9228/P9228 BTCON — Basic Timer Control Register DCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.4 Watchdog Timer Enable Bits 1 0 1 0 Any other value .3-.2 .1 .
S3C9228/P9228 CONTROL REGISTERS CLKCON — System Clock Control Register D4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6-.5 Oscillator IRQ Wake-up Function Bit 0 Enable IRQ for main or sub oscillator wake-up in power down mode 1 Disable IRQ for main or sub oscillator wake-up in power down mode Bits 6-5 0 .4-.3 .2-.
CONTROL REGISTERS S3C9228/P9228 FLAGS — System Flags Register D5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value x x x x – – – – R/W R/W R/W R/W – – – – Read/Write .7 Carry Flag (C) 0 .6 .5 .4 .3-.
S3C9228/P9228 CONTROL REGISTERS INTPND1 — Interrupt Pending Register 1 D6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 .6 .5 .4 .3 P1.3's Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) P1.2's Interrupt Pending Bit 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) P1.
CONTROL REGISTERS S3C9228/P9228 INTPND2 — Interrupt Pending Register 2 D7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – 0 0 0 0 0 0 Read/Write – – R/W R/W R/W R/W R/W R/W .7-.6 Not used for S3C9228/P9228 .5 P3.1 (INTP) Interrupt Pending Bit .4 .3 .2 .1 .0 0 No interrupt pending (when read), clear pending bit (when write) 1 Interrupt is pending (when read) P3.
S3C9228/P9228 CONTROL REGISTERS LMOD — LCD Mode Control Register FEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – 0 0 0 0 0 0 0 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6 COM Pins High Impedance Control Bit .5 .4 .3-.2 .1-.
CONTROL REGISTERS S3C9228/P9228 LPOT — LCD Port Control Register D8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – 0 0 0 0 0 0 0 Read/Write – R/W R/W R/W R/W R/W R/W R/W .7 Not used for S3C9228/P9228 .6-.4 SEG4-SEG19 and COM0-COM3 Selection Bit .3 .2 .1 .0 SEG4-7 SEG8-11 SEG12-15 SEG16-19/ COM7-COM4 COM0-3 P4.0-P4.3 P4.4-P4.7 P5.0-P5.3 P5.4-P5.7 P6.0-P6.
S3C9228/P9228 CONTROL REGISTERS OSCCON — Oscillator Control Register D3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 – 0 Read/Write – – – – R/W R/W – R/W .7-.4 Not used for S3C9228/P9228 .3 Main Oscillator Control Bit .2 0 Main oscillator RUN 1 Main oscillator STOP Sub Oscillator Control Bit 0 Sub oscillator RUN 1 Sub oscillator STOP .1 Not used for S3C9228/P9228 .
CONTROL REGISTERS S3C9228/P9228 P0CON – Port 0 Control Register EBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-14 P0.3/BUZ/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (BUZ output) P0.
S3C9228/P9228 CONTROL REGISTERS P0INT –Port 0 Interrupt Enable Register EDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Enable Bit .2 .1 .0 0 Disable interrupt 1 Enable interrupt P0.2's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt P0.1's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt P0.
CONTROL REGISTERS S3C9228/P9228 P0PUR –Port 0 Pull-up Resistors Enable Register ECH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Pull-up Resistor Enable Bit .2 .1 .0 4-16 0 Disable pull-up resistor 1 Enable pull-up resistor P0.2's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P0.
S3C9228/P9228 CONTROL REGISTERS P0EDGE –Port 0 Interrupt Edge Selection Register EEH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P0.3's Interrupt Edge Setting Bit .2 .1 .0 0 Falling edge interrupt 1 Rising edge interrupt P0.2's Interrupt State Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt P0.
CONTROL REGISTERS S3C9228/P9228 P1CON – Port 1 Control Register EFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-18 P1.3/AD3/INT Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Alternative function (ADC mode) P1.
S3C9228/P9228 CONTROL REGISTERS P1INT –Port 1 Interrupt Enable Register F1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Enable Bit .2 .1 .0 0 Disable interrupt 1 Enable interrupt P1.2's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt P1.1's Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt P1.
CONTROL REGISTERS S3C9228/P9228 P1PUR –Port 1 Pull-up Resistors Enable Register F0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Pull-up Resistor Enable Bit .2 .1 .0 4-20 0 Disable pull-up resistor 1 Enable pull-up resistor P1.2's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P1.
S3C9228/P9228 CONTROL REGISTERS P1EDGE –Port 1 Interrupt Edge Selection Register F2H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P1.3's Interrupt Edge Setting Bit .2 .1 .0 0 Falling edge interrupt 1 Rising edge interrupt P1.2's Interrupt State Setting Bit 0 Falling edge interrupt 1 Rising edge interrupt P1.
CONTROL REGISTERS S3C9228/P9228 P2CON – Port 2 Control Register F3H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-22 P2.3 Configuration Bits 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not available P2.
S3C9228/P9228 CONTROL REGISTERS P2PUR –Port 2 Pull-up Resistors Enable Register F4H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 P2.3's Pull-up Resistor Enable Bit .2 .1 .0 0 Disable pull-up resistor 1 Enable pull-up resistor P2.2's Pull-up Resistor Enable Bit 0 Disable pull-up resistor 1 Enable pull-up resistor P2.
CONTROL REGISTERS S3C9228/P9228 P3CON – Port 3 Control Register F5H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3-.2 P3.1/SEG2/INTP Configuration Bits .1-.0 4-24 0 0 Schmitt trigger input 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Not available P3.
S3C9228/P9228 CONTROL REGISTERS P3INT –Port 3 Interrupt Enable Register F7H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Interrupt Enable Bit .0 0 Disable interrupt 1 Enable interrupt P3.
CONTROL REGISTERS S3C9228/P9228 P3PUR –Port 3 Pull-up Resistors Enable Register F6H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W .7-.2 Not used for S3C9228/P9228 .1 P3.1's Pull-up Resistor Enable Bit .0 4-26 0 Disable pull-up resistor 1 Enable pull-up resistor P3.
S3C9228/P9228 CONTROL REGISTERS P3EDGE –Port 3 Interrupt Edge Selection Register F8H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – – – 0 0 Read/Write – – – – – – R/W R/W .7-.4 Not used for S3C9228/P9228 .1 P3.1's Interrupt State Setting Bit .0 0 Falling edge interrupt 1 Rising edge interrupt P3.
CONTROL REGISTERS S3C9228/P9228 P4CONH – Port 4 Control Register High Byte F9H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-28 P4.7/SEG11 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P4.
S3C9228/P9228 CONTROL REGISTERS P4CONL–Port 4 Control Register Low Byte FAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 P4.3/SEG7 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P4.
CONTROL REGISTERS S3C9228/P9228 P5CONH – Port 5 Control Register High Byte FBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-30 P5.7/SEG19/COM4 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P5.
S3C9228/P9228 CONTROL REGISTERS P5CONL – Port 5 Control Register Low Byte FCH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 P5.3/SEG15 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P5.
CONTROL REGISTERS S3C9228/P9228 P6CON – Port 6 Control Register High Byte FDH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7-.6 .5-.4 .3-.2 .1-.0 4-32 P6.3/COM0 Configuration Bits 0 0 Input mode 0 1 Push-pull output 1 0 N-channel open-drain output 1 1 Input, pull-up mode P6.
S3C9228/P9228 CONTROL REGISTERS SIOCON — SIO Control Register E1H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W R/W – Read/Write .7 .6 .5 .4 .3 .2 .1 .0 SIO Shift Clock Selection Bit 0 Internal clock (P.
CONTROL REGISTERS S3C9228/P9228 STPCON – Stop Control Register E0H Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read/Write .7 Stop Control Bits 1 0 1 0 0 Other values 1 0 1 Enable Stop instruction Disable Stop instruction NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP instruction will not execute.
S3C9228/P9228 CONTROL REGISTERS SYM — System Mode Register DFH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – – – – 0 0 0 0 Read/Write – – – – R/W R/W R/W R/W .7-.4 Not used for S3C9228/P9228 .3 Global Interrupt Enable Bit .2-.
CONTROL REGISTERS S3C9228/P9228 TACON — Timer 1/A Control Register BBH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W R/W – Read/Write .7 .6-.4 .3 .2 .1 .
S3C9228/P9228 CONTROL REGISTERS TBCON — Timer B Control Register BAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value – 0 0 0 0 0 0 – Read/Write – R/W R/W R/W R/W R/W R/W – .7 Not used for S3C9228/P9228 .6-.4 Timer B Clock Selection Bits .3 .2 .1 .
CONTROL REGISTERS S3C9228/P9228 WTCON — Watch Timer Control Register DAH Bit Identifier .7 .6 .5 .4 .3 .2 .1 .0 RESET Value 0 0 0 0 0 0 0 – R/W R/W R/W R/W R/W R/W R/W – Read/Write .7 .6 .5-.4 .3-.2 .1 .0 4-38 Watch Timer Clock Selection Bit 0 Select main clock divided by 27 (fx/128) 1 Select sub clock (fxt) Watch Timer Interrupt Enable Bit 0 Disable watch timer interrupt 1 Enable watch timer interrupt Buzzer Signal Selection Bits 0 0 0.
S3C9228/P9228 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H–0001H. VECTOR SOURCES S1 0000H 0001H S2 S3 Sn NOTES: 1. The SAM88RCRI interrupt has only one vector address (0000H-0001H). 2. The number of Sn value is expandable. Figure 5-1.
INTERRUPT STRUCTURE S3C9228/P9228 INTERRUPT PENDING FUNCTION TYPES When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there is not a interrupt priority register in SAM87RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine.
S3C9228/P9228 INTERRUPT STRUCTURE INTERRUPT SOURCE SERVICE SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request pending bit to "1". 2. The CPU generates an interrupt acknowledge signal. 3. The service routine starts and the source's pending flag is cleared to "0" by software. 4. Interrupt priority must be determined by software polling method.
INTERRUPT STRUCTURE S3C9228/P9228 INTERRUPT STRUCTURE The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources: — Timer 1/A interrupt — Timer B interrupt — SIO interrupt — Watch Timer interrupt — Four external interrupts for port 0 — Four external interrupts for port 1 — Two external interrupts for port 3 5-4 S3C9228/P9228
S3C9228/P9228 INTERRUPT STRUCTURE Vector Enable/Disable Pending Sources INTPND1.0 P0.0 External Interript INTPND1.1 P0.1 External Interript INTPND1.2 P0.2 External Interript INTPND1.3 P0.3 External Interript INTPND1.4 P1.0 External Interript INTPND1.5 P1.1 External Interript INTPND1.6 P1.2 External Interript INTPND1.7 P1.3 External Interrupt INTPND2.0 Timer 1/A Interrupt INTPND2.1 Timer B Interrupt INTPND2.2 SIO Interrupt INTPND2.3 Watch Timer Interrupt INTPND2.4 P3.
INTERRUPT STRUCTURE Programming Tip — S3C9228/P9228 How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. LD • • • INTPND1, #11111011B ; Clear P0.2's interrupt pending bit INTPND2, #11110111B ; Clear watch timer interrupt pending bit IRET 2.
S3C9228/P9228 6 SAM88RCRI INSTRUCTION SET SAM88RCRI INSTRUCTION SET OVERVIEW The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file.
SAM88RI INSTRUCTION SET S3C9228/P9228 Table 6-1.
S3C9228/P9228 SAM88RCRI INSTRUCTION SET Table 6-1.
SAM88RI INSTRUCTION SET S3C9228/P9228 FLAGS REGISTER (FLAGS) The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 – FLAGS.7, can be tested and used with conditional jump instructions; FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register.
S3C9228/P9228 SAM88RCRI INSTRUCTION SET INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag 0 Cleared to logic zero 1 Set to logic one * Set or cleared according to operation – Value is unaffected x Value is undefined Table 6-3.
SAM88RI INSTRUCTION SET S3C9228/P9228 Table 6-4. Instruction Notation Conventions Notation cc Actual Operand Range Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, ..., 14) R Register or working register reg or Rn (reg = 0–255, n = 0–15) Register pair or working register pair reg or RRp (reg = 0–254, even number only, where p = 0, 2, ...
S3C9228/P9228 SAM88RCRI INSTRUCTION SET Table 6-5.
SAM88RI INSTRUCTION SET S3C9228/P9228 Table 6-5.
S3C9228/P9228 SAM88RCRI INSTRUCTION SET CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
SAM88RI INSTRUCTION SET S3C9228/P9228 INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing.
S3C9228/P9228 ADC — SAM88RCRI INSTRUCTION SET Add With Carry ADC dst,src Operation: dst ¨ dst + src + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two'scomplement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands.
SAM88RI INSTRUCTION SET ADD — S3C9228/P9228 Add ADD dst,src Operation: dst ¨ dst + src The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Z: S: V: Set if there is a carry from the most significant bit of the result; cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
S3C9228/P9228 AND — SAM88RCRI INSTRUCTION SET Logical AND AND dst,src Operation: dst ¨ dst AND src The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
SAM88RI INSTRUCTION SET S3C9228/P9228 CALL — Call Procedure CALL dst Operation: SP @SP SP @SP PC ¨ ¨ ¨ ¨ ¨ SP – 1 PCL SP –1 PCH dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure.
S3C9228/P9228 CCF — SAM88RCRI INSTRUCTION SET Complement Carry Flag CCF Operation: C ¨ NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected.
SAM88RI INSTRUCTION SET CLR — S3C9228/P9228 Clear CLR dst Operation: dst ¨ "0" The destination location is cleared to "0". Flags: No flags are affected.
S3C9228/P9228 COM — SAM88RCRI INSTRUCTION SET Complement COM dst Operation: dst ¨ NOT dst The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result bit 7 is set; cleared otherwise. Always reset to "0". Unaffected. Unaffected.
SAM88RI INSTRUCTION SET CP — S3C9228/P9228 Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Z: S: V: Set if a "borrow" occurred (src > dst); cleared otherwise. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise.
S3C9228/P9228 DEC — SAM88RCRI INSTRUCTION SET Decrement DEC dst Operation: dst ¨ dst – 1 The contents of the destination operand are decremented by one. Flags: C: Z: S: V: Unaffected. Set if the result is "0"; cleared otherwise. Set if result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is, dst value is –128(80H) and result value is +127(7FH); cleared otherwise. D: Unaffected. H: Unaffected.
SAM88RI INSTRUCTION SET DI — S3C9228/P9228 Disable Interrupts DI Operation: SYM (2) ¨ 0 Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: No flags are affected.
S3C9228/P9228 EI — SAM88RCRI INSTRUCTION SET Enable Interrupts EI Operation: SYM (2) ¨ 1 An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: No flags are affected.
SAM88RI INSTRUCTION SET IDLE — S3C9228/P9228 Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: opc Example: The instruction IDLE stops the CPU clock but not the system clock.
S3C9228/P9228 INC — SAM88RCRI INSTRUCTION SET Increment INC dst Operation: dst ¨ dst + 1 The contents of the destination operand are incremented by one. Flags: C: Z: S: V: Unaffected. Set if the result is "0"; cleared otherwise. Set if the result is negative; cleared otherwise. Set if arithmetic overflow occurred, that is dst value is +127(7FH) and result is –128(80H); cleared otherwise. D: Unaffected. H: Unaffected.
SAM88RI INSTRUCTION SET IRET — S3C9228/P9228 Interrupt Return IRET IRET Operation: FLAGS ¨ @SP SP ¨ SP + 1 PC ¨ @SP SP ¨ SP + 2 SYM(2) ¨ 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred).
S3C9228/P9228 JP — SAM88RCRI INSTRUCTION SET Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC ¨ dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair.
SAM88RI INSTRUCTION SET JR — S3C9228/P9228 Jump Relative JR cc,dst Operation: If cc is true, PC ¨ PC + dst If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed (See list of condition codes).
S3C9228/P9228 LD — SAM88RCRI INSTRUCTION SET Load LD dst,src Operation: dst ¨ src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected.
SAM88RI INSTRUCTION SET LD — S3C9228/P9228 Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD LD LD LD LD LD LD LD LD LD LD LD 6-28 R0,#10H → R0,01H → 01H,R0 → R1,@R0 → @R0,R1 → 00H,01H → 02H,@00H → 00H,#0AH → @00H,#10H → @00H,02H → R0,#LOOP[R1]→ #LOOP[R0],R1→ R0 = 10H R0 = 20H, register 01H = 20H Register 01H = 01H, R0 = 01H R1 = 20H, R0 = 01H R0 = 01H, R1 = 0AH, register 01H = 0AH Register 0
S3C9228/P9228 SAM88RCRI INSTRUCTION SET LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst ¨ src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst src 1.
SAM88RI INSTRUCTION SET LDC/LDE — S3C9228/P9228 Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H.
S3C9228/P9228 SAM88RCRI INSTRUCTION SET LDCD/LDED — LDCD/LDED dst,src Operation: dst ¨ src Load Memory and Decrement rr ¨ rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.
SAM88RI INSTRUCTION SET LDCI/LDEI — S3C9228/P9228 Load Memory and Increment LDCI/LDEI dst,src Operation: dst ¨ src rr ¨ rr + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.
S3C9228/P9228 NOP — SAM88RCRI INSTRUCTION SET No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 FF When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.
SAM88RI INSTRUCTION SET OR — S3C9228/P9228 Logical OR OR dst,src Operation: dst ¨ dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3C9228/P9228 POP — SAM88RCRI INSTRUCTION SET Pop From Stack POP dst Operation: dst ¨ @SP SP ¨ SP + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected.
SAM88RI INSTRUCTION SET S3C9228/P9228 PUSH — Push To Stack PUSH src Operation: SP ¨ SP – 1 @SP ¨ src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No flags are affected.
S3C9228/P9228 RCF — SAM88RCRI INSTRUCTION SET Reset Carry Flag RCF RCF Operation: C ¨ 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: opc Example: Bytes Cycles Opcode (Hex) 1 4 CF Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero.
SAM88RI INSTRUCTION SET RET — S3C9228/P9228 Return RET Operation: PC ¨ @SP SP ¨ SP + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: No flags are affected.
S3C9228/P9228 RL — SAM88RCRI INSTRUCTION SET Rotate Left RL dst Operation: C ¨ dst (7) dst (0) ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise.
SAM88RI INSTRUCTION SET RLC — S3C9228/P9228 Rotate Left Through Carry RLC dst Operation: dst (0) ¨ C C ¨ dst (7) dst (n + 1) ¨ dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the most significant bit position (bit 7) was "1". Set if the result is "0"; cleared otherwise.
S3C9228/P9228 RR SAM88RCRI INSTRUCTION SET — Rotate Right RR dst Operation: C ¨ dst (0) dst (7) ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1". Set if the result is "0"; cleared otherwise.
SAM88RI INSTRUCTION SET RRC — S3C9228/P9228 Rotate Right Through Carry RRC dst Operation: dst (7) ¨ C C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). 7 0 C Flags: C: Z: S: V: Set if the bit rotated from the least significant bit position (bit zero) was "1".
S3C9228/P9228 SBC — SAM88RCRI INSTRUCTION SET Subtract With Carry SBC dst,src Operation: dst ¨ dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand.
SAM88RI INSTRUCTION SET SCF — S3C9228/P9228 Set Carry Flag SCF Operation: C ¨ 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: opc Example: The statement SCF sets the carry flag to logic one.
S3C9228/P9228 SRA — SAM88RCRI INSTRUCTION SET Shift Right Arithmetic SRA dst Operation: dst (7) ¨ dst (7) C ¨ dst (0) dst (n) ¨ dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. 7 6 0 C Flags: C: Z: S: V: D: H: Set if the bit shifted from the LSB position (bit zero) was "1".
SAM88RI INSTRUCTION SET STOP — S3C9228/P9228 Stop Operation STOP Operation: The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or External interrupt input.
S3C9228/P9228 SUB — SAM88RCRI INSTRUCTION SET Subtract SUB dst,src Operation: dst ¨ dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Z: S: V: Set if a "borrow" occurred; cleared otherwise. Set if the result is "0"; cleared otherwise.
SAM88RI INSTRUCTION SET TCM — S3C9228/P9228 Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result.
S3C9228/P9228 TM — SAM88RCRI INSTRUCTION SET Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Z: S: V: D: H: Unaffected.
SAM88RI INSTRUCTION SET S3C9228/P9228 XOR — Logical Exclusive OR XOR dst,src Operation: dst ¨ dst XOR src The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Z: S: V: D: H: Unaffected. Set if the result is "0"; cleared otherwise.
S3C9228/P9228 7 CLOCK CIRCUITS CLOCK CIRCUITS OVERVIEW The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency, is determined by CLKCON register settings.
CLOCK CIRCUITS S3C9228/P9228 SUB OSCILLATOR CIRCUITS MAIN OSCILLATOR CIRCUITS XIN XTIN XOUT XTOUT 32.768 kHz Figure 7-1. Crystal/Ceramic Oscillator XIN Figure 7-4. Crystal/Ceramic Oscillator XTIN XOUT XTOUT Figure 7-2. External Oscillator XIN R XOUT Figure 7-3. RC Oscillator 7-2 Figure 7-5.
S3C9228/P9228 CLOCK CIRCUITS CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When the fx is selected as system clock).
CLOCK CIRCUITS S3C9228/P9228 SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following functions: — Oscillator IRQ wake-up function enable/disable — Oscillator frequency divide-by value CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release (This is called the “IRQ wake-up” function). The IRQ “wake-up” enable bit is CLKCON.7.
S3C9228/P9228 CLOCK CIRCUITS OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions: — System clock selection — Main oscillator control — Sub oscillator control OSCCON.0 register settings select Main clock or Sub clock as system clock. After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0". The main oscillator can be stopped or run by setting OSCCON.3.
CLOCK CIRCUITS S3C9228/P9228 SWITCHING THE CPU CLOCK Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the system clock. OSCCON .3 start or stop main clock oscillation, and OSCCON.
S3C9228/P9228 CLOCK CIRCUITS STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B". Stop Control Register (STPCON) E0H, R/W MSB .7 .6 .5 .4 .3 .2 .1 .
CLOCK CIRCUITS S3C9228/P9228 NOTES 7-8
RESET and POWER-DOWN S3C9228/P9228 8 RESET and POWER-DOWN SYSTEM RESET OVERVIEW During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C9228/P9228 into a known operating status.
RESET and POWER-DOWN S3C9228/P9228 POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But the watch timer and LCD controller will not halted in stop mode if the sub clock is selected as watch timer clock source. The data stored in the internal register file are retained in stop mode.
S3C9228/P9228 RESET and POWER-DOWN Using an Internal Interrupt to Release Stop Mode An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release stop mode. That is, you had better use the idle instruction instead of stop one when sub clock is selected as the system clock.
RESET and POWER-DOWN S3C9228/P9228 HARDWARE RESET VALUES Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values: — A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively. — An 'x' means that the bit value is undefined following RESET.
RESET and POWER-DOWN S3C9228/P9228 Table 8-1.
RESET and POWER-DOWN S3C9228/P9228 NOTES 8-6
S3C9228/P9228 9 I/O PORTS I/O PORTS OVERVIEW The S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required.
I/O PORTS S3C9228/P9228 PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1. Table 9-2.
S3C9228/P9228 I/O PORTS PORT 0 Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P0.0-P0.3): TAOUT,T1CLK, BUZ, INT — High-nibble pins (P0.4-P0.
I/O PORTS S3C9228/P9228 Port 0 Control Register (P0CON) EBH, Page 0, R/W MSB .7 .6 P0.3/BUZ (INT) .5 .4 P0.2 (INT) .3 .2 .1 .0 LSB P0.1/T1CLK P0.0/TAOUT (INT) (INT) P0CON bit-pair pin configuration settings: Schmitt trigger input mode (T1CLK) Push-pull output mode 00 01 10 11 N-channel open-drain output mode Alternative function (TAOUT, BUZ) Figure 9-2. Port 0 Control Register (P0CON) Port 0 Interrupt Control Register (P0INT) EDH, Page 0, R/W MSB .7 .6 .5 Not used .4 .3 .2 .1 .
S3C9228/P9228 I/O PORTS Port 0 Interrupt Pending Bits (INTPND1.3-.0) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.0 (INT) (INT) (INT) (INT) (INT) (INT) (INT) (INT) INTPND1 bit configuration settings: 0 No interrupt pending (when read), clear pending bit (when write) Interrupt is pending (when read) 1 Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0) Port 0 Interrupt Edge Selection Register (P0EDGE) EEH, Page 0, R/W MSB .7 .6 .5 .4 .3 .
I/O PORTS S3C9228/P9228 PORT 1 Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0. P1.0-P1.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P1.0-P1.3): AD0-AD3, INT Port 1 Control Register (P1CON) Port 1 has a 8-bit control register: P1CON for P1.0-P1.3.
S3C9228/P9228 I/O PORTS Port 1 Interrupt Control Register (P1INT) F1H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT) Not used P1INT bit configuration settings: 0 1 Disable interrupt Enable interrupt Figure 9-8. Port 1 Interrupt Control Register (P1INT) Port 1 Interrupt Pending Bits (INTPND1.7-.4) D6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 P1.2 P1.1 P1.0 P0.3 P0.2 P0.1 P0.
I/O PORTS S3C9228/P9228 Port 1 Interrupt Edge Selection Register (P1EDGE) F2H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P1.3 P1.2 P1.1 P1.0 (INT) (INT) (INT) (INT) Not used P1EDGE bit configuration settings: 0 Falling edge detection Rising edge detection 1 Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE) Port 1 Pull-up Control Register (P1PUR) F0H, Page 0, R/W MSB .7 .6 .5 Not used .4 .3 .2 .1 .0 P1.3 P1.2 P1.1 P1.
S3C9228/P9228 I/O PORTS PORT 2 Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0. P2.0-P2.3 can serve as inputs (with or without pullup), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P2.0-P2.3): SCK, SO, SI, SEG0-SEG1 Port 2 Control Register (P2CON) Port 2 has a 8-bit control register: P2CON for P2.0-P2.3.
I/O PORTS S3C9228/P9228 Port 2 Pull-up Control Register (P2PUR) F4H, Page 0, R/W MSB .7 .6 .5 Not used .4 .3 .2 .1 .0 P2.3 P2.2 P2.1 P2.0 LSB P2PUR bit configuration settings: 0 1 Disable pull-up resistor Enable pull-up resistor Figure 9-13.
S3C9228/P9228 I/O PORTS PORT 3 Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0. P3.0-P3.1 can serve as inputs (with or without pullup, and high impedance input), as outputs (push-pull or open-drain) or you can be configured the following functions. — Low-nibble pins (P3.0-P3.1): SEG2-SEG3, INTP Port 3 Control Register (P3CON) Port 3 has a 8-bit control register: P3CON for P3.
I/O PORTS S3C9228/P9228 Port 3 Interrupt Control Register (P3INT) F7H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.1 P3.0 (INTP) (INTP) Not used P3INT bit configuration settings: 0 1 Disable interrupt Enable interrupt Figure 9-15. Port 3 Interrupt Control Register (P3INT) Port 3 Interrupt Pending Bits (INTPND2.5-.4) D7H, Page 0, R/W MSB .7 .6 Not used .5 .4 P3.0 (INTP) .3 .2 SIO P3.0 (INTP) Watch Timer .1 .
S3C9228/P9228 I/O PORTS Port 3 Interrupt Edge Selection Register (P3EDGE) F8H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB P3.1 P3.0 (INTP) (INTP) Not used P3EDGE bit configuration settings: 0 1 Falling edge detection Rising edge detection Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE) Port 3 Pull-up Control Register (P3PUR) F6H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 Not used .1 .0 P3.1 P3.
I/O PORTS S3C9228/P9228 PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: — Low-nibble pins (P4.0-P4.3): SEG4-SEG7 — High-nibble pins (P4.4-P4.
S3C9228/P9228 I/O PORTS PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: — Low-nibble pins (P5.0-P5.3): SEG12-SEG15 — High-nibble pins (P5.4-P5.
I/O PORTS S3C9228/P9228 PORT 6 Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT: — Low-nibble pins (P6.0-P6.3): COM0-COM3 Port 6 Control Register (P6CON) Port 6 has a 8-bit control register: P6CONH for P6.0-P6.3.
S3C9228/P9228 (Preliminary Spec) 10 BASIC TIMER BASIC TIMER OVERVIEW Basic timer (BT) can be used in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.
BASIC TIMER S3C9228/P9228 (Preliminary Spec) BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addressable using Register addressing mode. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of f xx/4096.
S3C9228/P9228 (Preliminary Spec) BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than “1010B”. (The “1010B” value disables the watchdog function.) A reset clears BTCON to “00H”, automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.
BASIC TIMER S3C9228/P9228 (Preliminary Spec) RESET or STOP Bit 1 Bits 3, 2 Basic Timer Control Register (Write '1010xxxxB' to Disable) Data Bus fXX/4096 Clear fXX/1024 fXX DIV fXX/128 MUX 8-Bit Up Counter (BTCNT, Read-Only) OVF fXX/16 R Start the CPU (note) Bit 0 NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). Figure 10-2.
S3C9228/P9228 11 TIMER 1 TIMER 1 ONE 16-BIT TIMER MODE (TIMER 1) The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers. — One 16-bit timer mode (Timer 1) — Two 8-bit timers mode (Timer A and B) OVERVIEW The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate TACON setting.
TIMER 1 S3C9228/P9228 Timer 1 Control Register (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer) — Select the timer 1 input clock frequency — Clear the timer 1 counter, TACNT and TBCNT — Enable the timer 1 interrupt TACON is located in page 0, at address BBH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H".
S3C9228/P9228 TIMER 1 BTCON.0 TACON.6-.4 1/512 R TACON.3 Data Bus 1/256 TACON.2 fxx (XIN or XT IN) DIV 1/64 1/8 1/1 fxt M U LSB TBCNT MSB Clear TACNT R TACON.1 Match X 16-Bit Comparator T1CLK LSB MSB TBDATA TADATA Buffer Buffer INTPND2.0 T1INT TAOUT Match Signal Counter clear signal TBDATA TADATA Data Bus NOTE: When one 16-bit timer mode (TACON.7 <- "1": Timer 1) Figure 11-2.
TIMER 1 S3C9228/P9228 TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.
S3C9228/P9228 TIMER 1 TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3. A reset clears TBCON to "00H".
TIMER 1 S3C9228/P9228 Timer B Control Register (TBCON) BAH, R/W MSB .7 Not used .6 .5 .4 .3 .2 .1 .
S3C9228/P9228 TIMER 1 FUNCTION DESCRIPTION Interval Timer Function (Timer A and Timer B) The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT). The timer A match interrupt pending condition (INTPND2.0) and the timer B match interrupt pending condition (INTPND2.1) must be cleared by software in the application's interrupt service by means of writing a "0" to the INTPND2.0 and INTPND2.1 interrupt pending bit.
TIMER 1 S3C9228/P9228 BTCON.0 R TACON.6-.4 1/512 1/256 TACON.3 Data Bus TACON.2 fxx (XIN or XT IN) 1/64 DIV M LSB MSB 1/8 U TACNT (8-Bit Up-Counter) R 1/1 X TACON.1 Match 8-Bit Comparator fxt T1CLK/ P0.1 Clear LSB INTPND2.0 TAINT TAOUT MSB TADATA Buffer Match Signal Counter Clear Signal TADATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A) Figure 11-5.
S3C9228/P9228 TIMER 1 BTCON.0 R TBCON.6-.4 1/512 1/256 fxx (XIN or XTIN) DIV 1/64 TBCON.3 Data Bus M U 1/8 TBCON.2 LSB MSB TBCNT (8-Bit Up-Counter) R X TBCON.1 Match 1/1 8-Bit Comparator fxt Clear LSB INTPND2.1 TBINT MSB TBDATA Buffer Match Signal Counter Clear Signal TBDATA Register Data Bus NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B) Figure 11-6.
TIMER 1 S3C9228/P9228 NOTES 11-10
S3C9228/P9228 12 WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt, then set the WTCON.6 to “1”. The watch timer overflow interrupt pending condition (INTPND2.
WATCH TIMER S3C9228/P9228 WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode. A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock.
S3C9228/P9228 WATCH TIMER WATCH TIMER CIRCUIT DIAGRAM WTCON.7 WTCON.6 WT INT Enable BUZ (P0.3) WTCON.6 WTCON.5 8 MUX WTCON.4 WTCON.3 WTCON.2 WTCON.1 WTINT fW/64 (0.5 kHz) fW/32 (1 kHz) fW/16 (2 kHz) fW/8 (4 kHz) Enable/Disable Selector Circuit INTPND2.3 WTCON.0 Clock Selector fW 32.768 kHz Frequency Dividing Circuit fW/27 fW/213 fW/214 fW/215 (1 Hz) fLCD = 2048 Hz fxt fx/128 fX = Main clock (where fx = 4.19 MHz) fxt = Sub clock (32,768 Hz) fW = Watch timer frequency Figure 12-2.
WATCH TIMER S3C9228/P9228 NOTES 12-4
S3C9228/P9228 13 LCD CONTROLLER/DRIVER LCD CONTROLLER/DRIVER OVERVIEW The S3C9228/P9228 microcontroller can directly drive an up-to-128-dot (16segments x 8 commons) LCD panel.
LCD CONTROLLER/DRIVER S3C9228/P9228 LCD CIRCUIT DIAGRAM 16 Port Latch SEG15/P5.3 Display RAM (Page1) SEG Control 160 16 MUX or Data BUS 4 LPOT 8 COM Control or selector COM Control LMOD LCD Voltage Control Port Latch Port 3 Control 2 Figure 13-2. LCD Circuit Diagram 13-2 SEG0/P2.1 fLCD Timing Controller Port Latch Selector COM7/SEG16/P5.4 COM4/SEG19/P5.7 COM3/P6.0 COM0/P6.3 P3.1/INTP/SEG2 P3.
S3C9228/P9228 LCD CONTROLLER/DRIVER LCD RAM ADDRESS AREA RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off. Display RAM data are sent out through segment pins SEG0–SEG19 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use.
LCD CONTROLLER/DRIVER S3C9228/P9228 LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode. It has the following control functions.
S3C9228/P9228 LCD CONTROLLER/DRIVER LCD PORT CONTROL REGISTER The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET, a LPOT values are cleared to "0". LCD Port Control Register D8H, R/W MSB .7 .6 .5 .4 .3 .2 .1 Not used .0 LSB SEG0/P2.1 selection bit: 0 = SEG port 1 = Normal I/O port SEG4-SEG19 and COM0-COM3 selection bits: SEG1/P2.0 selection bit: 000 = P4.0-P6.3: LCD signal pins 0 = SEG port 001 = P4.0-P4.3: Normal I/O, P4.4-P6.
LCD CONTROLLER/DRIVER S3C9228/P9228 LCD VOLTAGE DIVIDING RESISTORS 1/5 Bias 1/4 Bias 1/3 Bias S3C9228/P9228 S3C9228/P9228 S3C9228/P9228 VDD LMOD.4 VDD LMOD.4 VLC1 VLC2 VLC3 VLC4 VLC5 VSS VDD LMOD.4 VLC1 R R R R R VLC2 VLC3 VLC4 VLC5 VSS VLC1 R R R R R VLC2 VLC3 VLC4 VLC5 VSS R R R R R Figure 13-6. Internal Voltage Dividing Resistor Connection COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.
S3C9228/P9228 LCD CONTROLLER/DRIVER COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 FR VDD VSS 1 Frame S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 COM0 VDD VLC1 VLC2 (VLC3) VLC4 VSS COM1 VDD VLC1 VLC2 (VLC3) VLC4 VSS COM2 VDD VLC1 VLC2 (VLC3) VLC4 VSS SEG0 VDD VLC1 VLC2 (VLC3) VLC4 VSS + VDD SEG0-COM0 + 1/4VLCD 0V - 1/4VLCD -VLCD Figure 13-7.
LCD CONTROLLER/DRIVER S3C9228/P9228 SEG0 SEG1 0 1 2 3 0 1 2 3 COM0 VDD VSS 1 Frame COM1 COM2 COM0 COM3 VDD VLC1(VLC2) VLC3(VLC4) VSS VDD COM1 COM2 COM3 VLC1(VLC2) VLC3(VLC4) VSS VDD VLC1(VLC2) VLC3(VLC4) VSS VDD VLC1(VLC2) VLC3(VLC4) VSS SEG0 VDD VLC1(VLC2) VLC3(VLC4) VSS SEG1 VDD VLC1(VLC2) VLC3(VLC4) VSS + VLCD COM0-SEG0 + 1/3 VLCD 0V - 1/3 V LCD - VLCD Figure 13-8.
S3C9228/P9228 SEG2 LCD CONTROLLER/DRIVER SEG1 SEG0 0 1 2 0 1 2 COM0 VDD VSS 1 Frame COM0 VDD VLC1(VLC2) VLC3(VLC4) VSS COM1 VDD VLC1(VLC2) VLC3(VLC4) VSS COM2 VDD VLC1(VLC2) VLC3(VLC4) VSS SEG0 VDD VLC1(VLC2) VLC3(VLC4) VSS SEG1 VDD VLC1(VLC2) VLC3(VLC4) VSS COM1 COM2 + VLCD COM0-SEG0 + 1/3 VLCD 0V - 1/3 VLCD - VLCD Figure 13-9.
LCD CONTROLLER/DRIVER S3C9228/P9228 NOTES 13-10
S3C9228/P9228 14 A/D CONVERTER 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values.
A/D CONVERTER S3C9228/P9228 CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit × 10-bit + set-up time = 50 clocks, 50 clock × 1.
S3C9228/P9228 A/D CONVERTER Conversion Data Register ADDATAH/ADDATAL D1H/D2H, Page 0, Read Only MSB .9 .8 .7 .6 .5 .4 .3 .2 LSB (ADDATAH) MSB - - - - - - .1 .0 LSB (ADDATAL) Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range VSS to VDD.
A/D CONVERTER S3C9228/P9228 VDD Analog Input Pin (VSS ≤ ADC input ≤ VDD) AD0-AD3 C 101 S3C9228 Figure 14-4.
S3C9228/P9228 15 SERIAL I/O INTERFACE SERIAL I/O INTERFACE OVERVIEW Serial I/O modules, SIO can interface with various types of external device that require serial data transfer.
SERIAL I/O INTERFACE S3C9228/P9228 SIO CONTROL REGISTERS (SIOCON) The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module.
S3C9228/P9228 SERIAL I/O INTERFACE SIO PRE-SCALER REGISTER (SIOPS) The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0. The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows: Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock. SIO Pre-scaler Register (SIOPS) E3H, Page 0, R/W MSB .7 .6 .5 .4 .3 .2 .1 .0 LSB Baud rate = (fXX/4)/(SIOPS + 1) Figure 15-2.
SERIAL I/O INTERFACE S3C9228/P9228 SERIAL I/O TIMING DIAGRAM (SIO) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Transmit Complete SIO INT Set SIOCON.3 Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0) SCK SI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 SO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Transmit Complete SIO INT Set SIOCON.3 Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.
S3C9228/P9228 16 ELECTRICAL DATA ELECTRICAL DATA OVERVIEW In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — D.C. electrical characteristics — Data retention supply voltage in Stop mode — Stop mode release timing when initiated by an external interrupt — Stop mode release timing when initiated by a Reset — I/O capacitance — A.C.
ELECTRICAL DATA S3C9228/P9228 Table 16-1. Absolute Maximum Ratings (TA = 25°C) Parameter Symbol Conditions Rating Unit Supply voltage VDD – – 0.3 to + 6.5 V Input voltage VIN – 0.3 to VDD + 0.3 V Output voltage VO – 0.3 to VDD + 0.
S3C9228/P9228 ELECTRICAL DATA Table 16-2. D.C. Electrical Characteristics (Continued) (TA = – 25°C to + 85°C, VDD = 2.0 V to 5.
ELECTRICAL DATA S3C9228/P9228 Table 16-2. D.C. Electrical Characteristics (Concluded) (TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V) Parameter Symbol Supply current (1) IDD1 IDD2 Conditions Min Typ Max Unit – 6.0 12.0 mA Run mode: VDD = 5 V ± 10% 8.0 MHz Crystal oscillator C1 = C2 = 22pF 4.19 MHz 3.0 6.0 VDD = 3 V ± 10% 8.0 MHz 2.5 5.0 4.19 MHz 1.5 3.0 Idle mode: VDD = 5 V ± 10% 8.0 MHz 1.3 3.0 Crystal oscillator C1 = C2 = 22pF 4.19 MHz 1.0 2.0 VDD = 3 V ± 10% 8.
S3C9228/P9228 ELECTRICAL DATA Table 16-3. Data Retention Supply Voltage in Stop Mode (TA = – 25 °C to + 85 °C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage VDDDR – 2.0 – 5.5 V Data retention supply current IDDDR – – 1 µA Stop mode, TA = 25 °C VDDDR = 2.0 V Idle Mode (Basic Timer Active) ~ ~ Stop Mode Normal Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instruction 0.8 VDD tWAIT NOTE: tWAIT is the same as 16 x 1/BT clock.
ELECTRICAL DATA S3C9228/P9228 RESET Occurs Oscillation Stabilization TIme ~ ~ Stop Mode Normal Operating Mode Data Retention Mode ~ ~ VDD VDDDR Execution of STOP Instrction RESET 0.8 VDD 0.2 VDD NOTE: tWAIT tWAIT is the same as 16 × 1/BT clock. Figure 16-2. Stop Mode Release Timing When Initiated by a RESET Table 16-4.
S3C9228/P9228 ELECTRICAL DATA Table 16-5. A.C. Electrical Characteristics (TA = – 25°C to + 85°C, VDD = 2.0 V to 5.
ELECTRICAL DATA S3C9228/P9228 Table 16-6. A/D Converter Electrical Characteristics (TA = – 25°C to + 85°C, VDD = 2.7 V to 5.5 V, VSS = 0 V) Parameter Symbol Conditions Min Typ Max Unit – 10 – bit VDD = 5.12 V – – ±3 LSB Resolution Total accuracy Integral linearity error ILE fxx = 8 MHz – – ±2 Differential linearity error DLE f CON = fxx/4 – – ±1 Offset error of top EOT – ±1 ±3 Offset error of bottom EOB – ±0.
S3C9228/P9228 ELECTRICAL DATA tRSL RESET 0.2 VDD Figure 16-4. Input Timing for RESET tKCY tKL tKH SCK 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI 0.2VDD tKSO SO Output Data Figure 16-5.
ELECTRICAL DATA S3C9228/P9228 Table 16-7. Main Oscillation Characteristics (TA = – 25°C to + 85°C) Oscillator Clock Configuration Crystal C1 XIN Parameter Test Condition Min Typ Max Units 2.7 V – 5.5 V 0.4 – 8 MHz 2.0 V – 5.5 V 0.4 – 4 2.7 V – 5.5 V 0.4 – 8 2.0 V – 5.5 V 0.4 – 4 2.7 V – 5.5 V 0.4 – 8 2.0 V – 5.5 V 0.4 – 4 Frequency 5.0 V 0.4 – 2 Frequency 3.0 V 0.
S3C9228/P9228 ELECTRICAL DATA Table 16-9. Main Oscillation Stabilization Time (TA = – 25 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit Crystal fx > 1 MHz – – 30 ms Ceramic Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage ranage. – – 10 ms External clock XIN input high and low width (tXH, tXL) 62.5 – 1250 ns 1/fx tXL tX XIN VDD-0.1 V 0.1 V Figure 16-6.
ELECTRICAL DATA S3C9228/P9228 Table 16-10. Sub Oscillation Stabilization Time (TA = – 25 °C to + 85 °C, VDD = 2.0 V to 5.5 V) Oscillator Test Condition Min Typ Max Unit – – – 10 s 5 – 15 µs Crystal External clock XTIN input high and low width (tXH, tXL) 1/fxt tXTL tXTH XTIN VDD-0.1 V 0.1 V Figure 16-7.
S3C9228/P9228 ELECTRICAL DATA Instruction Clock fx (Main/Sub oscillation frequency) 2 MHz 8 MHz 1.0 MHz 4 MHz 400 kHz 6.25 kHz (main)/8.2 kHz(sub) 400 kHz (main)/32.8 kHz(sub) 1 2 2.7 5.5 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 16-8.
ELECTRICAL DATA S3C9228/P9228 NOTES 16-14
S3C9228/P9228 17 MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package. #22 0.2 5 42-SDIP-600 +0 - 0 .1 .05 0-15 15.24 14.00 ± 0.2 #42 (1.77) NOTE: 1.00 ± 0.1 5.08 MAX 39.10 ± 0.2 0.1 3.30 ± 0.3 0.2 39.50 MAX 0.50 ± 3.50 ± #21 0.51 MIN #1 1.78 Dimensions are in millimeters. Figure 17-1.
MECHANICAL DATA S3C9228/P9228 13.20 ± 0.3 0-8 10.00 ± 0.2 10.00 ± 0.2 + 0.10 - 0.05 0.10 MAX 44-QFP-1010B 0.80 ± 0.20 13.20 ± 0.3 0.15 #44 #1 + 0.10 0.35 - 0.05 0.80 0.05 MIN (1.00) 2.05 ± 0.10 2.30 MAX NOTE: Dimensions are in millimeters. Figure 17-2.
S3C9228/P9228 S3P9228 OTP 18 S3P9228 OTP OVERVIEW The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format. 44 43 42 41 40 39 38 37 36 35 34 P0.5 P0.4 P0.3/BUZ/INT P0.2/INT P0.1/T1CLK/INT P0.0/TAOUT/INT COM0/P6.3 COM1/P6.2 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.
S3P9228 OTP S3C9228/P9228 S3C9228 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 (42-SDIP) COM1/P6.2 COM0/P6.3 P0.0/TAOUT/INT P0.1/T1CLK/INT P0.2/INT P0.3/BUZ/INT P1.0/AD0/INT P1.1/AD1/INT SDAT/P1.2/AD2/INT SCLK/P1.3/AD3/INT VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT RESET /RESET P2.3 P2.2/SI SEG0/P2.1/SO 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 COM2/P6.1 COM3/P6.0 COM4/SEG19/P5.7 COM5/SEG18/P5.6 COM6/SEG17/P5.5 COM7/SEG16/P5.4 SEG15/P5.3 SEG14/P5.2 SEG13/P5.1 SEG12/P5.
S3C9228/P9228 S3P9228 OTP Table 18-1. Descriptions of Pins Used to Read/Write the EPROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P1.2 SDAT 3 (9) I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P1.3 SCLK 4 (10) I/O Serial clock pin. Input only pin. TEST VPP(TEST) 9 (15) I Power supply pin for EPROM cell writing (indicates that OTP enters into the writing mode). When 12.
S3P9228 OTP S3C9228/P9228 Table 18-4. D.C. Electrical Characteristics (TA = – 25°C to + 85°C, VDD = 2.0 V to 5.5 V) Parameter Symbol Supply current (1) IDD1 IDD2 Conditions Min Typ Max Unit – 6.0 12.0 mA Run mode: VDD = 5 V ± 10% 8.0 MHz Crystal oscillator C1 = C2 = 22pF 4.19 MHz 3.0 6.0 VDD = 3 V ± 10% 8.0 MHz 2.5 5.0 4.19 MHz 1.5 3.0 Idle mode: VDD = 5 V ± 10% 8.0 MHz 1.3 3.0 Crystal oscillator C1 = C2 = 22pF 4.19 MHz 1.0 2.0 VDD = 3 V ± 10% 8.0 MHz 0.8 1.6 4.
S3C9228/P9228 S3P9228 OTP Instruction Clock fx (Main/Sub oscillation frequency) 2 MHz 8 MHz 1.0 MHz 4 MHz 400 kHz 6.25 kHz (main)/8.2 kHz(sub) 400 kHz (main)/32.8 kHz(sub) 1 2 2.7 5.5 6 Supply Voltage (V) Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Figure 18-3.
S3P9228 OTP S3C9228/P9228 NOTES 18-6
S3C9228/P9228 19 DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used.
DEVELOPMENT TOOLS S3C9228/P9228 IBM-PC AT or Compatible RS-232C SMDS2+ Target Application System PROM/OTP Writer Unit RAM Break/Display Unit BUS Probe Adapter Trace/Timer Unit SAM8 Base Unit Power Supply Unit POD TB9228 Target Board EVA Chip Figure 19-1.
S3C9228/P9228 DEVELOPMENT TOOLS TB9228 TARGET BOARD The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system. TB9228 To User_VCC OFF REV.0 '2002.03.
DEVELOPMENT TOOLS S3C9228/P9228 Table 19-1. Power Selection Settings for TB9228 "To User_VCC" Settings Operating Mode Comments To User_VCC Off On TB9228 VCC Target System The SMDS2/SMDS2+ supplies VCC to the target board (evaluation chip) and the target system. VSS VCC SMDS2/SMDS2+ To User_VCC Off On TB9228 External VCC VSS Target System The SMDS2/SMDS2+ supplies VCC only to the target board (evaluation chip). The target system must have its own power supply.
S3C9228/P9228 DEVELOPMENT TOOLS SMDS2+ Selection (SAM8) In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available. Table 19-2. The SMDS2+ Tool Selection Setting "SW1" Setting SMDS2 Operating Mode SMDS2+ R/W R/W Target Board SMDS2+ Table 19-3.
DEVELOPMENT TOOLS S3C9228/P9228 J101 42-SDIP P6.2 P6.3 P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.1 NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 43 44 45 46 J102 44-QFP 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 50 49 48 47 P6.1 P6.0 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 P3.0 P3.1 P2.0 NC NC NC NC P1.0 P1.1 P1.2 P1.3 USER_VCC VSS NC NC VSS NC NC DEMO_RSTB P2.3 P2.2 P2.
S3C9228/P9228 DEVELOPMENT TOOLS Target Board Target System J101 50-Pin DIP Connector 1 J101 42 1 42 21 22 Target Cable for Connector Part Name: AP42SD Order Code: SM6538 21 22 Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package Target Board Target System J102 44 1 44 22 23 Target Cable for 50-pin Connector Part Name: AP50D-A Order Code: SM6305 22 23 50-Pin Connector 50-Pin Connector 1 J102 Figure 19-5.
DEVELOPMENT TOOLS S3C9228/P9228 NOTES 19-8