DDR3 SDRAM Unbuffered DIMM DDR3 SDRAM Specification 240pin Unbuffered DIMM based on 1Gb E-die 64/72-bit Non-ECC/ECC 78FBGA with Lead-Free & Halogen-Free (RoHS compliant) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY.
DDR3 SDRAM Unbuffered DIMM Table Contents 1.0 DDR3 Registered DIMM Ordering Information ...........................................................................5 2.0 Key Features .................................................................................................................................5 3.0 Address Configuration .................................................................................................................5 4.0 x64 DIMM Pin Configurations (Front side/Back Side) .
DDR3 SDRAM Unbuffered DIMM 14.0 IDD Specification Definition .....................................................................................................24 14.1 IDD SPEC Table ........................................................................................................................26 15.0 Input/Output Capacitance ........................................................................................................29 15.1 Non ECC UDIMM ..............................................
DDR3 SDRAM Unbuffered DIMM Revision History Revision Month Year History 1.0 December 2008 - First release 1.01 January 2009 - Corrected Module Physical Dimensions. 1.02 February 2009 - Added Tolerances to Physical Dimensions 1.03 July 2009 - Corrected Typo. 4 of 39 Rev. 1.
DDR3 SDRAM Unbuffered DIMM 1.
DDR3 SDRAM Unbuffered DIMM 4.
DDR3 SDRAM Unbuffered DIMM 5.
DDR3 SDRAM Unbuffered DIMM 6.
DDR3 SDRAM Unbuffered DIMM 8.0 Input/Output Functional Description Symbol Type Function CK0-CK1 CK0-CK1 SSTL CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK (Both directions of crossing) CKE0-CKE1 SSTL Activates the SDRAM CK signal when high and deactivates the CK signal when low.
DDR3 SDRAM Unbuffered DIMM 8.1 Address Mirroring Feature There is a via grid located under the DRAMs for wiring the CA signals (address, bank address, command, and control lines) to the DRAM pins. The length of the traces from the vias to the DRAMs places limitations on the bandwidth of the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3 modules, a scheme was defined to reduce the length of these traces.
DDR3 SDRAM Unbuffered DIMM 9.0 Function Block Diagram: 9.
DDR3 SDRAM Unbuffered DIMM 9.
DDR3 SDRAM Unbuffered DIMM 9.
DDR3 SDRAM Unbuffered DIMM 9.
DDR3 SDRAM Unbuffered DIMM 10.0 Absolute Maximum Ratings 10.1 Absolute Maximum DC Ratings Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to VSS -0.4 V ~ 1.975 V V 1,3 VDDQ Voltage on VDDQ pin relative to VSS -0.4 V ~ 1.975 V V 1,3 VIN, VOUT Voltage on any pin relative to VSS -0.4 V ~ 1.975 V V 1 TSTG Storage Temperature -55 to +100 °C 1, 2 Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DDR3 SDRAM Unbuffered DIMM 12.0 AC & DC Input Measurement Levels 12.1 AC & DC Logic Input Levels for Single-ended Signals Single Ended AC and DC input levels for Command and Address Symbol VIH.CA(DC) Parameter DDR3-1066 Min. DDR3-1333 Max. Min. Max. Unit Notes mV 1 DC input logic high VREF + 100 VDD VREF + 100 VDD VIL.CA(DC) DC input logic low VSS VREF - 100 VSS VREF - 100 mV 1 VIH.CA(AC) AC input logic high VREF + 175 - VREF + 175 - mV 1,2 VIL.
DDR3 SDRAM Unbuffered DIMM 12.2 VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in Figure 2. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements of VREF. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD.
DDR3 SDRAM Unbuffered DIMM 12.3 AC & DC Logic Input Levels for Differential Signals 12.3.1 Differential Signals Definition tDVAC Differential Input Voltage (i.e. DQS-DQS, CK-CK) VIH.DIFF.AC.MIN VIH.DIFF.MIN 0.0 half cycle VIL.DIFF.MAX VIL.DIFF.AC.MAX tDVAC time Figure 3. Definition of differential ac-swing and "time above ac level" tDVAC 12.3.
DDR3 SDRAM Unbuffered DIMM 12.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every half-cycle.
DDR3 SDRAM Unbuffered DIMM 12.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in below table. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the mid level between of VDD and VSS.
DDR3 SDRAM Unbuffered DIMM 13.0 AC & DC Output Measurement Levels 13.1 Single-ended AC & DC Output Levels Single Ended AC and DC output levels Symbol Parameter DDR3-1066/1333 Units VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x VDDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x VDDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x VDDQ V Notes VOH(AC) AC output high measurement level (for output SR) VTT + 0.
DDR3 SDRAM Unbuffered DIMM 13.4 DIfferential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below.
DDR3 SDRAM Unbuffered DIMM 14.0 IDD Specification Definition Symbol Description Operating One Bank Active-Precharge Current IDD0 CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 32 ; Data IO: MID-LEVEL; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,...
DDR3 SDRAM Unbuffered DIMM Symbol Description Self-Refresh Current: Extended Temperature Range (optional)f) IDD6ET TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Extendede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: MID-LEVEL Au
DDR3 SDRAM Unbuffered DIMM 14.
DDR3 SDRAM Unbuffered DIMM M391B2873EH1: 1GB(128Mx72) Module Symbol CF8 (DDR3-1066@CL=7) CH9 (DDR3-1333@CL=9) CK0 (DDR3-1600@CL=11) Unit IDD0 540 585 TBD mA IDD1 675 720 TBD mA IDD2P0(slow exit) 90 90 TBD mA IDD2P1(fast exit) 225 225 TBD mA IDD2N 270 315 TBD mA IDD2Q 270 315 TBD mA IDD3P(fast exit) 225 225 TBD mA IDD3N 405 450 TBD mA IDD4R 945 1125 TBD mA IDD4W 1035 1215 TBD mA IDD5B 1350 1440 TBD mA IDD6 90 90 TBD mA IDD7 1575 2070 TBD m
DDR3 SDRAM Unbuffered DIMM 15.0 Input/Output Capacitance 15.
DDR3 SDRAM Unbuffered DIMM 16.0 Electrical Characteristics and AC timing (0 °C
DDR3 SDRAM Unbuffered DIMM DDR3-1333 Speed Bins Speed DDR3-1333 CL-nRCD-nRP Parameter Internal read command to first data ACT to internal read or write delay time 9 -9 - 9 Units Symbol min max tAA 13.5 (13.125)5,9 20 ns tRCD 13.5 (13.125)5,9 - ns 5,9 PRE command period tRP 13.5 (13.125) - ns ACT to ACT or REF command period tRC 49.5 (49.125)5,9 - ns ACT to PRE command period CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 Note tRAS 36 9*tREFI ns 8 CWL = 5 tCK(AVG) 2.5 3.
DDR3 SDRAM Unbuffered DIMM DDR3-1600 Speed Bins Speed DDR3-1600 CL-nRCD-nRP Parameter 11-11-11 Units Symbol min max tAA 13.75 (13.125)5,9 20 ns tRCD 13.75 (13.125)5,9 - ns PRE command period tRP 13.75 (13.125)5,9 - ns ACT to ACT or REF command period tRC 48.75 (48.125)5,9 - ns Intermal read command to first data ACT to internal read or write delay time ACT to PRE command period CL = 6 CL = 7 CL = 8 CL = 9 CL = 10 CL = 11 Note tRAS 35 9*tREFI ns CWL = 5 tCK(AVG) 2.
DDR3 SDRAM Unbuffered DIMM 16.3.1 Speed Bin Table Notes Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); Note : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).
DDR3 SDRAM Unbuffered DIMM 17.
DDR3 SDRAM Unbuffered DIMM Speed Parameter DDR3-1066 Symbol DDR3-1333 MIN MAX DDR3-1600 MIN MAX MIN MAX Units Note Command and Address Timing DLL locking time tDLLK 512 - 512 - 512 - internal READ Command to PRECHARGE Command delay tRTP max (4nCK,7.5ns) - max (4nCK,7.5ns) - max (4nCK,7.5ns) - e Delay from start of internal write transaction to internal read command tWTR max (4nCK,7.5ns) - max (4nCK,7.5ns) - max (4nCK,7.
DDR3 SDRAM Unbuffered DIMM Speed Parameter DDR3-1066 DDR3-1333 DDR3-1600 Symbol MIN MAX MIN MAX MIN MAX tXP max (3nCK, 7.5ns) - max (3nCK,6ns) - max (3nCK,6ns) - tXPDLL max (10nCK, 24ns) - max (10nCK, 24ns) - max (10nCK, 24ns) - tCKE max (3nCK, 5.625ns) - max (3nCK, 5.
DDR3 SDRAM Unbuffered DIMM 17.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
DDR3 SDRAM Unbuffered DIMM 17.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register 5. Value must be rounded-up to next higher integer value 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7.
DDR3 SDRAM Unbuffered DIMM 18.0 Physical Dimensions 18.1 64Mbx16 based 64Mx64 Module (1 Rank) Units : Millimeters 9.50 128.95 2.30 17.30 SPD 30.00 ± 0.15 (4X)3.00 ± 0.1 133.35 ± 0.15 (2) 2.50 54.675 A B 47.00 71.00 Max 4.0 2.50 ± 0.20 1.270 ± 0.10 5.00 0.80 ± 0.05 3.80 2x 2.10 ± 0.15 0.2 ± 0.15 1.50±0.10 1.00 2.50 Detail A Detail B The used device is 64M x16 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B1G1646E-HC∗∗ * Note : Tolerances on all dimensions ±0.
DDR3 SDRAM Unbuffered DIMM 18.2 128Mbx8 based 128Mx64/x72 Module (1 Rank) Units : Millimeters 128.95 ECC SPD 17.30 9.50 N/A (for x64) 2.30 (for x72) 30.00 ± 0.15 (4X)3.00 ± 0.1 133.35 ± 0.15 (2) 2.50 54.675 A B 47.00 71.00 Max 4.0 2.50 ± 0.20 1.270 ± 0.10 5.00 0.80 ± 0.05 3.80 2x 2.10 ± 0.15 0.2 ± 0.15 1.50±0.10 1.00 2.50 Detail A Detail B The used device is 128M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B1G0846E-HC∗∗ * Note : Tolerances on all dimensions ±0.
DDR3 SDRAM Unbuffered DIMM 18.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks) Units : Millimeters 128.95 ECC SPD 17.30 9.50 N/A (for x64) 2.30 (for x72) 30.00 ± 0.15 (4X)3.00 ± 0.1 133.35 ± 0.15 (2) 2.50 54.675 A B 47.00 Max 4.0 71.00 N/A (for x64) ECC (for x72) 2.50 ± 0.20 1.270 ± 0.10 5.00 0.80 ± 0.05 3.80 2x 2.10 ± 0.15 0.2 ± 0.15 1.50±0.10 1.00 2.50 Detail A Detail B The used device is 128M x8 DDR3 SDRAM, FBGA.