Page 1/51 HiAllNC User Manual HiAllNC User Manual 2012/06/28
Page 2/51 SOMMAIRE / CONTENTS 1 OVERVIEW...................................................................................................................................................................5 1.1 OBJECT OF THE DOCUMENT.........................................................................................................................5 1.2 REFERENCE DOCUMENTS.............................................................................................................................5 1.
Page 3/51 7.2 Module handling .................................................................................................................................................42 NC 7.3 Customer’s product with HiAll ......................................................................................................................42 7.4 Analysis ...............................................................................................................................................................
Page 4/51 FIGURES LIST Figure 1: HiAllNC Block diagram .............................................................................................................................................7 Figure 2: Typical SIM schematic ...........................................................................................................................................12 Figure 3: SIM card signals.................................................................................................................
Page 5/51 1 OVERVIEW 1.1 OBJECT OF THE DOCUMENT The aim of this document is to provide technical guidelines to help the customer to design solutions based on NC HiAll module. 1.2 REFERENCE DOCUMENTS NC [1] URD1 5717.1 004 72589 - HiAll Technical Specification [2] URD1 5635.1 008 70248 - AT Command Set for SAGEMCOM Modules [3] URD1 5635.1 118 72618 – Radio Application Note for Hilo Modules NC [4] URD1 5696 3 001 72497 - HiLo -3GPS Technical Specification 1.
Page 6/51 HBM HDOP HSCSD HSDPA HSUPA HSPA+ IC IEEE I/O ISO ITU IVS JTAG Kbps LCD LED LTO Mbps MSD NAD PBCCH PCB PCM PCS PSAP PWM RAM RF RI RMS RTS RX SIM SMS SV TBC TTFF TX UART UMTS USB USSD VAD VM HiAllNC User Manual Human Body Model Horizontal Dilution Of Precision High Speed Circuit Switched Data High Speed Downlink Packet Access High Speed Uplink Packet Access Evolved High-Speed Packet Access Integrated Circuit Institute of Electrical and Electronics Engineers Input / Output International Standards O
page 7/51 2. BLOCK DIAGRAM Memory (Flash + RAM) VBAT GND VGPIO VBACKUP HiAllNC Baseband 850 900 GPIO x6 ADC x2 DATA JAVA apps SAW Filters 1800 1900 UART1 8pins UART0 4pins SPI JTAG PCM MIC_IN HSET_OUT HiAllNC GSM PA & Switch RF 2G_TX_ IND VM eCall library GNSS library LNA RF CTRL GNSS GSM Baseband IC SIM SAW Filter RF EXT_LNA_EN DATA PPS EXT SIM 16.369MHz 26MHz 32.
page 8/51 3. FUNCTIONAL INTEGRATION 3.1 POWER DOMAIN NC HiAll module has several power domains as defined below. • • • • • • • SIM I/Os VBACKUP Digital IOs VBAT MIC_IN HSET_OUT ADC 1.8V or 2.9V 3V 2.8V 3.3V to 4.5V 2.85V same as VBAT 2.
page 9/51 26 MIC_N Analog input 27 RESET Digital input 28 VBACKUP Power supply input/output 29 VBAT Power supply input 30 ADC1 Analog input 31 ADC0 Analog input 32 33 34 35 POK_IN SIM_VCC SIM_DATA SIM_CLK Digital input Power supply output Digital bi-directional buffer Digital output buffer 36 GPIO1 Digital bi-directional buffer 37 SPI_IRQ Digital input buffer RESERVED (futur use) GPS_EXT_LN A_EN RESERVED (futur use) microphone Differential input from microphone Module Reset Back
page 10/51 (3G compatibility) PCM_OUT PCM_IN RESERVED (3G compatibility) RESERVED (3G compatibility) RESERVED (3G compatibility) RESERVED (3G compatibility) (3G compatibility) (3G compatibility) Digital output buffer Digital input buffer Digital audio out Digital audio in 2.85V 2.
page 11/51 98 GND GND 99 GND GND 100 GND GND 101 GND GND 102 GND GND 103 GND GND 104 GND GND 105 GND GND 106 GND GND 107 GND GND 108 GND GND 109 GND GND 110 GND GND 111 GND GND 112 GND GND 113 GND GND 114 GND GND 115 GND GND 116 GND GND Note 1: VIO_SEL (Pad86) left unconnected.
page 12/51 3.2 SIM CARD 3.2.1 Internal SIM card NC HiAll module embeds an IC SIM Card as an optional hardware feature (MFF2 format according to ETSI standard). To get information about internal IC SIM Card option, please contact SAGEMCOM. 3.2.2 External SIM card connection NC HiAll module provides also external SIM interface.
page 13/51 protect SIM access of the 6 pin connector. This must be performed every time when the SIM card holder is accessed by the end user. If it is necessary to use long SIM bus lines of over 100mm, it is recommended to adopt serial resistors to avoid electrical overshoot on SIM bus signals. Use 56 Ω for the clock line and 10Ω for the reset and data lines. To use external SIM detection function, a GPIO pad must be connected to SIM holder.
page 14/51 3.3 AUDIOS NC The HiAll module provides both analogue and digital audio interfaces. 3.3.1 Analogue audio connection NC HiAll module features one input path and one output path for analogue audio. Both the input path and the output path are differential. The design examples in the following chapter will take into account the EMC, ESD protections, and reducing the possible TDMA noise in sensitive area by performing the given routing rules.
page 15/51 ESD protection 33pF Ferrite Bead NC HiAll + Ferrite Bead MIC 33pF ESD protection Figure 6: Filter and ESD protection of microphone 3.3.1.1.2 Notes for speaker As explained for the microphone, if the speaker is deported out of the board or is sensitive to ESD, use the schematic here to improve the audio.
page 16/51 Figure 8: Example of D class TPA2010D1 1Watt audio amplifier connections 3.3.1.2 Recommended characteristics for the microphone and speaker 3.3.1.2.1 Recommended characteristics for the microphone Item to be inspected Sensitivity Acceptance criterion - 40 dB SPL +/-3 dB (0 dB = 1 V/Pa @ 1kHz) Frequency response Limits (relatives values) Freq. (Hz) Lower limit 100 -1 200 -1 300 -1 1000 0 2000 -1 3000 -1.5 3400 -2 4000 -2 Upper limit 1 1 1 0 1 1.
page 17/51 Distortion 5% max at 1K Hz, nominal input power 3.3.1.3 DTMF OVER GSM network Former systems used to transmits data through DTMF modulation on RTC telephone lines. Audio DTMF tones are not guaranteed over GSM network This is due to the nature of the GSM Voice CODEC - it is specifically designed for the human voice and does not faithfully transmit DTMF.
page 18/51 Figure 9: PCM interface timing 3.4 POWER SUPPLY NC HiAll module can be supplied by a battery or by any DC/DC converter compliant with the input voltage range from 3.3V to 4.5V and 2A current capability. >VBAT traces are required to be as short and as wide as possible. VBAT ceramic decoupling capacitors of at least 100µF/10V are required to ensure good RF performance.
page 19/51 3.4.2 Ripples and drops Current burst at 1.8A 33dBm GSM TX Lev 5 Ripple VBAT drop 3.3V Min Figure 11: GSM/GPRS Burst Current rush and VBAT drops and ripples The minimum voltage during the drop of VBAT must be 3.3V at 33dBm for the full range of the required functioning temperature. To reach this aim, adapt the VBAT tracks width to minimize the loss: the shorter and thicker is the track; the lower is the serial impedance.
page 20/51 Figure 12: DC/DC power supply schematic example 3.4.3.2 Simple high current low dropout voltage regulator If the whole power consumption is not an issue, this example of a simple voltage regulator preceded by an AC/DC to 5V converter, can be used to power the module. The voltage output is given by: VOUT = 1.24V × [1 + (R1 / R2)] To have 3.7V out R1=100K & R2=49.9K) Figure 13: Example of power supply based on regulator MIC29302WU 3.4.3.
page 21/51 Figure 14: Example with Linear LT1913 3.4.4 Avoid side effects of a retro supply (current re-injection) NC Interactions or connections between HiAll module and the external systems can lead to retro power supply side effects, or current re-injection through pads while the module is not yet fully powered up (means VBAT lower than its minimum 3.3V).
o o page 22/51 Use external resistor divider to limit the ADC input voltage when measured a voltage higher than VANA. Do not connect the UART lines (TXD, RXD, RTS, CTS) to any other voltage. • To avoid any current re-injection on VGPIO (2.80V), o Do not connect a power supply to the VGPIO pad. This pad is an LDO output only. NC o The host must supply all the GPIOs connected to HiAll with correct voltage in compliance with the power domain, and must shut off the GPIOs when the module is off.
page 23/51 NC HiAll module has another reduced UART port. Its application is similar as the reduced case of main UART. Thus, this document describes only for main UART in the following chapter. 3.5.1 Complete V24 connection of HiAllNC to host NC HiAll provides a V24 interface with the following signals: UART1_RTS/ UART1_CTS, UART1_RXD/ UART1_TXD, UART1_DSR, UART1_DTR, UART1_DCD, UART1_RI. Use of this complete V24 connection is required whenever your application exchanges data.
page 24/51 NC Avoid supplying power to the main UART before the HiAll is ON, as this may result in power up sequence error. 3.5.2 Complete V24 interface with PC It supports speeds up to 1Mbps (115.2 Kbps with auto bauding). NC To use the V24 interface, some level shifter components are necessary, as HiAll signals need to be converted to +/- 5V signals compatible with a PC.
page 25/51 Figure 18: Example of a connection to a data cable with a MAX3238E 3.5.3 Partial V24 (RX-TX-RTS-CTS) connection of HiAllNC to host When using only UART1_RXD/ UART1_TXD/ UART1_RTS/ UART1_CTS instead of the complete V24 link, the following schematic could be used.
page 26/51 command after power up sequence or wake up from sleep mode. UART1_RI signal is a stand alone signal that can be used with any one of the following configuration. Consult the AT command specification for more information about this signal and its use. This configuration allows to use the flow control UART1_RTS & UART1_CTS to avoid any overflow error NC during the data transfer, UART1_CTS is moreover used to signal when the HiAll command after a power up sequence or a wake up from sleep mode.
page 27/51 3.6 SPI HiAllNC module manages a host SPI interface. This SPI interface is only dedicated for software traces. SAGEMCOM strongly recommends leaving this interface externally accessible for SW traces (e.g. access by test point pads) In case of needs SAGEMCOM may request to connect a dedicated trace cable to the customer’s electronic board. If tests points have been foreseen, simply solder 5 wires to a small HE10 male connector using the following schematic.
page 28/51 3.8 ADCS NC Two ADC input pads are available on HiAll module, which can be used to read the value of the voltage applied. Following characteristics must be met to allow proper performances: • The input signal voltage must be within 0V to 3V • The input impedance of the pad is 150KΩ • The input capacitance typically is 10pF. • 10 bits resolution • Maximum sampling frequency is 200KHz. 3.9 BACKUP BATTERY 3.9.
page 29/51 R VBACKUP HiAllNC VBACKUP Backup battery HiAllNC 10µF capacitor Figure 22: internal charging of backup battery or 10uF capacitor The value of resistor R depends on the charging current value of the backup battery manufacturer. 3.9.4 Capacitor backup battery technology SAGEMCOM strongly recommends using Supercap technology. These kinds of backup battery have not the drawbacks of the Lithium Ion rechargeable battery.
page 30/51 4. UNUSED PINS POLICY The table below defines the connection requirement of unused pins, as well as mandatory connections.
page 31/51 41 GPIO3 Left Open 42 TRST Left Open 43 VBAT_PA VBAT_PA 44 VBAT_PA VBAT_PA 45-56 57 GND 0V 58 VBAT UART1_DCD Left Open 59 UART1_RTS Loop to UART1_CTS 60 UART1_TX UART1_TX 61 UART1_RI Left Open 62 UART0_RX Left Open 63 UART0_CTS RESERVED (3G compatibility) PCM_OUT Loop to UART0_RTS Left Open 71 PCM_IN RESERVED (3G compatibility) RESERVED (3G compatibility) RESERVED (3G compatibility) RESERVED (3G compatibility) VGPIO 72 SPI_IN Left Open 73 SPI_OUT Left Open
page 32/51 NC 5. SCALABILITY WITH HILO -3GPS NC The table below defines the pin & supply voltage matching between HiAll Pad number 1-3 4 5-8 9 10 11 12 NC HiAll Pad name GND RF_GSM GND RESERVED (Not connected internally) GND RF_GPS GND Supply voltage domain Note 1 0V 0V NC Hilo -3GPS Pad name GND RF GND NC and HiLo -3GPS . Supply voltage domain 0V 0V AUX signal can be left connected NC to HiAll pad AUX 0V 0V GND GPS GND 0V 0V PPS signal can be left connected NC to Hilo -3GPS pad 13 PPS 2.
page 33/51 32 POK_IN 33 SIM_VCC 34 SIM_DATA 35 SIM_CLK 36 GPIO1 37 SPI_IRQ 38 RESERVED (Not connected internally) 39 GPS_EXT_LNA_EN 40 41 42 43 44 45-56 GPIO2 GPIO3 TRST VBAT_PA VBAT_PA GND 3V 1.8V/2.9 V 1.8V/2.9 V 1.8V/2.9 V 2.8V 2.8V 2.8V 2.8V 2.8V 2.8V 3.7V 3.7V 0V PWON 1.8V SIM_VCC 1.8V/2.9V SIM_DATA 1.8V/2.9V SIM_CLK 1.8V/2.
page 34/51 NC HiAll pad if tied to static signal internally) 71 72 73 74 75 76 77 78 VGPIO SPI_IN SPI_OUT SPI_SEL SPI_CLK TMS TDI TDO 79 SIM_RST 80 JTAG_TEST 82 83 84 85 RESERVED (Factory use, left open) TCK GPIO4 GPIO5 GPIO6 86 VIO_SEL 81 2.8V 2.8V 2.8V 2.8V 2.8V 2.8V 2.8V 2.8V 1.8V/2.9 V 2.8V 2.8V 2.8V 2.8V 2.8V 87 2G_RF_IND 2.85V 88 RTCK 2.8V 89-116 GND 0V Note 1: VIO_SEL (pad86) left unconnected. HiAllNC User Manual VGPIO SPI_IN SPI_OUT SPI_SEL SPI_CLK TMS TDI TDO 2.85V 1.8V 1.8V 1.
page 35/51 6. POWER MANAGEMENT VBAT Input voltage shall be in the range 3.3V to 4.5V. 6.1 POWER MODES NC Depending on the status of the HiAll , different power consumption modes can be identified. Communication mode (with or without GPS running) NC All systems on HiAll are active. In this mode, the module is registered to the network and a voice/data call is actively transmitting data.
page 36/51 Module is OFF Module is ON 2000ms POK_IN VGPIO Software Loading spike Module is ready to receive AT commands CTS Typ 5 seconds Max 7 seconds Figure 24: Power ON sequence 6.2.2 IO DC Presence before Power on When VBAT is available but the module has not yet powered up, the following I/O's raise their output. POK_IN raise to 3V VBACKUP raise to 3V HSET_N raise to 1.4V HSET_P raise to 1.4V 6.2.3 MODULE RESET To reset the module, a low level pulse must be sent on RESET pin during 10 ms.
page 37/51 The RESET signal will reset the registers of the CPU and reset the RAM memory as well. As RESET is referenced to VGPIO domain (internally to the module) it is impossible to make a reset before the module starts or try to use the RESET as a way to start the module. An other solution more costly would be to use MOS transistor to switch off the power supply and restart the power up procedure using the POK_IN input line 6.
page 38/51 DTE is in idle mode U.A.R.T. closed ? VBAT≥3.3 Volts min stable? POK_IN LOW for 2s AND Reset High? VGPIO rise to 2.
page 39/51 Module is ready to receive and send AT Sleep mode request Ksleep = 1 OR ( Ksleep = 0 AND DTR = High) Delay to enter the sleep mode VGPIO remains at 2.8V CTS is High DTE could also be in sleep mode The wakes up periods are set by the network DRX or the OS Module is in sleep m Wake up incoming event such as: • Network event. • Alarm interruption. • DTR interruption. • RTS interruption.
page 40/51 6.4 MODULE POWER OFF NC AT command “AT*PSCPOF” allows for correct power-off of the HiAll module. In case of necessary the module can be powered off by controlling the power supply. This can be used for NC example when the system freezes and no reset line is connected to the HiAll . In this case the only way to get the control back over the module is to switch off the power line.
page 41/51 6.5 MODULE SLEEP MODE The AT command “AT+KSLEEP” allows to configure the sleep mode. When AT+KSLEEP=1 is configured: • • NC The HiAll module decides by itself when it enters in sleep mode (no more task running). NC “0x00” character on serial link wakes up the HiAll module. When AT+KSLEEP=0 is configured: • • NC When UART1_DTR is deactivated (high electrical level), the HiAll module enters in sleep mode after a while.
page 42/51 7. ESD & EMC RECOMMENDATIONS 7.1 HiAll NC HiAll NC MODULE module alone can hold up to 2KV on each of the 116 pads including the RF pad. 7.2 Module handling NC HiAll modules are designed and packaged in tape-and-real for factories SMT process. NC HiAll modules contain electronic circuits sensitive to human hand's electrostatic electricity. Handling without ESD protection could result in permanent damages or even destruction of the module. 7.
page 43/51 8. RADIO INTEGRATION Radio engineering skills are mandatory to get accurate radio performance on customer’s product 8.1 GSM antenna connection RF lines shall match 50 ohms impedance In order to achieve optimum sensitivity and output power in radiated mode, it is strongly recommended to implement a matching circuit, as shown on schematic below Figure 28: GSM antenna connection schematic More information about GSM radio design can be found in [3]. 8.2 GNSS antenna connection 8.2.
page 44/51 Figure 29: GNSS active antenna connection schematic 8.2.2 Antenna detection For passive antenna, the command AT+KGNSSAD can be used to perform antenna detection. For active antenna, a GPIO can be used to detect the antenna power consumption. The customer needs to fit the current sense circuitry on its own board and match the detection level to the VGPIO level. 8.
page 45/51 9. AUDIO INTEGRATION FTA audio mandatory tests only deal with handset mode so a particular care must be brought to the design of audio (mechanical integration, gasket, electronic) in this mode. The audio related standard are 3GPP TS 26.131 & 3GPP TS 26.132. Note that acoustic competences are mandatory to get accurate audio performance on customer’s product. 9.
page 46/51 Separate the PCBs for the microphone and the speaker if possible. Reduce the number of electronic components as much as possible (to avoid loss of quality and greater dispersion). Audio tracks must be larger than 0.5 mm.
page 47/51 10. LAYOUT RECOMMENDATIONS ON CUSTOMER BOARD 10.1 GENERAL RECOMMENDATIONS ON LAYOUT There are many different types of signals in the module which may be interfered each other. Particularly, Audio signals are very sensitive to external signals such as VBAT... Therefore it is very important to follow some rules to avoid signal disruption or abnormal behaviour. Magnetic fields generated by VBAT tracks may cause speaker interference and burst noise.
page 48/51 10.1.3 Clocks Clock signals must be shielded between two grounds layer and bordered with ground vias. 10.1.4 Data bus and other signals Data bus must be routed on the same layer with equivalent track length and avoiding long parallel routing. Lines crossings shall be perpendicular Suitable signals track width, thickness for other signals. Data bus must be protected by upper and lower ground plans 10.1.
page 49/51 10.2 EXAMPLE OF LAYOUT FOR CUSTOMER’S BOARD The following figure is an example of layer allocation for a 6 layers circuit (for reference purpose only): Depending on the customer’s design, the layout could also be 4 layers. Figure 32: 6 layers PCB stack-up 11. LABEL NC The HiAll module is labelled with its own FCC ID (VW3HIALLNC) on the shield side. When the module is installed in customer’s product, the FCC ID label on the module will not be visible.
page 50/51 This device has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
page 51/51 interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p) is not more than necessary for successful communication. Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les.
