RX23W Group Table 33.15 33. Serial Communications Interface (SCIg, SCIh) Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) SEMR Settings SEMR Settings PCLK (MHz) BGDM Bit ABCS Bit n N Maximum Bit Rate (bps) PCLK (MHz) BGDM Bit ABCS Bit n N Maximum Bit Rate (bps) 8 0 0 0 0 250000 17.
RX23W Group Table 33.16 33. Serial Communications Interface (SCIg, SCIh) Maximum Bit Rate with External Clock Input (Asynchronous Mode) Maximum Bit Rate (bps) PCLK (MHz) External Input Clock (MHz) SEMR.ABCS Bit = 0 SEMR.ABCS Bit = 1 8 2.0000 125000 250000 9.8304 2.4576 153600 307200 10 2.5000 156250 312500 12 3.0000 187500 375000 12.288 3.0720 192000 384000 14 3.5000 218750 437500 16 4.0000 250000 500000 17.2032 4.3008 268800 537600 18 4.5000 281250 562500 19.
RX23W Group Table 33.18 33. Serial Communications Interface (SCIg, SCIh) BRR Settings for Various Bit Rates (Clock Synchronous Mode, Simple SPI Mode) Operating Frequency PCLK (MHz) 8 Bit Rate (bps) 10 16 20 n N n N n N 250 3 124 3 155 3 249 500 2 249 3 77 3 1k 2 124 2 155 2 2.
RX23W Group Table 33.20 33. Serial Communications Interface (SCIg, SCIh) BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Bit Rate (bps) PCLK (MHz) n N 9600 7.1424 0 0 0.00 10.00 0 1 –30.00 10.7136 0 1 –25.00 13.00 0 1 –8.99 14.2848 0 1 0.00 16.00 0 1 12.01 18.00 0 2 –15.99 20.00 0 2 –6.66 25.00 0 3 –12.49 30.00 0 3 5.01 Table 33.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) BRR Settings for Various Bit Rates (Simple I2C Mode) Table 33.22 Operating Frequency PCLK (MHz) 8 10 16 20 25 Bit Rate (bps) n N Error (%) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 10 k 0 24 0.0 0 31 –2.3 1 12 –3.8 1 15 –2.3 1 19 –2.3 25 k 0 9 0.0 0 12 –3.8 1 4 0.0 1 6 –10.7 1 7 –2.3 50 k 0 4 0.0 0 6 –10.7 1 2 –16.7 1 3 –21.9 1 3 –2.3 100 k 0 2 –16.
RX23W Group 33.2.12 33. Serial Communications Interface (SCIg, SCIh) Modulation Duty Register (MDDR) Address(es): SCI1.MDDR 0008 A032h, SCI5.MDDR 0008 A0B2h, SCI8.MDDR 0008 A112h, SCI12.MDDR 0008 B312h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 1 1 The MDDR register corrects the bit rate adjusted by the BRR register. When the SEMR.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Smaller settings of the SMR.CKS[1:0] bits and larger settings of the BRR register reduce difference in the length of the 1-bit period. 33.2.13 Serial Extended Mode Register (SEMR) Address(es): SCI1.SEMR 0008 A027h, SCI5.SEMR 0008 A0A7h, SCI8.SEMR 0008 A107h, SCI12.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) ACS0 Bit (Asynchronous Mode Clock Source Select) Selects the clock source in the asynchronous mode. The ACS0 bit is valid in asynchronous mode (SMR.CM bit = 0) and when an external clock input is selected (SCR.CKE[1:0] bits = 10b or 11b). This bit is used to select an external clock input or the logical AND of compare matches output from the internal TMR. Set the ACS0 bit to 0 in other than asynchronous mode.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) BRME Bit (Bit Rate Modulation Enable) This bit enables and disables the bit rate modulation function. The bit rate generated by on-chip baud rate generator is evenly corrected when this function is enabled. NFEN Bit (Digital Noise Filter Function Enable) This bit enables or disables the digital noise filter function.
RX23W Group 33.2.14 33. Serial Communications Interface (SCIg, SCIh) Noise Filter Setting Register (SNFR) Address(es): SCI1.SNFR 0008 A028h, SCI5.SNFR 0008 A0A8h, SCI8.SNFR 0008 A108h, SCI12.SNFR 0008 B308h Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 NFCS[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 NFCS[2:0] Noise Filter Clock Select In asynchronous mode, the standard setting for the base clock is as follows.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) I2C Mode Register 1 (SIMR1) 33.2.15 Address(es): SCI1.SIMR1 0008 A029h, SCI5.SIMR1 0008 A0A9h, SCI8.SIMR1 0008 A109h, SCI12.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) I2C Mode Register 2 (SIMR2) 33.2.16 Address(es): SCI1.SIMR2 0008 A02Ah, SCI5.SIMR2 0008 A0AAh, SCI8.SIMR2 0008 A10Ah, SCI12.SIMR2 0008 B30Ah Value after reset: b7 b6 b5 b4 b3 b2 — — IICACK T — — — 0 0 0 0 0 0 b1 b0 IICCSC IICINT M 0 0 Bit Symbol Bit Name Description R/W b0 IICINTM I2C Interrupt Mode Select 0: Use ACK/NACK interrupts. 1: Use reception and transmission interrupts.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) I2C Mode Register 3 (SIMR3) 33.2.17 Address(es): SCI1.SIMR3 0008 A02Bh, SCI5.SIMR3 0008 A0ABh, SCI8.SIMR3 0008 A10Bh, SCI12.SIMR3 0008 B30Bh b7 b6 IICSCLS[1:0] Value after reset: 0 0 b5 b4 IICSDAS[1:0] 0 0 b3 b2 b1 b0 IICSTIF IICSTP IICRST IICSTA REQ AREQ REQ 0 0 0 0 Bit Symbol Bit Name Description R/W b0 IICSTAREQ Start Condition Generation 0: A start condition is not generated. 1: A start condition is generated.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) IICRSTAREQ Bit (Restart Condition Generation) When a restart condition is to be generated, set both the IICSDAS[1:0] and IICSCLS[1:0] bits to 01b as well as setting the IICRSTAREQ bit to 1.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) I2C Status Register (SISR) 33.2.18 Address(es): SCI1.SISR 0008 A02Ch, SCI5.SISR 0008 A0ACh, SCI8.SISR 0008 A10Ch, SCI12.SISR 0008 B30Ch Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — IICACK R 0 0 x x 0 x 0 0 x: Undefined Bit Symbol Bit Name Description R/W b0 IICACKR ACK Reception Data Flag 0: ACK received 1: NACK received R/W*1 b1 — Reserved This bit is read as 0. The write value should be 0.
RX23W Group 33.2.19 33. Serial Communications Interface (SCIg, SCIh) SPI Mode Register (SPMR) Address(es): SCI1.SPMR 0008 A02Dh, SCI5.SPMR 0008 A0ADh, SCI8.SPMR 0008 A10Dh, SCI12.SPMR 0008 B30Dh b7 b6 CKPH CKPOL Value after reset: 0 0 b5 b4 b3 b2 b1 b0 — MFF — MSS CTSE SSE 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 SSE SSn# Pin Function Enable 0: SSn# pin function is disabled. 1: SSn# pin function is enabled.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) MFF Flag (Mode Fault Flag) This bit indicates mode fault errors. In a multi-master configuration, determine the mode fault error occurrence by reading the MFF flag.
RX23W Group 33.2.21 33. Serial Communications Interface (SCIg, SCIh) Control Register 0 (CR0) Address(es): SCI12.CR0 0008 B321h Value after reset: b7 b6 b5 b4 — — — — 0 0 0 0 b3 b2 b1 b0 BRME RXDSF SFSF 0 0 — 0 0 Bit Symbol Bit Name Description R/W b0 — Reserved This bit is read as 0. The write value should be 0. R/W b1 SFSF Start Frame Status Flag 0: Start Frame detection function is disabled. 1: Start Frame detection function is enabled.
RX23W Group 33.2.23 33. Serial Communications Interface (SCIg, SCIh) Control Register 2 (CR2) Address(es): SCI12.CR2 0008 B323h b7 Value after reset: b6 b4 b3 RTS[1:0] BCCS[1:0] — 0 0 0 0 b5 0 b2 b1 b0 DFCS[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 DFCS[2:0] RXDX12 Signal Digital Filter Clock Select b2 R/W b3 — Reserved This bit is read as 0. The write value should be 0. R/W b5, b4 BCCS[1:0] Bus Collision Detection Clock Select • When SEMR.
RX23W Group 33.2.24 33. Serial Communications Interface (SCIg, SCIh) Control Register 3 (CR3) Address(es): SCI12.CR3 0008 B324h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — SDST 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 SDST Start Frame Detection Start 0: Detection of Start Frame is not performed. 1: Detection of Start Frame is performed. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 33.2.26 33. Serial Communications Interface (SCIg, SCIh) Interrupt Control Register (ICR) Address(es): SCI12.ICR 0008 B326h Value after reset: b7 b6 — — 0 0 b5 b4 b3 b2 b1 b0 AEDIE BCDIE PIBDIE CF1MI CF0MI BFDIE E E 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 BFDIE Break Field Low Width Detected Interrupt Enable 0: Interrupts on detection of the low width for a Break Field are disabled.
RX23W Group 33.2.27 33. Serial Communications Interface (SCIg, SCIh) Status Register (STR) Address(es): SCI12.
RX23W Group 33.2.28 33. Serial Communications Interface (SCIg, SCIh) Status Clear Register (STCR) Address(es): SCI12.STCR 0008 B328h Value after reset: b7 b6 — — 0 0 b5 b4 b3 b2 b1 b0 AEDCL BCDCL PIBDC CF1MC CF0MC BFDCL L L L 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 BFDCL BFDF Clear Setting this bit to 1 clears the STR.BFDF flag. This bit is read as 0. R/W b1 CF0MCL CF0MF Clear Setting this bit to 1 clears the STR.CF0MF flag. This bit is read as 0.
RX23W Group 33.2.30 33. Serial Communications Interface (SCIg, SCIh) Control Field 0 Compare Enable Register (CF0CR) Address(es): SCI12.CF0CR 0008 B32Ah b7 b6 b5 b4 b3 b2 b1 b0 CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE CF0CE 7 6 5 4 3 2 1 0 Value after reset: 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 CF0CE0 Control Field 0 Bit 0 Compare Enable 0: Comparison with bit 0 of Control Field 0 is disabled. 1: Comparison with bit 0 of Control Field 0 is enabled.
RX23W Group 33.2.33 33. Serial Communications Interface (SCIg, SCIh) Secondary Control Field 1 Data Register (SCF1DR) Address(es): SCI12.SCF1DR 0008 B32Dh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 PCF1DR is an 8-bit readable and writable register that holds the 8-bit secondary value for comparison with Control Field 1. 33.2.34 Control Field 1 Compare Enable Register (CF1CR) Address(es): SCI12.
RX23W Group 33.2.36 33. Serial Communications Interface (SCIg, SCIh) Timer Control Register (TCR) Address(es): SCI12.TCR 0008 B330h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — TCST 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 TCST Timer Count Start 0: Stops the timer counting 1: Starts the timer counting R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W 33.2.37 Timer Mode Register (TMR) Address(es): SCI12.
RX23W Group 33.2.38 33. Serial Communications Interface (SCIg, SCIh) Timer Prescaler Register (TPRE) Address(es): SCI12.TPRE 0008 B332h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 1 1 TPRE consists of an 8-bit reload register, a read buffer, and a counter, each of which has FFh as its initial value. The counter counts down in synchronization with the counter clock selected by the TMR.TCSS[2:0] bits, and is reloaded with the value in the reload register when it underflows.
RX23W Group 33.3 33. Serial Communications Interface (SCIg, SCIh) Operation in Asynchronous Mode Figure 33.5 shows the general format for asynchronous serial communications. One frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the communications line is usually held in the mark state (high level). The SCI monitors the communications line.
RX23W Group Table 33.27 33.
RX23W Group 33.3.2 33. Serial Communications Interface (SCIg, SCIh) Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times*1 the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
RX23W Group 33.3.3 33. Serial Communications Interface (SCIg, SCIh) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be selected as the SCI’s transfer clock, according to the setting of the SMR.CM bit and the SCR.CKE[1:0] bits. When an external clock is input to the SCKn pin, the clock frequency should be 16 times the bit rate (when SEMR.ABCS bit = 0) and 8 times the bit rate (when SEMR.ABCS bit = 1).
RX23W Group 33.3.5 33. Serial Communications Interface (SCIg, SCIh) CTS and RTS Functions The CTS function is the use of input on the CTSn# pin in transmission control. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled, placing the low level on the CTSn# pin causes transmission to start. Applying the high level to the CTS# pin while transmission is in progress does not affect transmission of the current frame, which continues.
RX23W Group 33.3.6 33. Serial Communications Interface (SCIg, SCIh) SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue through the procedure for SCI given in Figure 33.8. Whenever the operating mode or transfer format is changed, the SCR register must be initialized before the change is made.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Figure 33.9 shows an example of data transmission when the SCI is set to asynchronous mode according to the flow described in Figure 33.8 after a reset. When the pin function is set to the TXD pin, it is still high-impedance because the SCR.TE bit is 0. When the transmit data is written after setting the TE bit to 1, a data transmission starts.
RX23W Group 33.3.7 33. Serial Communications Interface (SCIg, SCIh) Serial Data Transmission (Asynchronous Mode) Figure 33.10 to Figure 33.12 show an example of the operation for serial transmission in asynchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI transfers data from the TDR register*1 to the TSR register when data is written to the TDR register*1 in the TXI interrupt handling routine.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Data Start bit 0 D0 D1 SCR.TE bit Parity bit Stop bit D7 0/1 1 0 D0 D7 0/1 D1 1 0 1 frame TXI interrupt flag (IRn in ICU*1) SSR.TEND flag TXI interrupt request generated Data written to TDR in TXI interrupt handling routine TXI interrupt request generated Data written to TDR in TXI interrupt handling routine Data written to TDR in TXI interrupt handling routine Note 1.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Data Start bit Parity bit 0 D0 D1 Stop bit D7 0/1 1 0 D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1 Idle state (mark state) SCR.TE bit 1 (TIE = 1) TXI interrupt flag (IRn in ICU*1) (TIE = 0) SSR.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) [1] Initialization [1] SCI initialization: Set data transmission. After the SCR.TE bit is set to 1, high is output for a frame, and transmission is enabled. [2] Transmit data write to the TDR register by a TXI interrupt request: When transmit data is transferred from the TDR register to the TSR register, a transmit data empty interrupt (TXI) request is generated.
RX23W Group 33.3.8 33. Serial Communications Interface (SCIg, SCIh) Serial Data Reception (Asynchronous Mode) Figure 33.14 and Figure 33.15 show an example of the operation for serial data reception in asynchronous mode. In serial data reception, the SCI operates as described below. 1. When the value of the SCR.RE bit becomes 1, the output signal on the RTSn# pin goes to the low level. 2.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Data Start bit 0 D0 Parity Stop bit bit D7 0/1 Data Start bit 1 0 D0 Parity Stop bit bit D7 0/1 0 Start bit Idle state (mark state) 0 Data D0 RXI interrupt flag (IRn in ICU*1) SSR.FER flag RXI interrupt request generated RDR data read in RXI interrupt handling routine ERI interrupt request generated by framing error Error flag is cleared RTSn# pin 1 frame Note 1.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) [1] Initialization [1] Start data reception Read the SSR.ORER, PER, and FER flags [2] Yes SSR.ORER flag = 1, SSR.PER flag = 1, or SSR.FER flag = 1 [3] No Error processing SCI initialization: Set data reception. [ 2 ] [ 3 ] Receive error processing and break detection: If a receive error occurs, an ERI interrupt is generated. An error is identified by reading the ORER, PER, and FER flags in the SSR register.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) [3] Error processing No SSR.ORER flag = 1 Yes Overrun error processing [6] [ 6 ] Processing in response to an overrun error: Read the RDR register. In combination with step [ 7 ], this will make correct reception of the next frame possible. No SSR.FER flag = 1 Yes Yes Break? No Framing error processing Set the SCR.RE bit to 0 No SSR.PER flag = 1 Yes Parity error processing Set the SSR.
RX23W Group 33.4 33. Serial Communications Interface (SCIg, SCIh) Multi-Processor Communications Function Using the multi-processor communication functions enables to transmit and receive data by sharing a communication line between multiple processors by using asynchronous serial communication in which the multi-processor bit is added. In multi-processor communication, a unique ID code is allocated to each receiving station.
RX23W Group 33.4.1 33. Serial Communications Interface (SCIg, SCIh) Multi-Processor Serial Data Transmission Figure 33.19 is a sample flowchart of multi-processor data transmission. In the ID transmission cycle, the ID should be transmitted with the SSR.MPBT bit set to 1. In the data transmission cycle, the data should be transmitted with the MPBT bit set to 0. The other operations are the same as the operations in asynchronous mode. Initialization [1] [1] SCI initialization: Set data transmission.
RX23W Group 33.4.2 33. Serial Communications Interface (SCIg, SCIh) Multi-Processor Serial Data Reception Figure 33.21 and Figure 33.22 are sample flowcharts of multi-processor data reception. When the SCR.MPIE bit is set to 1, reading the communication data is skipped until reception of the communication data in which the multi-processor bit is set to 1.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Initialization [1] [ 1 ] SCI initialization: Set data reception. Start data reception [ 2 ] ID reception cycle: Set the SCR.MPIE bit to 1 and wait for ID reception. Set SCR.MPIE bit to 1 [2] [ 3 ] SCI status confirmation and reception and comparison of ID: Read data in the RDR register at the first RXI No RXI interrupt? interrupt, and compare it with the ID of the receiving station itself.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) [5] Error processing No SSR.ORER flag = 1 Yes Overrun error processing [6] [ 6 ] Processing in response to an overrun error: Read the RDR register. In combination with step [ 7 ], this will make correct reception of the next frame possible. No SSR.FER flag = 1 Yes Yes Break? No Framing error processing Set the SSR.ORER, PER, and FER flags to 0. [7] [ 7 ] Clearing the error flag: Write 0 to the error flag. Read the SSR.
RX23W Group 33.5 33. Serial Communications Interface (SCIg, SCIh) Operation in Clock Synchronous Mode Figure 33.23 shows the data format for clock synchronous serial data communications. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In clock synchronous mode, no parity bit can be added. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next.
RX23W Group 33.5.2 33. Serial Communications Interface (SCIg, SCIh) CTS and RTS Functions In the CTS function, CTSn# pin input is used to control reception/transmission start when the clock source is the internal clock. Setting the SPMR.CTSE bit to 1 enables the CTS function. When the CTS function is enabled, placing the low level on the CTSn# pin causes reception/transmission to start.
RX23W Group 33.5.3 33. Serial Communications Interface (SCIg, SCIh) SCI Initialization (Clock Synchronous Mode) Before transmitting and receiving data, start by writing the initial value 00h to the SCR register and then continue through the procedure for SCI given in Figure 33.24. Whenever the operating mode or transfer format is changed, the SCR register must be initialized before the change is made. Note that setting the SCR.
RX23W Group 33.5.4 33. Serial Communications Interface (SCIg, SCIh) Serial Data Transmission (Clock Synchronous Mode) Figure 33.25, Figure 33.26, and Figure 33.27 show an example of the operation for serial transmission in clock synchronous mode. In serial data transmission, the SCI operates as described below. 1. The SCI transfers data from the TDR register to the TSR register when data is written to the TDR register in the TXI interrupt handling routine.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Synchronization clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Bit 0 SCR.TE bit TXI interrupt flag (IRn in ICU*1) SSR.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Synchronization clock Bit 0 Serial data Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7 (TIE = 1) TXI interrupt flag (IRn in ICU*1) (TIE = 0) SSR.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) [1] Initialization Start transmission No [1] SCI initialization: Set data transmission. [2] Writing transmit data write to the TDR register by a TXI interrupt request: When transmit data is transferred from the TDR register to the TSR register, a transmit data empty interrupt (TXI) request is generated. Transmit data is written to the TDR register once from the handling routine for TXI requests.
RX23W Group 33.5.5 33. Serial Communications Interface (SCIg, SCIh) Serial Data Reception (Clock Synchronous Mode) Figure 33.29 and Figure 33.30 show an example of SCI operation for serial reception in clock synchronous mode. In serial data reception, the SCI operates as described below. 1. The value of the SCR.RE bit becoming 1 places the signal output on the RTSn# pin at the low level (when the RTS function is in use). 2.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Synchronization clock Serial data Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 RXI interrupt flag (IRn in ICU*1) SSR.ORER flag RXI interrupt request generated RXI interrupt request generated RDR data read in RXI interrupt handling routine RDR data read in RXI interrupt handling routine RTSn# pin 1 frame Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number. Figure 33.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Figure 33.31 shows a sample flowchart for serial data reception. Initialization Start data reception SCI initialization: Make input port-pin settings for pins to be used as RXDn pins. [2] [ 3 ] Receive error processing: If a receive error occurs, read the SSR.ORER flag, perform the relevant error processing, and then set the ORER flag to 0. Data reception cannot be resumed while the ORER flag is 1.
RX23W Group 33.5.6 33. Serial Communications Interface (SCIg, SCIh) Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode) Figure 33.32 shows a sample flowchart for simultaneous serial transmit and receive operations in clock synchronous mode. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
RX23W Group 33.6 33. Serial Communications Interface (SCIg, SCIh) Operation in Smart Card Interface Mode The SCI supports smart card (IC card) interfaces conforming to ISO/IEC 7816-3 (standard for Identification Cards), as an extended function of the SCI. Smart card interface mode can be selected using the appropriate register. 33.6.1 Sample Connection Figure 33.33 shows a sample connection between a smart card (IC card) and this MCU.
RX23W Group 33.6.2 33. Serial Communications Interface (SCIg, SCIh) Data Format (Except in Block Transfer Mode) Figure 33.34 shows the data transfer formats in smart card interface mode. • One frame consists of 8-bit data and a parity bit in asynchronous mode. • During transmission, at least 2 etu (elementary time unit: time required for transferring 1 bit) is secured as a guard time from the end of the parity bit until the start of the next frame.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) For communications with IC cards of the direct convention type and inverse convention type, follow the procedure below. (1) Direct Convention Type For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB first as the start character, as shown in Figure 33.35. Therefore, data in the start character in the figure is 3Bh.
RX23W Group 33.6.4 33. Serial Communications Interface (SCIg, SCIh) Receive Data Sampling Timing and Reception Margin Only the base clock generated by the on-chip baud rate generator can be used as a transmit/receive clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate according to the settings of the SCMR.BCP2 bit and the SMR.BCP[1:0] bits.
RX23W Group 33.6.5 33. Serial Communications Interface (SCIg, SCIh) SCI Initialization (Smart Card Interface Mode) Initialize the SCI following the example of flowchart shown in Figure 33.38. Initialize the SCR and SSR registers before switching from transmit mode to receive mode and vice versa. When not changing the bit rate, it is not necessary to set the CKE[1:0] bits to 00b. Even if the RE bit is set to 0, the RDR register is not initialized.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Figure 33.39 shows an example of data transmission when the SCI is set to smart card interface mode according to the flow described in Figure 33.38 after a reset. When the pin functions are set to the SCK and TXD pins, they are still high-impedance because the SCR.CKE[0] and SCR.TE bits are 0. When the CKE[0] bit is set to 1, clock is output from the SCK pin.
RX23W Group 33.6.6 33. Serial Communications Interface (SCIg, SCIh) Serial Data Transmission (Except in Block Transfer Mode) Serial data transmission in smart card interface mode (except in block transfer mode), in that an error signal is sampled and data can be retransmitted, is different from that in non-smart card interface mode. Figure 33.40 shows the data retransmit operation during transmission.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Figure 33.41 shows a sample flowchart of serial transmission. Start Initialization Start data transmission No SSR.ERS flag = 0? Yes Error processing No TXI interrupt Yes Write transmit data to the TDR register No All transmit data written? Yes No SSR.ERS flag = 0? Yes Error processing No TXI interrupt Yes Set the SCR.TIE, RIE, and TE bits to 0 End Figure 33.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) When transmitting/receiving data using the DTC or DMAC, be sure to make settings to enable the DTC or DMAC before making SCI settings. For DTC or DMAC settings, refer to section 19, Data Transfer Controller (DTCa), section 18, DMA Controller (DMACA). Note that the SSR.TEND flag is set in different timings depending on the SMR.GM bit setting. Figure 33.42 shows the TEND flag generation timing. I/O data Ds D0 D1 D2 D3 D4 D5 D6 D7 SSR.
RX23W Group 33.6.7 33. Serial Communications Interface (SCIg, SCIh) Serial Data Reception (Except in Block Transfer Mode) Serial data reception in smart card interface mode is similar to that in non-smart card interface mode. Figure 33.43 shows the data retransmit operation in receive mode. nth transmitted frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (n + 1)-th transmitted frame Retransmitted frame DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 RXI interrupt signal (2) (4) (1) (3) SSR.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Figure 33.44 shows a sample flowchart for serial data reception. Start Initialization Start data reception SSR.ORER = 0 and SSR.PER = 0? No Yes Error processing No RXI interrupt Yes Read data from the RDR register No All data received? Yes Set the SCR.RIE and RE bits to 0 Figure 33.
RX23W Group 33.6.8 33. Serial Communications Interface (SCIg, SCIh) Clock Output Control Clock output can be fixed to high or low using the SCR.CKE[1:0] bits when the SMR.GM bit is 1. When the CKE[1:0] bits are set to 01b (clock output), the base clock is output from the SCK pin. For the settings of the base clock frequency (bit rate), refer to section 33.2.11, Bit Rate Register (BRR).
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Operation in Simple I2C Mode 33.7 Simple I2C-bus format is composed of 8 data bits and an acknowledge bit. By continuing into a slave-address frame after a start condition or restart condition, a master device is able to specify a slave device as the partner for communications. The currently specified slave device remains valid until a new slave device is specified or a stop condition is satisfied.
RX23W Group 33.7.1 33. Serial Communications Interface (SCIg, SCIh) Generation of Start, Restart, and Stop Conditions Writing 1 to the SIMR3.IICSTAREQ bit causes the generation of a start condition. The generation of a start condition proceeds through the following operations. • The level on the SSDAn line falls (from the high level to the low level) and the SSCLn line is kept in the released state.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Figure 33.48 shows the timing of operations in the generation of start, restart, and stop conditions. SSCLn SSDAn SIMR3.IICSTAREQ SIMR3.IICRSTAREQ SIMR3.IICSTPREQ SIMR3.IICSDAS[1:0] 11b 01b SIMR3.IICSCLS[1:0] Start-condition generated interrupt request Figure 33.
RX23W Group 33.7.2 33. Serial Communications Interface (SCIg, SCIh) Clock Synchronization The SSCLn line may be placed at the low level in the case of a wait inserted by a slave device as the other side of transfer. Setting the SIMR2.IICCSC bit to 1 applies control to obtain synchronization when the levels of the internal SSCLn clock signal and the level being input on the SSCLn pin differ. When the SIMR2.
RX23W Group 33.7.3 33. Serial Communications Interface (SCIg, SCIh) SSDA Output Delay The SIMR1.IICDL[4:0] bits can be used to set a delay for output on the SSDAn pin relative to falling edges of output on the SSCLn pin. Delay-time settings from 0 to 31 are selectable, representing periods of the corresponding numbers of cycles of the clock signal from the on-chip baud rate generator (derived by frequency-dividing the base clock, PCLK, by the divisor selected by the SMR.CKS[1:0] bits).
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) SCI Initialization (Simple I2C Mode) 33.7.4 Before transferring data, write the initial value (00h) to the SCR register and initialize the interface following the example shown in Figure 33.51. When changing the operating mode, transfer format, and so on, be sure to set the SCR register to its initial value before proceeding with the changes.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Operation in Master Transmission (Simple I2C Mode) 33.7.5 Figure 33.52 and Figure 33.53 show examples of operations in master transmission and Figure 33.54 is a flowchart showing the procedure for data transmission. Refer to Table 33.33 for more information on the STI interrupt. When 10-bit slave addresses are in use, steps [3] and [4] in Figure 33.54 are repeated twice.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) [1] Initialization [1] Initialization for simple I2C mode For transmission, set the SCR.RIE bit to 0 (RXI and ERI interrupts requests are disabled) [2] Generate a start condition. [3] Writing to the TDR register: Writing the slave address and value for the R/W bit to the TDR register. [4] Confirming ACK response from the slave address: Check the SISR.IICACKR bit.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Master Reception (Simple I2C Mode) 33.7.6 Figure 33.55 shows an example of operations in simple I2C mode master reception and Figure 33.56 is a flowchart showing the procedure for master reception. The value of the SIMR2.IICINTM bit is assumed to be 1 (use reception and transmission interrupts).
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) [1] Initialization Start of reception Simultaneously set the SIMR3.IICSTAREQ bit to 1 and the SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to 01b STI interrupt? [2] Generate a start condition. [3] Writing to the TDR register: Writing the slave address and value for the R/W bit to the TDR register. [4] Confirming ACK response from the slave address: Check the SISR.IICACKR bit.
RX23W Group 33.7.7 33. Serial Communications Interface (SCIg, SCIh) Recovery from Bus Hang-up If the bus is stuck by an abnormal state in SCI because of the communication error, reset the SCI according to the following steps and release the bus. (1) Set the SCR.TE and RE bit to 0 at the same time to reset SCI. (2) Set the SIMR3 register to F0h to release the bus. (3) If the SSR.RDRF flag is 1, dummy-read the RDR register to clear the flag. (4) Set the SCR.TE and RE bit to 1 at the same time.
RX23W Group 33.8 33. Serial Communications Interface (SCIg, SCIh) Operation in Simple SPI Mode As an extended function, the SCI supports a simple SPI mode that handles transfer among one or multiple master devices and multiple slave devices. Making the settings for clock synchronous mode (SCMR.SMIF = 0, SIMR1.IICM = 0, SMR.CM = 1) plus setting the SPMR.SSE bit to 1 places the SCI in simple SPI mode.
RX23W Group 33.8.1 33. Serial Communications Interface (SCIg, SCIh) States of Pins in Master and Slave Modes The direction (input or output) of pins for the simple SPI mode interface differs according to whether the device is a master (SCR.CKE[1:0] = 00b or 01b and SPMR.MSS = 0) or slave (SCR.CKE[1:0] = 10b or 11b and SPMR.MSS = 1). Table 33.29 lists the states of pins according to the mode and the level on the SSn# pin. Table 33.
RX23W Group 33.8.4 33. Serial Communications Interface (SCIg, SCIh) Relationship between Clock and Transmit/Receive Data The CKPOL and CKPH bits in the SPMR register can be used to set up the clock for use in transmission and reception in four different ways. The relation between the clock signal and the transmission and reception of data is shown in Figure 33.58. The relation is the same for both master and slave operation.
RX23W Group 33.8.5 33. Serial Communications Interface (SCIg, SCIh) SCI Initialization (Simple SPI Mode) The procedure is the same as for initialization in clock synchronous mode Figure 33.24, Sample SCI Initialization Flowchart. The CKPOL and CKPH bits in the SPMR register must be set to ensure that the kind of clock signal they select is suitable for both master and slave devices.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.10 Extended Serial Mode Control Section: Description of Operation 33.10.1 Serial Transfer Protocol The extended serial mode control section of the SCI12 can realize the serial transfer protocol composed of Start Frames and Information Frames that is shown in Figure 33.60. A Start Frame is composed of a Break Field, Control Field 0, and Control Field 1.
RX23W Group 33.10.2 33. Serial Communications Interface (SCIg, SCIh) Transmitting a Start Frame Figure 33.61 shows an example of operations to transmit a Start Frame, which is composed of the Break Field low width, Control Field 0, and Control Field 1. Figure 33.62 and Figure 33.63 are flowcharts for the transmission of a Start Frame. Operations when the extended serial mode control section is to be used to transmit a Start Frame are as listed below. Be sure to use the SCI12 in asynchronous mode.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Start Set 1 to ESMER.ESME Enable the extended serial mode control section. Set CR2.RTS[1:0], BCCS[1:0], and DFCS[2:0] Set the timing of sampling for RXDX12 reception, clock for bus collision detection, and sampling clock for the RXDX12 signal’s digital filter. Set PCR.SHARPS, RXDXPS, and TXDXPS Set the RXDX12 and TXDX12 pins. Set 10b to TMR.TOMS[1:0] Set Break Field low width output mode as the operating mode of the timer. Set TMR.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) A Set 1 to TCR.TCST STR.BFDF = 1? Start the timer counter and output of the Break Field low width. No The STR.BFDF flag is set to 1 on output of the Break Field low width. At this time, if the ICR.BFDIE bit is 1, an SCIX0 interrupt is generated. Yes Set 1 to STCR.BFDCL Clear the BFDF flag. After output of the Break Field low width is completed, stop the timer counting before the next underflow of the timer occurs. Set TCR.
RX23W Group 33.10.3 33. Serial Communications Interface (SCIg, SCIh) Receiving a Start Frame The extended serial mode control section is capable of receiving Start Frames with the structures listed in Table 33.30. Table 33.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Start Frame Break Field low width RXDX12 pin Write 1 to CR3.SDST Information Frame Control Field 0 Control Field 1 8 bits 8 bits Data Field Set to 0 after Break Field low width detection CR0.RXDSF Specified period for TCNT and TPRE Write 1 to STCR.BFDCL STR.BFDF Write 1 to STCR.CF0MCL STR.CF0MF Write 1 to STCR.CF1MCL STR.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Start Set 1 to ESMER.ESME Enable the extended serial mode control section. Set CR1.BFE and CF0RE Set whether to include the Break Field and Control Field 0 in the Start Frame. Set CR1.CF1DS[1:0] and PIBE Select the data for comparison with Control Field 1 and the presence or absence of a priority interrupt bit. Set CR1.PIBS[2:0] Select the bit of Control Field 1 that will be the priority interrupt bit.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) B Set 1 to TCR.TCST Start the timer counter so that determining the Break Field is possible. Set 1 to CR3.SDST Begin detection of the Start Frame. STR.BFDF = 1? No The STR.BFDF flag is set to 1 on detection of the Break Field low width. At this time, if the ICR.BFDIE bit is 1, an SCIX0 interrupt is generated. Yes Set 1 to STCR.BFDCL STR.CF0MF = 1? Clear the STR.BFDF flag.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Initialization CR3.SDST = 1 Break Field [Break Field low width] detected Non-match Control Field 0 CR3.SDST = 1 [CF0RR] matches [CF0DR] Non-match Control Field 1 [CF1RR] matches [PCF1DR, SCF1DR], or both or the priority interrupt bit is detected. Information Frame Figure 33.67 State Transitions When Receiving a Start Frame R01UH0823EJ0110 Rev.1.
RX23W Group 33.10.3.1 33. Serial Communications Interface (SCIg, SCIh) Priority Interrupt Bit Figure 33.68 shows an example of operation in Start Frame reception where a priority interrupt bit is in use. Setting the CR1.PIBE bit to 1 enables the use of a priority interrupt bit. Operations of the extended serial mode control section in start Frame reception where a priority interrupt bit is in use are as described below. Steps (1) to (4) are the same as in Figure 33.64, for Start Frame reception.
RX23W Group 33.10.4 33. Serial Communications Interface (SCIg, SCIh) Detection of Bus Collisions Detection of bus collisions operate for cases where output of the Break Field low width and transmission of data are in progress when the ESMER.ESME bit and the SCI.TE bit are set to 1. Figure 33.69 shows an example of operations with bus collision detection. Signals output through TXDX12 and input through RXDX12 are sampled with the bus collision detection clock set with the CR2.
RX23W Group 33.10.5 33. Serial Communications Interface (SCIg, SCIh) Digital Filter for Input on the RXDX12 Pin Signals input through the RXDX12 pin can be passed through a digital filter before they are conveyed to the internal circuits. The digital filter consists of three flip-flop circuit stages connected in series and a match-detecting circuit. The CR2.DFCS[2:0] bits select the sampling clock for the RXDX12 pin input signals.
RX23W Group 33.10.6 33. Serial Communications Interface (SCIg, SCIh) Bit Rate Measurement The bit rate measurement function measures the intervals between rising and falling edges and between falling and rising edges of the signal input from the RXDX12 pin. Figure 33.71 shows an example of operations for bit rate measurement. (1) Writing 1 to the CR0.BRME bit enables bit rate measurement. Only set the BRME bit to 1 when you wish to proceed with bit rate measurement.
RX23W Group 33.10.7 33. Serial Communications Interface (SCIg, SCIh) Selectable Timing for Sampling Data Received through RXDX12 The extended serial mode control section provides a way of adjusting the timing for the sampling of data received through the RXDX12 pin by setting the CR2.RTS[1:0] bits to select the rising edges of 8th, 10th, 12th, or 14th cycle of the base clock. If the value of the SEMR.ABCS bit is 1, the bits select the rising edges of 4th, 5th, 6th, or 7th cycle of the base clock.
RX23W Group 33.10.8 33. Serial Communications Interface (SCIg, SCIh) Timer The timer has the following operating modes. (1) Break Field Low Width Output Mode This mode is for output through the TXDX12 pin of the low level over the Break Field low width at the transmission of a Start Frame. Setting the TMR.TOMS[1:0] bits to 10b switches operation to Break Field low width output mode. The TMR.TCSS[2:0] bits select the clock source for the counter. When the TCR.
RX23W Group (2) 33. Serial Communications Interface (SCIg, SCIh) Break Field Low Width Determination Mode This mode is for determining the Break Field low width in the input signal on the RXDX12 pin at the reception of a Start Frame. Setting the TMR.TOMS[1:0] bits to 01b switches operation to Break Field low width determination mode. The TMR.TCSS[2:0] bits select the clock source for the counter. When the TCR.TCST bit is set to 1, the interface enters the Break Field low width determinable state.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.11 Noise Cancellation Function Figure 33.75 shows the configuration of the noise filter used for noise cancellation. The noise filter consists of two stages of flip-flop circuits and a match-detection circuit. When the level on the pin matches in three consecutive samples taken at the set sampling interval, the matching level continues to be conveyed internally until the level on the pin again matches in three consecutive samples.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.12 Interrupt Sources 33.12.1 Buffer Operations for TXI and RXI Interrupts If the conditions for a TXI and RXI interrupt are satisfied while the interrupt status flag in the interrupt controller is 1, the SCI does not output the interrupt request but retains it internally (with a capacity for retention of one request per source).
RX23W Group 33.12.3 33. Serial Communications Interface (SCIg, SCIh) Interrupts in Smart Card Interface Mode Table 33.32 lists interrupt sources in smart card interface mode. A transmit end interrupt (TEI) request cannot be used in this mode. Table 33.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Interrupts in Simple I2C Mode 33.12.4 The interrupt sources in simple I2C mode are listed in Table 33.33. The STI interrupt is allocated to the transmit end interrupt (TEI) request. The receive error interrupt (ERI) request cannot be used. The DTC or DMAC can also be used to handle transfer in simple I2C mode. When the value of the SIMR2.
RX23W Group 33.12.5 33. Serial Communications Interface (SCIg, SCIh) Interrupt Requests from the Extended Serial Mode Control Section The extended serial mode control section has a total of six types of interrupt request for generating the SCIX0 interrupt (Break Field low width detected), SCIX1 interrupt (Control Field 0 match, Control Field 1 match, priority interrupt bit detected), SCIX2 interrupt (bus collision detected), and SCIX3 interrupt (valid edge detected).
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.13 Event Linking By employing interrupt request signals as event signals, SCI5 is able to provide linked operation through the event link controller (ELC) for modules selected in advance. Event signals can be output regardless of the values of the corresponding interrupt request enable bits.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) 33.14 Usage Notes 33.14.1 Setting the Module Stop Function Module stop control register B (MSTPCRB) and module stop control register C (MSTPCRC) are used to stop and start SCI operations. With the value after a reset, SCI operations are stopped. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption. 33.14.
RX23W Group 33.14.6 33. Serial Communications Interface (SCIg, SCIh) Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode and Simple SPI Mode) When the external clock source is used as a synchronization clock, the following restrictions apply. (1) Start of transmission Update the TDR register by the CPU, DMAC, or DTC and wait for at least five PCLK cycles before allowing the transmit clock to be input (refer to Figure 33.76).
RX23W Group 33.14.7 33. Serial Communications Interface (SCIg, SCIh) Restrictions on Using DMAC or DTC When using the DMAC or DTC to read the RDR, RDRH, and RDRL registers, be sure to set the receive data full interrupt (RXI) as the activation source of the relevant SCI. 33.14.8 Notes on Starting Transfer At the point where transfer starts when the interrupt status flag (IRn.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Data transmission No All data transmitted? [1] [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting the SCR.TE bit to 1, reading the SSR register, and writing data to the TDR register after canceling software standby mode. However, if the DMAC or DTC has been activated, the data remaining in the DMAC or DTC will be transmitted when both the TE and TIE bits in the SCR register are set to 1.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Transition to software standby mode Software standby mode canceled Port mode register (PMR) setting SCR.TE bit The level at transition to software standby mode is retained SCKn output pin TXDn output pin Port input/output Port Figure 33.
RX23W Group 33. Serial Communications Interface (SCIg, SCIh) Data reception RXI interrupt No [1] [ 1 ] Data being received is invalid. Yes Read receive data in RDR SCR.RE = 0 Make transition to software standby mode [2] [ 2 ] Setting for the module stop state is included. Cancel software standby mode Change operating mode? No Yes Initialization SCR.RE = 1 Start data reception Figure 33.80 33.14.
RX23W Group 33.14.11 (1) 33. Serial Communications Interface (SCIg, SCIh) Limitations on Simple SPI Mode Master Mode • Use a resistor to pull up or pull down the clock line matching the initial settings for the transfer clock set by the SPMR.CKPH and CKPOL bits when the SPMR.SSE bit is 1. This prevents the clock line from being placed in the high-impedance state when the SCR.TE bit is set to 0 or unexpected edges from being generated on the clock line when the SCR.TE bit is changed from 0 to 1.
RX23W Group 33.14.12 33. Serial Communications Interface (SCIg, SCIh) Limitation 1 on Usage of the Extended Serial Mode Control Section When the PCR.SHARPS bit is set to 1, output on the TXDX12/RXDX12 pin is only possible when the following conditions apply. • The timer is in Break Field low width output mode and the value of the TCR.
RX23W Group 33.14.14 33. Serial Communications Interface (SCIg, SCIh) Note on Transmit Enable Bit (TE Bit) When setting the pin function to “TXDn” while the SCR.TE bit is 0 (serial transmission is disabled) or setting the TE bit to 0 while the pin function is “TXDn”, output of the TXDn pin becomes high-impedance. Prevent the TXDn line from becoming high-impedance by any of the following ways: (1) Connect a pull-up resistor to the TXDn line.
RX23W Group 34. 34. IrDA Interface IrDA Interface The IrDA interface sends and receives IrDA data communication waveforms in cooperation with the SCI5 based on the IrDA (Infrared Data Association) standard 1.0. In this section, “PCLK” is used to refer to PCLKB. 34.1 Overview Enabling the IrDA function by using the IRE bit in the IRCR register allows encoding and decoding the TXD5 and RXD5 signals of the SCI5 to the waveforms conforming to the IrDA standard 1.0 (IRTXD5 and IRRXD5 pins).
RX23W Group 34.2 34. IrDA Interface Register Descriptions 34.2.1 IrDA Control Register (IRCR) Address(es): IRDA.IRCR 0008 8410h b7 b6 IRE Value after reset: 0 b5 b4 0 b2 IRTXIN IRRXIN V V IRCKS[2:0] 0 b3 0 0 0 b1 b0 — — 0 0 Bit Symbol Bit Name Description R/W b1, b0 — Reserved These bits are read as 0. The write value should be 0. R/W b2 IRRXINV IrRX Data Polarity Switching 0: IRRXD5 input is used as received data as is.
RX23W Group 34. IrDA Interface IRE Bit (IrDA Enable) This bit selects either normal serial communication or IrDA data communication as the function of the serial I/O pins. R01UH0823EJ0110 Rev.1.
RX23W Group 34.3 34. IrDA Interface Operation 34.3.1 Transmission In transmission, the signals output from the SCI5 (UART frames) are converted to the IR frame data through the IrDA interface (see Figure 34.2). When the IRCR.IRTXINV bit is 0 and data is 0, high-level pulses with 3/16 of the bit period are output (initial setting). The high-level pulse width can be changed by setting the IRCR.IRCKS[2:0] bits. The standard prescribes that the minimum high-level pulse width should be 1.
RX23W Group 34.3.2 34. IrDA Interface Reception In reception, the IR frame data is converted to the UART frame data through the IrDA interface and is input to the SCI5. Low-level data is input when the IRCR.IRRXINV bit is 0 and a high-level pulse is detected; high-level data is input when no pulse is detected for a 1-bit period. 34.3.3 Selecting High-Level Pulse Width The IRCKS[2:0] bits need to be set to encode waveforms that meet the IrDA standard (the minimum pulse width should be 1.
RX23W Group 34.4 34.4.1 34. IrDA Interface Usage Notes Module Stop Function Setting The IrDA can be enabled and disabled using module stop control register C (MSTPCRC). The IrDA is stopped after a reset. Registers can be accessed by releasing the module stop state. For details, refer to section 11, Low Power Consumption. 34.4.2 SCI5 Setting When using the IrDA, set the SCI5.SEMR.ABCS bit to 0 and SMR.STOP bit to 1 (2 stop bits). 34.4.
35. I2C-bus Interface (RIICa) RX23W Group 35. I2C-bus Interface (RIICa) This MCU has a single-channel I2C-bus interface (RIIC). The RIIC module conforms with the NXP I2C-bus (Inter-IC bus) interface and provides a subset of its functions. In this section, “PCLK” is used to refer to PCLKB. 35.1 Overview Table 35.1 lists the specifications of the RIIC, Figure 35.1 shows a block diagram of the RIIC, and Figure 35.
35. I2C-bus Interface (RIICa) RX23W Group Table 35.1 RIIC Specifications (2/2) Item Description Low power consumption function Module stop state can be set.
35. I2C-bus Interface (RIICa) RX23W Group VCC SCLin SCL SCL SDA SDA SCLout# SDAin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) Figure 35.2 SDA SCL SCLin SDA (Master) SCL SDAout# (Slave 2) I/O Pin Connection to the External Circuit (I2C-bus Configuration Example) The logic levels of the input signals for RIIC are CMOS when the I2C-bus is selected (ICMR3.SMBS bit is 0), or TTL when the SMBus is selected (ICMR3.SMBS bit is 1). Table 35.
35. I2C-bus Interface (RIICa) RX23W Group 35.2 Register Descriptions I2C-bus Control Register 1 (ICCR1) 35.2.1 Address(es): RIIC0.ICCR1 0008 8300h b7 b6 b5 ICE IICRST CLO 0 0 0 Value after reset: b4 b3 SOWP SCLO 1 1 b2 b1 b0 SDAO SCLI SDAI 1 1 1 Bit Symbol Bit Name Description R/W b0 SDAI SDA Line Monitor 0: SDA0 line is low. 1: SDA0 line is high. R b1 SCLI SCL Line Monitor 0: SCL0 line is low. 1: SCL0 line is high.
35. I2C-bus Interface (RIICa) RX23W Group CLO Bit (Additional SCL Output) This bit is used to output an additional SCL for debugging or error processing. Normally, set the bit to 0. Setting the bit to 1 in a normal communication state causes a communication error. For details on this function, refer to section 35.11.2, Additional SCL Output Function. IICRST Bit (I2C-bus Interface Internal Reset) This bit is used to reset the internal states of the RIIC.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Control Register 2 (ICCR2) 35.2.2 Address(es): RIIC0.ICCR2 0008 8301h b7 b6 b5 b4 b3 b2 b1 b0 BBSY MST TRS — SP RS ST — 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b0 — Reserved This bit is read as 0. The write value should be 0. R/W b1 ST Start Condition Generation Request 0: Does not request to generate a start condition. 1: Requests to generate a start condition.
RX23W Group 35. I2C-bus Interface (RIICa) RS Bit (Restart Condition Generation Request) This bit is used to request that a restart condition be generated in master mode. When this bit is set to 1 to request to generate a restart condition, a restart condition is generated when the BBSY flag is set to 1 (bus busy state) and the MST bit is set to 1 (master mode). For details on the restart condition generation, refer to section 35.10, Start Condition/Restart Condition/Stop Condition Generating Function.
RX23W Group 35. I2C-bus Interface (RIICa) TRS Bit (Transmit/Receive Mode) This bit indicates transmit or receive mode. The RIIC is in receive mode when the TRS bit is set to 0 and is in transmit mode when the bit is set to 1. Combination of this bit and the MST bit indicates the operating mode of the RIIC. The value of the TRS bit is automatically changed to 1 for transmission or 0 for reception in response to the generation or detection of a start condition and setting of the R/W# bit.
RX23W Group 35. I2C-bus Interface (RIICa) BBSY Flag (Bus Busy Detection Flag) The BBSY flag indicates whether the I2C-bus is occupied (bus busy state) or released (bus free state). This bit is set to 1 when the SDA0 line changes from high to low under the condition of SCL0 line = high, assuming that a start condition has been generated. The RIIC recognizes the SDA0 line changing from low to high while the SCL0 line is high as generation of the stop condition.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Mode Register 1 (ICMR1) 35.2.3 Address(es): RIIC0.ICMR1 0008 8302h b7 b6 MTWP Value after reset: 0 b5 b4 CKS[2:0] 0 0 b3 b2 BCWP 0 1 b1 b0 BC[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 BC[2:0] Bit Counter b2 R/W*1 b3 BCWP BC Write Protect 0: Enables a value to be written in the BC[2:0] bits. (This bit is read as 1.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Mode Register 2 (ICMR2) 35.2.4 Address(es): RIIC0.ICMR2 0008 8303h b7 b6 DLCS Value after reset: 0 b5 b4 SDDL[2:0] 0 0 b3 — 0 0 b2 b1 TMOH TMOL 1 b0 TMOS 1 0 Bit Symbol Bit Name Description R/W b0 TMOS Timeout Detection Time Select 0: Long mode is selected. 1: Short mode is selected. R/W b1 TMOL Timeout L Count Control 0: Count-up is disabled while the SCL0 line is low. 1: Count-up is enabled while the SCL0 line is low.
RX23W Group 35. I2C-bus Interface (RIICa) TMOL Bit (Timeout L Count Control) This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held low when the timeout function is enabled (ICFER.TMOE bit is 1). TMOH Bit (Timeout H Count Control) This bit is used to enable or disable the internal counter of the timeout function to count up while the SCL0 line is held high when the timeout function is enabled (ICFER.TMOE bit is 1).
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Mode Register 3 (ICMR3) 35.2.5 Address(es): RIIC0.ICMR3 0008 8304h b7 SMBS Value after reset: 0 b6 b5 b4 b3 b2 b1 WAIT RDRFS ACKW ACKBT ACKBR P 0 0 0 0 0 b0 NF[1:0] 0 0 Bit Symbol Bit Name Description R/W b1, b0 NF[1:0] Noise Filter Stage Select b1 b0 R/W b2 ACKBR Received Acknowledge 0: 0 is received as the acknowledgment bit (ACK reception). 1: 1 is received as the acknowledgment bit (NACK reception).
RX23W Group 35. I2C-bus Interface (RIICa) ACKBR Bit (Received Acknowledge) This bit is used to store the value of the acknowledgment bit received from the receiver in transmit mode. [Setting condition] • When 1 is received as the acknowledgment bit with the ICCR2.TRS bit set to 1 [Clearing conditions] • When 0 is received as the acknowledgment bit with the ICCR2.TRS bit set to 1 • When 1 is written to the ICCR1.IICRST bit while the ICCR1.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Function Enable Register (ICFER) 35.2.6 Address(es): RIIC0.ICFER 0008 8305h Value after reset: b7 b6 b5 — SCLE NFE 0 1 1 b4 b3 NACKE SALE 1 0 b2 b1 b0 NALE MALE TMOE 0 1 0 Bit Symbol Bit Name Description R/W b0 TMOE Timeout Function Enable 0: The timeout function is disabled. 1: The timeout function is enabled. R/W b1 MALE Master Arbitration-Lost Detection Enable 0: Master arbitration-lost detection is disabled.
RX23W Group 35. I2C-bus Interface (RIICa) NACKE Bit (NACK Reception Transfer Suspension Enable) This bit is used to specify whether to continue or discontinue the data transfer when NACK is received in transmit mode. Normally, set this bit to 1. When NACK is received with the NACKE bit set to 1, the next transfer operation is suspended. When the NACKE bit is 0, the next transfer operation is continued regardless of the value of the received acknowledgment bit.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Status Enable Register (ICSER) 35.2.7 Address(es): RIIC0.ICSER 0008 8306h b7 b6 b5 b4 HOAE — DIDE — 0 0 0 0 Value after reset: b3 b2 b1 b0 GCAE SAR2E SAR1E SAR0E 1 0 0 1 Bit Symbol Bit Name Description R/W b0 SAR0E Slave Address Register 0 Enable 0: Slave address in registers SARL0 and SARU0 is disabled. 1: Slave address in registers SARL0 and SARU0 is enabled.
RX23W Group 35. I2C-bus Interface (RIICa) HOAE Bit (Host Address Enable) This bit is used to specify whether to ignore received host address (0001 000b) when the ICMR3.SMBS bit is 1. When this bit is set to 1 while the ICMR3.SMBS bit is 1, if the received slave address matches the host address, the RIIC recognizes the received slave address as the host address independently of the slave addresses set in registers SARLy and SARUy (y = 0 to 2) and performs the receive operation. When the ICMR3.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Interrupt Enable Register (ICIER) 35.2.8 Address(es): RIIC0.ICIER 0008 8307h b7 b6 b5 b4 b3 b2 b1 b0 TIE TEIE RIE NAKIE SPIE STIE ALIE TMOIE 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b0 TMOIE Timeout Interrupt Request Enable 0: Timeout interrupt (TMOI) request is disabled. 1: Timeout interrupt (TMOI) request is enabled.
RX23W Group 35. I2C-bus Interface (RIICa) TEIE Bit (Transmit End Interrupt Request Enable) This bit is used to enable or disable transmit end interrupt (TEI) requests when the ICSR2.TEND flag is set to 1. An TEI interrupt request is canceled by setting the TEND flag or the TEIE bit to 0. TIE Bit (Transmit Data Empty Interrupt Request Enable) This bit is used to enable or disable transmit data empty interrupt (TXI) requests when the ICSR2.TDRE flag is set to 1. R01UH0823EJ0110 Rev.1.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Status Register 1 (ICSR1) 35.2.9 Address(es): RIIC0.ICSR1 0008 8308h b7 b6 b5 b4 b3 b2 b1 b0 HOA — DID — GCA AAS2 AAS1 AAS0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b0 AAS0 Slave Address 0 Detection Flag 0: Slave address 0 is not detected. 1: Slave address 0 is detected. R/(W) *1 b1 AAS1 Slave Address 1 Detection Flag 0: Slave address 1 is not detected. 1: Slave address 1 is detected.
RX23W Group 35. I2C-bus Interface (RIICa) For 10-bit address format: SARUy.FS bit = 1 • When the received slave address does not match a value of (11110b + SARUy.SVA[1:0] bits) with the ICSER.SARyE bit set to 1 (slave address y detection enabled) This flag is set to 0 at the rising edge of the ninth SCL in the first byte. • When the received slave address matches a value of (11110b + SARUy.SVA[1:0] bits) and the following address does not match the SARLy value with the ICSER.
RX23W Group 35. I2C-bus Interface (RIICa) (host address detection is enabled) This flag is set to 0 at the rising edge of the ninth SCL in the first byte. • When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset R01UH0823EJ0110 Rev.1.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Status Register 2 (ICSR2) 35.2.10 Address(es): RIIC0.ICSR2 0008 8309h b7 b6 TDRE TEND 0 0 Value after reset: b5 b4 b3 b2 RDRF NACKF STOP START 0 0 0 0 b1 b0 AL TMOF 0 0 Bit Symbol Bit Name Description R/W b0 TMOF Timeout Detection Flag 0: Timeout is not detected. 1: Timeout is detected. R/(W) *1 b1 AL Arbitration-Lost Flag 0: Arbitration is not lost. 1: Arbitration is lost.
35. I2C-bus Interface (RIICa) RX23W Group [Setting conditions] When master arbitration-lost detection is enabled: ICFER.MALE = 1 • When the internal SDA output state does not match the SDA0 line level at the rising edge of SCL except for the ACK period during data (including slave address) transmission in master transmit mode (when the SDA0 line is driven low while the internal SDA output is high (the SDA0 pin is in the high-impedance state)) • When a start condition is detected while the ICCR2.
RX23W Group 35. I2C-bus Interface (RIICa) NACKF Flag (NACK Detection Flag) [Setting condition] • When ACK is not received (NACK is received) from the receiver in transmit mode with the ICFER.NACKE bit set to 1 (transfer suspension enabled) [Clearing conditions] • When 0 is written to the NACKF bit after reading NACKF = 1 • When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset Note: When the NACKF flag is set to 1, the RIIC suspends data transmission/reception.
35. I2C-bus Interface (RIICa) RX23W Group 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) Address(es): RIIC0.SARL0 0008 830Ah, RIIC0.SARL1 0008 830Ch, RIIC0.
35. I2C-bus Interface (RIICa) RX23W Group 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) Address(es): RIIC0.SARU0 0008 830Bh, RIIC0.SARU1 0008 830Dh, RIIC0.SARU2 0008 830Fh Value after reset: b7 b6 b5 b4 b3 b2 b1 — — — — — SVA[1:0] 0 0 0 0 0 0 0 b0 FS 0 Bit Symbol Bit Name Description R/W b0 FS 7-Bit/10-Bit Address Format Select 0: The 7-bit address format is selected. 1: The 10-bit address format is selected.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Bit Rate Low-Level Register (ICBRL) 35.2.13 Address(es): RIIC0.ICBRL 0008 8310h Value after reset: b7 b6 b5 — — — 1 1 1 b4 b3 b2 b1 b0 1 1 BRL[4:0] 1 1 1 Bit Symbol Bit Name Description R/W b4 to b0 BRL[4:0] Bit Rate Low Period Low period of SCL R/W b7 to b5 — Reserved These bits are read as 1. The write value should be 1. R/W ICBRL is a 5-bit register to set the low period of SCL.
35. I2C-bus Interface (RIICa) RX23W Group I2C-bus Bit Rate High-Level Register (ICBRH) 35.2.14 Address(es): RIIC0.ICBRH 0008 8311h Value after reset: b7 b6 b5 — — — 1 1 1 b4 b3 b2 b1 b0 1 1 BRH[4:0] 1 1 1 Bit Symbol Bit Name Description R/W b4 to b0 BRH[4:0] Bit Rate High Period High period of SCL R/W b7 to b5 — Reserved These bits are read as 1. The write value should be 1. R/W ICBRH is a 5-bit register to set the high period of SCL. ICBRH is valid in master mode.
35. I2C-bus Interface (RIICa) RX23W Group Table 35.
35. I2C-bus Interface (RIICa) RX23W Group 35.2.15 I2C-bus Transmit Data Register (ICDRT) Address(es): RIIC0.ICDRT 0008 8312h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 1 1 When the ICDRT register detects a space in the I2C-bus shift register (ICDRS), it transfers the transmit data that has been written to the ICDRT register to the ICDRS register and starts transmitting data in transmit mode.
35. I2C-bus Interface (RIICa) RX23W Group 35.3 Operation 35.3.1 Communication Data Format The I2C-bus format consists of 8-bit data and 1-bit acknowledgment. The first byte following a start condition or restart condition is an address byte used to specify a slave device with which the master device communicates. The specified slave is valid until a new slave is specified or a stop condition is generated. Figure 35.3 shows the I2C-bus format, and Figure 35.4 shows the I2C-bus timing.
35. I2C-bus Interface (RIICa) RX23W Group 35.3.2 Initial Settings Before starting data transmission and reception, initialize the RIIC according to the procedure in Figure 35.5. Set the ICCR1.ICE bit to 1 (internal reset) after setting the ICCR1.IICRST bit to 1 (RIIC reset) with the ICCR1.ICE bit set to 0 (SCL0 and SDA0 pins in inactive state). This initializes the various flags and internal state of the ICSR1 register.
35. I2C-bus Interface (RIICa) RX23W Group 35.3.3 Master Transmit Operation In master transmit operation, the RIIC generates clock signals and sends data as the master device, and the slave device returns acknowledgments. Figure 35.6 shows an example of usage of master transmission and Figure 35.7 to Figure 35.9 show the timing of operations in master transmission. The following describes the procedure and operations for master transmission. (1) Initial settings. For details, refer to section 35.3.
35. I2C-bus Interface (RIICa) RX23W Group Master transmission [1] Initial settings Initial settings No ICCR2.BBSY = 0? [2] Check I2C-bus occupation and generate a start condition. Yes ICCR2.ST = 1 ICSR2.NACKF = 0? No Yes No ICSR2.TDRE = 1? Yes [3] Transmit slave address and W (first byte). [4] Check ACK and set transmit data. Write data to ICDRT register No All data transmitted? Yes No ICSR2.TEND = 1? Yes ICSR2.STOP = 0 [5] Check end of last data transmission and generate a stop condition.
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35. I2C-bus Interface (RIICa) RX23W Group 7 8 9 1 2 3 ACK b7 b6 b5 4 5 6 7 8 9 1 2 3 b4 b3 DATA n-1 b2 b1 b0 ACK b7 b6 b5 4 5 6 7 8 9 P b4 b3 DATA n b2 b1 b0 A/NA SCL0 SDA0 b1 b0 DATA n-2 BBSY MST TRS Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF ICDRT DATA n-1 ICDRS DATA n-2 DATA n DATA n-1 DATA n XXXX (Initial value/final receive data) ICDRR 0 (ACK) ACKBT 0 (ACK) ACKBR 0 (ACK) X (ACK/NACK) STOP SP Figure 35.9 35.3.
RX23W Group (4) (5) (6) (7) (8) (9) 35. I2C-bus Interface (RIICa) Because the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there was an error in communications, write 1 to the ICCR2.SP bit to generate a stop condition. For master reception from a device with a 10-bit address, start by using master transmission to send the 10-bit address, and then generate a restart condition.
35. I2C-bus Interface (RIICa) RX23W Group Master reception starts Initial settings No (1) Initial settings ICCR2.BBSY = 0? (2) Check I2C-bus occupation and generate a start condition. Yes ICCR2.ST = 1 No ICSR2.TDRE = 1? Yes Write the ICDRT register No (3) Transmit the slave address followed by R and check ACK. ICSR2.RDRF = 1? Yes No ICSR2.NACKF = 0? Yes ICMR3.
35. I2C-bus Interface (RIICa) RX23W Group Master reception Initial settings No [1] Initial settings ICCR2.BBSY = 0? [2] Check I2C-bus occupation and generate a start condition. Yes ICCR2.ST = 1 No ICSR2.TDRE = 1? Yes Write data to ICDRT register No [3] Transmit the slave address followed by R and check ACK. ICSR2.RDRF = 1? Yes No ICSR2.NACKF = 0? Yes Perform dummy read of ICDRR register No [4] Perform dummy read. ICSR2.
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35. I2C-bus Interface (RIICa) RX23W Group 35.3.5 Slave Transmit Operation In slave transmit operation, the master device outputs the SCL, the RIIC transmits data as a slave device, and the master device returns acknowledgments. Figure 35.15 shows an example of usage of slave transmission and Figure 35.16 and Figure 35.17 show the timing of operations in slave transmission. The following describes the procedure and operations for slave transmission. (1) Initial settings. For details, refer to section 35.
35. I2C-bus Interface (RIICa) RX23W Group Slave transmission [1] Initial settings Initial settings ICSR2.NACKF = 0? No Yes No ICSR2.TDRE = 1? Yes Write data to ICDRT register [2], [3] Check ACK bit and set transmit data (Checking of ACK not necessary immediately after address is received) No All data transmitted? Yes No ICSR2.TEND = 1? Yes Read ICDRR register [4] Dummy read to release the SCL ICSR2.STOP = 1? [5] Check stop condition generation No Yes ICSR2.
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35. I2C-bus Interface (RIICa) RX23W Group 35.3.6 Slave Receive Operation In slave receive operation, the master device outputs the SCL and transmit data, and the RIIC returns acknowledgments as a slave device. Figure 35.18 shows an example of usage of slave reception and Figure 35.19 and Figure 35.20 show the timing of operations in slave reception. The following describes the procedure and operations for slave reception. (1) Initial settings. For details, refer to section 35.3.2, Initial Settings.
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35. I2C-bus Interface (RIICa) RX23W Group 35.4 SCL Synchronization Circuit In generation of the SCL, the RIIC starts counting out the value for width at high level specified in the ICBRH register when it detects a rising edge on the SCL0 line and drives the SCL0 line low once counting of the width at high level is complete.
35. I2C-bus Interface (RIICa) RX23W Group 35.5 SDA Output Delay Function The RIIC module incorporates a function for delaying output on the SDA line. The delay can be applied to all output (generation of the start, restart, and stop conditions, data, and the ACK and NACK signals) on the SDA line.
35. I2C-bus Interface (RIICa) RX23W Group 35.6 Digital Noise Filters The states of the SCL0 and SDA0 pins are conveyed to the internal circuitry through analog noise filters and digital noise filters. Figure 35.23 is a block diagram of the digital noise filter. The on-chip digital noise filter of each RIIC consists of four flip-flop circuit stages connected in series and a match detection circuit. The number of effective stages in the digital noise filter is selected by the ICMR3.NF[1:0] bits.
35. I2C-bus Interface (RIICa) RX23W Group 35.7 Address Match Detection The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7bit or 10-bit slave addresses. 35.7.1 Slave-Address Match Detection The RIIC can set three unique slave addresses, and has a slave address detection function for each unique slave address. When the ICSER.
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35. I2C-bus Interface (RIICa) RX23W Group 35.7.2 Detection of the General Call Address The RIIC also has a facility for detecting the general call address (0000 000b + 0 (write)). This is enabled by setting the ICSER.GCAE bit to 1. If the address following a start or restart condition is 0000 000b + 1 (read) (start byte), the RIIC recognizes this as the address of a slave device with an “all-zero” address but not as the general call address.
35. I2C-bus Interface (RIICa) RX23W Group 35.7.3 Device-ID Address Detection The RIIC module has a function to detect device-ID addresses complying with the I2C-bus specification. When the RIIC receives 1111 100b as the first seven bits of the first byte following a start condition or a restart condition while the ICSER.DIDE bit set to 1, the RIIC recognizes the address as a device-ID address, sets the ICSR1.
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35. I2C-bus Interface (RIICa) RX23W Group 35.7.4 Host Address Detection The RIIC has a function to detect the host address while the SMBus is operating. When the ICSER.HOAE bit is set to 1 while the ICMR3.SMBS bit is 1, the RIIC can detect the host address (0001 000b) in slave receive mode (bits MST and TRS in the ICCR2 register are 00b). When the RIIC detects the host address, the ICSR1.HOA flag is set to 1 at the rising edge of the ninth SCL, and at the same time, the ICSR2.
35. I2C-bus Interface (RIICa) RX23W Group 35.8 Automatic Low-Hold Function for SCL 35.8.1 Function to Prevent Wrong Transmission of Transmit Data If the shift register (ICDRS) is empty when data have not been written to the I2C-bus transmit data register (ICDRT) with the RIIC in transmission mode (ICCR2.TRS bit is 1), the SCL0 line is automatically held low over the intervals shown below.
35. I2C-bus Interface (RIICa) RX23W Group 35.8.2 NACK Reception Transfer Suspension Function The RIIC has a function to suspend transfer operation when NACK is received in transmit mode (ICCR2.TRS bit is 1). This function is enabled when the ICFER.NACKE bit is set to 1 (transfer suspension enabled). If the next transmit data has already been written (ICSR2.TDRE flag is 0) when NACK is received, next data transmission at the falling edge of the ninth SCL is automatically suspended.
35. I2C-bus Interface (RIICa) RX23W Group 35.8.3 Function to Prevent Failure to Receive Data If response processing is delayed when receive data (ICDRR) read is delayed for a period of one transfer byte or more with receive data full (ICSR2.RDRF flag is 1) in receive mode (ICCR2.TRS bit is 0), the RIIC holds the SCL0 line low automatically immediately before the next data is received to prevent failure to receive data.
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35. I2C-bus Interface (RIICa) RX23W Group 35.9 Arbitration-Lost Detection Functions In addition to the normal arbitration-lost detection function defined by the I2C-bus specification, the RIIC has functions to prevent double-generation of a start condition, to detect arbitration-lost during transmission of NACK, and to detect arbitration-lost in slave transmit mode. 35.9.1 Master Arbitration-Lost Detection (MALE Bit) The RIIC drives the SDA0 line low to generate a start condition.
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35. I2C-bus Interface (RIICa) RX23W Group 35.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) The RIIC has a function to cause arbitration to be lost if the internal SDA output level does not match the level on the SDA0 line (the high output as the internal SDA output; i.e. the SDA0 pin is in the high-impedance state) and the low is detected on the SDA0 line during transmission of NACK in receive mode.
35. I2C-bus Interface (RIICa) RX23W Group Condition for arbitration-lost during NACK transmission • When the internal SDA output level does not match the SDA0 line (ACK is received) during transmission of NACK (ICMR3.ACKBT bit = 1) 35.9.3 Slave Arbitration-Lost Detection (SALE Bit) The RIIC has a function to cause arbitration to be lost if the data for transmission (i.e. the internal SDA output level) and the level on the SDA0 line do not match (the high output as the internal SDA output; i.e.
35. I2C-bus Interface (RIICa) RX23W Group 35.10 Start Condition/Restart Condition/Stop Condition Generating Function 35.10.1 Generating a Start Condition The RIIC generates a start condition when the ICCR2.ST bit is set to 1. When the ST bit is set to 1, a start condition generation request is made and the RIIC generates a start condition when the ICCR2.BBSY flag is 0 (bus free state). When a start condition is generated normally, the RIIC automatically shifts to the master transmit mode.
35. I2C-bus Interface (RIICa) RX23W Group 35.10.3 Generating a Stop Condition The RIIC generates a stop condition when the ICCR2.SP bit is set to 1. When the SP bit is set to 1, a stop condition generation request is made and the RIIC generates a stop condition when the ICCR2.BBSY flag is 1 (bus busy state) and the ICCR2.MST bit is 1 (master mode). A stop condition is generated in the following sequence. Stop condition generation (1) (2) (3) (4) Drive the SDA0 line low (high to low).
35. I2C-bus Interface (RIICa) RX23W Group 35.11 Bus Hanging If the clock signals from the master and slave devices go out of synchronization due to noise or other factors, the I2C-bus might hang with a fixed level on the SCL0 line and/or SDA0 line.
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35. I2C-bus Interface (RIICa) RX23W Group 35.11.2 Additional SCL Output Function In master mode, the RIIC module has a facility for the output of additional SCL to release the SDA0 line from being held low by the slave device due to the master being out of synchronization with the slave device.
35. I2C-bus Interface (RIICa) RX23W Group 35.11.3 RIIC Reset and Internal Reset The RIIC module incorporates a function for resetting itself. There are two types of reset. One is referred to as an RIIC reset; this initializes all registers including the ICCR2.BBSY flag. The other is referred to as an internal reset; this releases the RIIC from the slave-address matched state and initializes the internal counter while retaining other settings. After applying a reset, be sure to set the ICCR1.
35. I2C-bus Interface (RIICa) RX23W Group 35.12 SMBus Operation The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus communication, set the ICMR3.SMBS bit to 1. To use the transfer rate within a range of 10 kbps to 100 kbps of the SMBus specification, set the ICMR1.CKS[2:0] bits, the ICBRH register, and the ICBRL register. In addition, determine the values of the ICMR2.DLCS bit and the ICMR2.SDDL[2:0] bits to meet the data hold time (300 ns (min.)).
35. I2C-bus Interface (RIICa) RX23W Group SMBus specification TLOW:SEXT: Cumulative clock low extend time (slave device) TLOW:MEXT: Cumulative clock low extend time (master device) Start Clk ACK TLOW:MEXT S Stop TLOW:SEXT 1 2 7 8 9 Clk ACK TLOW:MEXT 1 2 7 8 9 Clk ACK TLOW:MEXT 1 2 7 8 TLOW:MEXT 9 P SCL0 SDA0 7-bit slave address R/W ACK Data ACK Data A/NA BBSY TDRE TEND RDRF RDRFS START STOP Measured with the MTU or TMR Figure 35.41 35.12.
35. I2C-bus Interface (RIICa) RX23W Group 35.13 Interrupt Sources The RIIC generates four types of interrupt request: transfer error or event generation (arbitration-lost, NACK detection, timeout detection, start condition detection, and stop condition detection), receive data full, transmit data empty, and transmit end. Table 35.6 lists details of the several interrupt requests. The receive data full and transmit data empty are both capable of activating data transfer by the DTC or DMAC. Table 35.
35. I2C-bus Interface (RIICa) RX23W Group 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected The RIIC can be reset by MCU reset, RIIC reset, and internal reset functions. Table 35.7 lists the reset states of registers and functions when a reset is applied or a condition is detected. Table 35.
35. I2C-bus Interface (RIICa) RX23W Group 35.15 Event Link Function (Output) The RIIC0 handles event output for the event link controller (ELC) corresponding to the following sources. • Communication error/ communication event • Receive data full • Transmit data empty • Transmit end 35.15.
35. I2C-bus Interface (RIICa) RX23W Group 35.16 Usage Notes 35.16.1 Setting Module Stop Function Module stop state can be entered or released using module stop control register B (MSTPCRB). The initial setting is for operation of the RIIC to be stopped. RIIC register access is enabled by releasing the module stop state. For details on module stop control register B, refer to section 11, Low Power Consumption. 35.16.
RX23W Group 36. CAN Module (RSCAN) 36. CAN Module (RSCAN) 36.1 Overview This MCU incorporates the Controller Area Network (CAN) module with one channel of CAN protocol controller conforming to the ISO 11898-1 standard. Table 36.1 shows the CAN module specifications. Figure 36.1 shows the CAN module block diagram. Table 36.2 lists the I/O pins of the CAN module. In this section, the following variables indicate the number of registers.
RX23W Group Table 36.1 36. CAN Module (RSCAN) CAN Module Specifications (2/2) Item Specification Transmit history function Stores the history information of transmitted messages. Bus off recovery mode selection Selects a method of returning from bus off state.
