User's Manual

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Table Of Contents

Cover
Notice
General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
How to Use This Manual
Contents
Features
1. Overview
- 1.1 Outline of Specifications
- 1.2 List of Products
- 1.3 Block Diagram
- 1.4 Pin Functions
- 1.5 Pin Assignments
- 1.6 List of Pins and Pin Functions
2. CPU
- 2.1 Features
- 2.2 Register Set of the CPU
- 2.3 Processor Mode
- 2.4 Data Types
- 2.5 Endian
- 2.6 Vector Table
  - 2.6.1 Exception Vector Table
  - 2.6.2 Interrupt Vector Table
- 2.7 Operation of Instructions
  - 2.7.1 Restrictions on RMPA and String-Manipulation Instructions
- 2.8 Number of Cycles
  - 2.8.1 Instruction and Number of Cycle
  - 2.8.2 Numbers of Cycles for Response to Interrupts
3. Operating Modes
- 3.1 Operating Mode Types and Selection
- 3.2 Register Descriptions
  - 3.2.1 Mode Monitor Register (MDMONR)
  - 3.2.2 System Control Register 1 (SYSCR1)
- 3.3 Details of Operating Modes
  - 3.3.1 Single-Chip Mode
  - 3.3.2 Boot Mode
    - 3.3.2.1 Boot Mode (USB Interface)
    - 3.3.2.2 Boot Mode (SCI)
- 3.4 Transitions of Operating Modes
  - 3.4.1 Operating Mode Transitions Determined by the Mode-Setting Pins
4. Address Space
- 4.1 Address Space
5. I/O Registers
- 5.1 I/O Register Addresses (Address Order)
6. Resets
- 6.1 Overview
- 6.2 Register Descriptions
- 6.3 Operation
7. Option-Setting Memory (OFSM)
- 7.1 Overview
- 7.2 Register Descriptions
- 7.3 Usage Note
  - 7.3.1 Setting Example of Option-Setting Memory
8. Voltage Detection Circuit (LVDAb)
- 8.1 Overview
- 8.2 Register Descriptions
- 8.3 VCC Input Voltage Monitor
  - 8.3.1 Monitoring Vdet0
  - 8.3.2 Monitoring Vdet1
- 8.4 Reset from Voltage Monitor 0
- 8.5 Interrupt and Reset from Voltage Monitoring 1
- 8.6 Event Link Output
  - 8.6.1 Interrupt Handling and Event Linking
9. Clock Generation Circuit
- 9.1 Overview
- 9.2 Register Descriptions
- 9.3 Main Clock Oscillator
- 9.4 Sub-Clock Oscillator
  - 9.4.1 Connecting 32.768-kHz Crystal
  - 9.4.2 Handling of Pins When Sub-Clock is Not Used
- 9.5 Dedicated Clock Oscillator for Bluetooth
  - 9.5.1 Connecting the Oscillator
  - 9.5.2 Connecting the Bluetooth-Dedicated Clock Output Pin
- 9.6 Oscillation Stop Detection Function
  - 9.6.1 Oscillation Stop Detection and Operation after Detection
  - 9.6.2 Oscillation Stop Detection Interrupts
- 9.7 PLL Circuit
- 9.8 Internal Clock
- 9.9 Usage Notes
10. Clock Frequency Accuracy Measurement Circuit (CAC)
- 10.1 Overview
- 10.2 Register Descriptions
- 10.3 Operation
  - 10.3.1 Measuring Clock Frequency
  - 10.3.2 Digital Filtering of Signals on the CACREF Pin
- 10.4 Interrupt Requests
- 10.5 Usage Notes
  - 10.5.1 Module Stop Function Setting
11. Low Power Consumption
- 11.1 Overview
- 11.2 Register Descriptions
- 11.3 Reducing Power Consumption by Switching Clock Signals
- 11.4 Module Stop Function
- 11.5 Function for Lower Operating Power Consumption
  - 11.5.1 Setting Operating Power Control Mode
- 11.6 Low Power Consumption Modes
- 11.7 Usage Notes
12. Battery Backup Function
- 12.1 Overview
- 12.2 Register Descriptions
- 12.3 Operation
  - 12.3.1 Battery Backup Function
  - 12.3.2 VBATT Pin Voltage Monitoring Function
- 12.4 Usage Notes
13. Register Write Protection Function
- 13.1 Register Descriptions
  - 13.1.1 Protect Register (PRCR)
14. Exception Handling
- 14.1 Exception Events
- 14.2 Exception Handling Procedure
- 14.3 Acceptance of Exception Events
  - 14.3.1 Acceptance Timing and Saved PC Value
  - 14.3.2 Vector and Site for Saving the Values in the PC and PSW
- 14.4 Hardware Processing for Accepting and Returning from Exceptions
- 14.5 Hardware Pre-Processing
- 14.6 Return from Exception Handling Routine
- 14.7 Priority of Exception Events
15. Interrupt Controller (ICUb)
- 15.1 Overview
- 15.2 Register Descriptions
- 15.3 Vector Table
- 15.4 Interrupt Operation
- 15.5 Non-maskable Interrupt Operation
- 15.6 Return from Power-Down States
  - 15.6.1 Return from Sleep Mode or Deep Sleep Mode
  - 15.6.2 Return from Software Standby Mode
- 15.7 Usage Note
  - 15.7.1 Note on WAIT Instruction Used with Non-Maskable Interrupt
16. Buses
- 16.1 Overview
- 16.2 Description of Buses
- 16.3 Register Descriptions
- 16.4 Bus Error Monitoring Section
- 16.5 Interrupt
  - 16.5.1 Interrupt Source
17. Memory-Protection Unit (MPU)
- 17.1 Overview
- 17.2 Register Descriptions
- 17.3 Functions
- 17.4 Procedures for Using Memory Protection
18. DMA Controller (DMACA)
- 18.1 Overview
- 18.2 Register Descriptions
- 18.3 Operation
- 18.4 Ending DMA Transfer
- 18.5 Interrupts
- 18.6 Event Link Function
- 18.7 Low Power Consumption Function
- 18.8 Usage Notes
19. Data Transfer Controller (DTCa)
- 19.1 Overview
- 19.2 Register Descriptions
- 19.3 Request Sources
  - 19.3.1 Allocating Transfer Information and DTC Vector Table
- 19.4 Operation

User’s Manual

www.renesas.com

RX23W Group

User’s Manual: Hardware

RENESAS 32-Bit MCU

RX Family ⁄ RX200 Series

Nov 2020

Rev.1.10

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

Cover

Summary of content (399 pages)

PAGE 1
User’s Manual 32 Cover RX23W Group User’s Manual: Hardware RENESAS 32-Bit MCU RX Family ⁄ RX200 Series All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).
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Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other use of the circuits, software, and information in the design of your product or system.
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General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1.
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How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers.
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2. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. X.X.X ... Register Address(es): xxxx xxxxh b7 b6 — Value after reset: x b5 ...[1:0] 0 0 b4 b3 b2 b1 b0 ...4 — — — ...0 0 0 0 0 0 x: Undefined Bit Symbol Bit Name Description b0 ...0 ...... 0: ......
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3.
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Contents Features ................................................................................................................................................... 51 1. Overview ........................................................................................................................................ 52 1.1 Outline of Specifications ..................................................................................................................... 52 1.2 List of Products ...............
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2.5.2 Access to I/O Registers ............................................................................................................... 91 2.5.3 Notes on Access to I/O Registers ............................................................................................... 91 2.5.4 Data Arrangement ....................................................................................................................... 92 2.5.4.1 Data Arrangement in Registers ......................................
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7. 6.3.1 RES# Pin Reset ......................................................................................................................... 147 6.3.2 Power-On Reset and Voltage Monitoring 0 Reset ................................................................... 147 6.3.3 Voltage Monitoring 1 Reset ..................................................................................................... 149 6.3.4 Independent Watchdog Timer Reset ....................................................
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9.2.8 Sub-Clock Oscillator Control Register (SOSCCR) .................................................................. 186 9.2.9 Low-Speed On-Chip Oscillator Control Register (LOCOCR) ................................................. 187 9.2.10 IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) ...................................... 188 9.2.11 High-Speed On-Chip Oscillator Control Register (HOCOCR) ............................................... 189 9.2.
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9.8.11 9.9 10. Usage Notes ....................................................................................................................................... 212 9.9.1 Notes on Clock Generation Circuit .......................................................................................... 212 9.9.2 Note on Rewriting the SCKCR3 Register ................................................................................ 212 9.9.3 Notes on Resonator .................................................
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11.6.1 Sleep Mode ............................................................................................................................... 249 11.6.1.1 Entry to Sleep Mode ........................................................................................................ 249 11.6.1.2 Exit from Sleep Mode ..................................................................................................... 250 11.6.1.3 Sleep Mode Return Clock Source Switching Function ......................
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15. 14.2 Exception Handling Procedure .......................................................................................................... 268 14.3 Acceptance of Exception Events ....................................................................................................... 270 14.3.1 Acceptance Timing and Saved PC Value ................................................................................. 270 14.3.2 Vector and Site for Saving the Values in the PC and PSW ..................
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15.4.1 Detecting Interrupts .................................................................................................................. 302 15.4.1.1 Operation of Status Flags for Edge-Detected Interrupts ................................................. 302 15.4.1.2 Operation of Status Flags for Level-Detected Interrupts ................................................ 304 15.4.2 Enabling and Disabling Interrupt Sources ..........................................................................
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17.1.1 Types of Access Control ........................................................................................................... 328 17.1.2 Regions for Access Control ...................................................................................................... 328 17.1.3 Background Region .................................................................................................................. 328 17.1.4 Overlap between Regions ..............................................
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18.2.11 DMA Status Register (DMSTS) ............................................................................................... 361 18.2.12 DMA Activation Source Flag Control Register (DMCSL) ...................................................... 363 18.2.13 DMA Module Activation Register (DMAST) .......................................................................... 364 18.3 18.3.1 Transfer Mode ..................................................................................................
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19.2.10 DTC Module Start Register (DTCST) ...................................................................................... 395 19.2.11 DTC Status Register (DTCSTS) ............................................................................................... 396 19.3 Request Sources ................................................................................................................................. 397 19.3.1 19.4 20. Allocating Transfer Information and DTC Vector Table ..........
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20.3.1 Relation between Interrupt Handling and Event Linking ......................................................... 430 20.3.2 Event Linkage ........................................................................................................................... 431 20.3.3 Operation of Peripheral Timer Modules When Event Signal is Input ..................................... 432 20.3.4 Operation of CTSU When Event Signal is Input ...................................................................
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22.3 23. Usage Notes ....................................................................................................................................... 477 22.3.1 Procedure for Specifying Input/Output Pin Function ............................................................... 477 22.3.2 Notes on MPC Register Setting ................................................................................................ 477 22.3.3 Note on Using Analog Functions .........................................
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23.3 Operation ........................................................................................................................................... 527 23.3.1 Basic Functions ......................................................................................................................... 527 23.3.2 Synchronous Operation ............................................................................................................ 533 23.3.3 Buffer Operation ...............................
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23.6.22 Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection ...... 614 23.6.23 Notes When Complementary PWM Mode Output Protection Functions are Not Used .......... 615 23.6.24 Points for Caution to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode .............................................................................................. 615 23.6.25 Continuous Output of Interrupt Signal in Response to a Compare Match ...............................
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25.2.1 Timer Control Register (TCR) ................................................................................................. 669 25.2.2 Timer Mode Register (TMDR) ................................................................................................. 673 25.2.3 Timer I/O Control Register (TIORH, TIORL, TIOR) .............................................................. 674 25.2.4 Timer Interrupt Enable Register (TIER) ...............................................................
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26. 25.9.14 Multiplexing of I/O Pins ........................................................................................................... 730 25.9.15 Continuous Output of Compare-Match Pulse Interrupt Signal ................................................ 731 25.9.16 Continuous Output of Input-Capture Pulse Interrupt Signal .................................................... 732 25.9.17 Continuous Output of Underflow Pulse Interrupt Signal ...................................................
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27. 26.8.8 Clock Source Setting with Cascaded Connection .................................................................... 761 26.8.9 Continuous Output of Compare Match Interrupt Signal .......................................................... 761 Compare Match Timer (CMT) ...................................................................................................... 762 27.1 Overview ...........................................................................................................
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28.2.15 Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register (BCNT2AER) ..... 786 28.2.16 Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable Register (BCNT3AER) ........................................................................................................................... 787 28.2.17 RTC Control Register 1 (RCR1) .............................................................................................. 788 28.2.18 RTC Control Register 2 (RCR2) ...........
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28.6.7 29. Initialization Procedure When the Realtime Clock is Not to be Used ..................................... 814 Low-Power Timer (LPT) ............................................................................................................... 815 29.1 Overview ........................................................................................................................................... 815 29.2 Register Descriptions ................................................................
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31.2.4 IWDT Reset Control Register (IWDTRCR) ............................................................................ 849 31.2.5 IWDT Count Stop Control Register (IWDTCSTPR) ............................................................... 850 31.2.6 Option Function Select Register 0 (OFS0) ............................................................................... 850 31.3 Operation ................................................................................................................
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32.2.17 BEMP Interrupt Status Register (BEMPSTS) .......................................................................... 891 32.2.18 Frame Number Register (FRMNUM) ...................................................................................... 892 32.2.19 USB Request Type Register (USBREQ) .................................................................................. 893 32.2.20 USB Request Value Register (USBVAL) .........................................................................
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32.3.3.15 EOFERR Interrupt ........................................................................................................... 940 32.3.3.16 Portable Device Detection Interrupt ................................................................................ 940 32.3.4 Pipe Control .............................................................................................................................. 941 32.3.4.1 Pipe Control Register Switching Procedures ................................
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33.2 Register Descriptions ......................................................................................................................... 977 33.2.1 Receive Shift Register (RSR) ................................................................................................... 977 33.2.2 Receive Data Register (RDR) ................................................................................................... 977 33.2.3 Receive Data Register H, L, HL (RDRH, RDRL, RDRHL) ...............
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33.3.1 Serial Data Transfer Format ................................................................................................... 1026 33.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode .................. 1028 33.3.3 Clock ....................................................................................................................................... 1029 33.3.4 Double-Speed Mode ....................................................................................
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33.8.6 Transmission and Reception of Serial Data (Simple SPI Mode) ........................................... 1083 33.9 Bit Rate Modulation Function ......................................................................................................... 1083 33.10 Extended Serial Mode Control Section: Description of Operation ................................................. 1084 33.10.1 Serial Transfer Protocol .......................................................................................
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34.3 34.3.1 Transmission ........................................................................................................................... 1118 34.3.2 Reception ................................................................................................................................ 1119 34.3.3 Selecting High-Level Pulse Width ......................................................................................... 1119 34.4 35. Operation .............................................
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35.7.2 Detection of the General Call Address ................................................................................... 1174 35.7.3 Device-ID Address Detection ................................................................................................. 1175 35.7.4 Host Address Detection .......................................................................................................... 1177 35.8 Automatic Low-Hold Function for SCL ..................................................
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36.2.8 Error Flag Register H (ERFLH) ............................................................................................. 1211 36.2.9 Global Configuration Register L (GCFGL) ........................................................................... 1212 36.2.10 Global Configuration Register H (GCFGH) .......................................................................... 1213 36.2.11 Global Control Register L (GCTRL) .......................................................................
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.2.49 Transmit/Receive FIFO Access Register 0AL (CFIDL0) ...................................................... 1245 36.2.50 Transmit/Receive FIFO Access Register 0AH (CFIDH0) ..................................................... 1246 36.2.51 Transmit/Receive FIFO Access Register 0BL (CFTS0) ........................................................ 1247 36.2.52 Transmit/Receive FIFO Access Register 0BH (CFPTR0) ..................................................... 1248 36.2.
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36.5.1 Transmit Priority Determination ............................................................................................ 1279 36.5.2 Transmission Using Transmit Buffers .................................................................................... 1280 36.5.3 Transmission Using FIFO Buffers ......................................................................................... 1280 36.5.4 Transmit History Function ....................................................................
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. 37.3.2 Non-Compressed Mode .......................................................................................................... 1324 37.3.3 WS Continue Mode ................................................................................................................ 1330 37.3.4 Operating States ...................................................................................................................... 1331 37.3.5 Transmit Operation .............................................
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38.3.4.1 When Parity is Disabled (SPCR2.SPPE = 0) ................................................................ 1375 38.3.4.2 When Parity is Enabled (SPCR2.SPPE = 1) ................................................................. 1379 38.3.5 Transfer Format ...................................................................................................................... 1383 38.3.5.1 CPHA = 0 ....................................................................................................
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39.2.3 40. CRC Data Output Register (CRCDOR) ................................................................................. 1423 39.3 Operation ......................................................................................................................................... 1424 39.4 Usage Notes ..................................................................................................................................... 1427 39.4.1 Module Stop Function Setting ......................
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40.3.6.1 Command Absent of Response Reception and Data Transfer ...................................... 1460 40.3.6.2 Command Absent of Data Transfer ............................................................................... 1461 40.3.6.3 Single Block Read Command (CMD17) ....................................................................... 1462 40.3.6.4 Single Block Write Command (CMD24) ...................................................................... 1464 40.3.6.
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.2.6 43. Random Number Generation .................................................................................................. 1500 42.3 Interrupt ........................................................................................................................................... 1501 42.4 Usage Notes ..................................................................................................................................... 1501 42.4.1 Standby Mode ............................
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.3.3 43.3.3.1 Sensor Stabilization Wait Time and Measurement Time .............................................. 1543 43.3.3.2 Interrupts ........................................................................................................................ 1544 43.4 44. Items Common to Multiple Modes ......................................................................................... 1543 Usage Notes ............................................................................................
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.2.25 A/D Compare Function Window A Lower-Side Level Setting Register (ADCMPDR0) ...... 1585 44.2.26 A/D Compare Function Window A Upper-Side Level Setting Register (ADCMPDR1) ...... 1587 44.2.27 A/D Compare Function Window A Channel Status Register 0 (ADCMPSR0) ..................... 1588 44.2.28 A/D Compare Function Window A Channel Status Register 1 (ADCMPSR1) ..................... 1589 44.2.29 A/D Compare Function Window A Extended Input Channel Status Register (ADCMPSER) .....................
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44.4.1 44.5 45. Interrupt Requests ................................................................................................................... 1630 Event Link Function ........................................................................................................................ 1631 44.5.1 Event Output to the ELC ........................................................................................................ 1631 44.5.2 12-Bit A/D Converter Operation by Event from the ELC ...
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. Temperature Sensor (TEMPSA) ................................................................................................ 1649 46.1 Overview ......................................................................................................................................... 1649 46.2 Register Descriptions ....................................................................................................................... 1650 46.2.1 46.3 47. Using the Temperature Sensor .................
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49. 50. RAM ........................................................................................................................................... 1676 49.1 Overview ......................................................................................................................................... 1676 49.2 Operation ......................................................................................................................................... 1676 49.2.
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50.7.2.1 Transition from E2 DataFlash Access Disable Mode to Read Mode ............................ 1702 50.7.2.2 Transition from Read Mode to P/E Mode ..................................................................... 1703 50.7.2.3 Transition from P/E Mode to Read Mode ..................................................................... 1705 50.7.3 Software Commands ............................................................................................................... 1707 50.7.
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50.10.8 50.10.8.1 User/Data Area Program Preparation ............................................................................ 1738 50.10.8.2 Program ......................................................................................................................... 1739 50.10.8.3 Data Area Program ........................................................................................................ 1740 50.10.8.4 Erase Preparation ..........................................................
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51.3.5.1 Timing of I/O Ports ....................................................................................................... 1795 51.3.5.2 Timing of MTU/TPU .................................................................................................... 1796 51.3.5.3 Timing of POE .............................................................................................................. 1797 51.3.5.4 Timing of TMR ........................................................................
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RX23W Group R01UH0823EJ0110 Rev.1.10 Nov 30, 2020 Renesas MCUs 54-MHz 32-bit RX MCUs, built-in FPU, 88.56 DMIPS, up to 512-KB flash memory, Bluetooth 5.0, various communication functions including USB 2.0 full-speed host/function/OTG, CAN, SD host interface, serial sound interface, capacitive touch sensing unit, 12-bit A/D converter, 12-bit D/A converter, RTC, Encryption functions Features PTBG0085KB-A 5.5 × 5.5 mm, 0.5 mm pitch ■ 32-bit RXv2 CPU core • Max. operating frequency: 54 MHz Capable of 88.
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RX23W Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.
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RX23W Group Table 1.1 1.
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RX23W Group Table 1.1 1.
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RX23W Group Table 1.1 1.
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RX23W Group Table 1.1 Classification 1. Overview Outline of Specifications (5/5) Module/Function Description Packages 85-pin BGA (PTBG0085KB-A) 5.5 × 5.5 mm, 0.5 mm pitch 83-pin LGA (PTLG0083KA-A) 6.1 × 9.5 mm, 0.5 mm pitch 56-pin QFN (PVQN0056LA-A) 7 × 7 mm, 0.4 mm pitch Debugging interfaces FINE interface R01UH0823EJ0110 Rev.1.
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RX23W Group Table 1.2 1.
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RX23W Group 1.2 1. Overview List of Products Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package type. Table 1.3 Group RX23W R List of Products: D Version (Ta = –40 to +85°C) Part No. Order Part No.
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RX23W Group 1.3 1. Overview Block Diagram Figure 1.2 shows a block diagram for the 85-pin BGA or 56-pin QFN product. SDHIa E2 DataFlash RSCAN WDTA CTSU IWDTa LPT ELC CRC SCIg × 3 channels (including IrDA × 1 channel) SCIh × 1 channel RSPIa × 1 channel RIICa × 1 channel Internal peripheral buses 1 to 6 SSI USB 2.
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RX23W Group 1. Overview Figure 1.3 shows a block diagram for the 83-pin LGA product. Pattern antenna VCC VSS VSS_RF INT_ANT … VSS_RF VCC VCC AVCC_RF VCC_RF ANT XTAL2_RF Dedicated crystal for the bluetooth 32MHz XTAL1_RF XTAL2_RF RX23W die DCLOUT DCLIN_D XTAL1_RF DCLIN_A … Note: Figure 1.3 The VCC_RF and AVCC_RF pins share the same external pin with the VCC pin. Block Diagram (83-Pin LGA) R01UH0823EJ0110 Rev.1.
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RX23W Group 1.4 1. Overview Pin Functions Table 1.4 lists the pin functions. Table 1.4 Pin Functions (1/4) Classifications Pin Name I/O Description Power supply VCC Input Power supply pin. Connect it to the system power supply. VCL — Connect this pin to the VSS pin via a 4.7 μF smoothing capacitor used to stabilize the internal power supply. Place the capacitor close to the pin. VSS Input Ground pin. Connect it to the system power supply (0 V).
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RX23W Group Table 1.4 1. Overview Pin Functions (2/4) Classifications Pin Name I/O Description Port output enable 2 POE0#, POE1#, POE3#, POE8# Input Input pins for request signals to place the MTU pins in the high impedance state. Realtime clock RTCOUT Output Output pin for the 1-Hz/64-Hz clock. RTCIC0, RTCIC1 Input Time capture event input pins. TMO0 to TMO2 Output Compare match output pins. TMCI0 to TMCI3 Input Input pins for the external clock to be input to the counter.
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RX23W Group Table 1.4 1. Overview Pin Functions (3/4) Classifications Pin Name I/O Description Serial peripheral interface RSPCKA I/O Input/output pin for the RSPI clock. MOSIA I/O Input/output pin for transmitting data from the RSPI master. MISOA I/O Input/output pin for transmitting data from the RSPI slave. SSLA0 I/O Input/output pin to select the slave for the RSPI. SSLA1, SSLA3 Output Output pins to select the slave for the RSPI. SSISCK0 I/O SSI serial bit clock pin.
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RX23W Group Table 1.4 1. Overview Pin Functions (4/4) Classifications Pin Name I/O Description I/O ports P03, P05, P07 I/O 3-bit input/output pins. Bluetooth low energy P14 to P17 I/O 4-bit input/output pins. P21, P22, P25 to P27 I/O 5-bit input/output pins. P30, P31, P35 to P37 I/O 5-bit input/output pins (P35 input pin). P40 to P47 I/O 8-bit input/output pins. PB0, PB1, PB3, PB5, PB7 I/O 5-bit input/output pins. PC0, PC2 to PC7 I/O 7-bit input/output pins.
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RX23W Group 1.5 1. Overview Pin Assignments 1.5.
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RX23W Group 1.5.2 1.
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RX23W Group 29 PC2 30 PC0 31 PB7 32 ANT 33 PB1 34 VCC 35 PB0 36 VSS 37 XTAL2_RF 38 XTAL1_RF 39 AVCC_RF 40 DCLOUT 41 PE4 56-Pin QFN 42 PE3 1.5.3 1. Overview PE2 43 28 VSS_RF VCC_RF 44 27 PC3 DCLIN_D 45 26 PC4 DCLIN_A 46 25 PC5 RX23W Group PVQN0056LA-A (56-pin QFN) (Top view) PD3 47 P47/CLKOUT_RF 48 P46 49 P45 50 P41 51 VREFL0 52 Figure 1.
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RX23W Group 1.6 1. Overview List of Pins and Pin Functions 1.6.1 85-Pin BGA Table 1.5 List of Pins and Pin Functions (85-Pin BGA) (1/2) I/O Port Timers (MTU, TPU, TMR, RTC, CMT, POE, CAC) A1 P25 MTIOC4C/MTCLKB/TIOCA4 A2 P30 MTIOC4B/TMRI3/POE8#/ RTCIC0 RXD1/SMISO1/SSCL1/ AUDIO_MCLK IRQ0/CMPOB3 IRQ7/CMPOB2 Pin No.
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RX23W Group Table 1.5 1. Overview List of Pins and Pin Functions (85-Pin BGA) (2/2) I/O Port Timers (MTU, TPU, TMR, RTC, CMT, POE, CAC) Communications (SCI, RSPI, RIIC, RSCAN, USB, SSI) PC6 MTIOC3C/MTCLKA/TMCI2 RXD8/SMISO8/SSCL8/MOSIA/ USB0_EXICEN F9 PD3 POE8# F10 P47 G1 PC4 MTIOC3D/MTCLKC/TMCI1/ POE0# CTS8#/RTS8#/SS8#/SSLA0/SCK5 PC5 MTIOC3B/MTCLKD/TMRI2 SCK8/RSPCKA/USB0_ID Pin No.
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RX23W Group 1.6.2 83-Pin LGA Table 1.6 Pin No. List of Pins and Pin Functions (83-Pin LGA) (1/2) Power Supply, Clock, System Control 1 2 3 1.
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RX23W Group Table 1.6 1. Overview List of Pins and Pin Functions (83-Pin LGA) (2/2) I/O Port Timers (MTU, TPU, TMR, RTC, CMT, POE, CAC) Communications (SCI, RSPI, RIIC, RSCAN, USB, SSI) 47 PC0 MTIOC3C/TCLKC CTS5#/RTS5#/SS5#/SSLA1 48 PC2 MTIOC4B/TCLKA RXD5/SMISO5/SSCL5/SSLA3/ IRRXD5 SDHI_D3 USB0_VBUS SDHI_CD Pin No.
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RX23W Group 1.6.3 1. Overview 56-Pin QFN Table 1.7 List of Pins and Pin Functions (56-Pin QFN) (1/2) Pin No.
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RX23W Group Table 1.7 Pin No. 1. Overview List of Pins and Pin Functions (56-Pin QFN) (2/2) Power Supply, Clock, System Control I/O Port Timers (MTU, TPU, TMR, RTC, CMT, POE, CAC) Communications (SCI, RSPI, RIIC, RSCAN, USB, SSI) Touch sensing Others 48 P47 AN007/ CLKOUT_RF 49 P46 AN006 50 P45 AN005 51 P41 AN001 P05 DA1 52 VREFL0 53 VREFH0 54 AVCC0 55 56 Note: AVSS0 VSS_RF is assigned as the exposed die pad. For details, refer to Appendix 2, Package Dimensions.
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RX23W Group 2. 2. CPU CPU The RXv2 instruction set architecture (RXv2) has upward compatibility with the RXv1 instruction set architecture (RXv1). • Adoption of variable-length instruction format As with RXv1, the RXv2 CPU has short formats for frequently used instructions, facilitating the development of efficient programs that take up less memory. • Powerful instruction set The RXv2 supports 109 selected instructions.
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RX23W Group 2.2 2. CPU Register Set of the CPU The RXv2 CPU has sixteen general-purpose registers, ten control registers, and two accumulator used for DSP instructions.
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RX23W Group 2.2.1 2. CPU General-Purpose Registers (R0 to R15) This CPU has sixteen 32-bit general-purpose registers (R0 to R15). R0 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW). 2.2.
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RX23W Group 2.2.2.1 2. CPU Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) b31 b0 ISP Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b31 0 b0 USP Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP).
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RX23W Group 2. CPU 2.2.2.
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RX23W Group 2. CPU C Flag (Carry Flag) This flag retains the state of the bit after a carry, borrow, or shift-out has occurred. Z Flag (Zero Flag) This flag is set to 1 if the result of an operation is 0; otherwise its value is cleared to 0. S Flag (Sign Flag) This flag is set to 1 if the result of an operation is negative; otherwise its value is cleared to 0. O Flag (Overflow Flag) This flag is set to 1 if the result of an operation overflows; otherwise its value is cleared to 0.
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RX23W Group 2.2.2.7 2. CPU Backup PSW (BPSW) b31 b0 Value after reset: Undefined The backup PSW (BPSW) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the processor status word (PSW) are saved in the BPSW. The allocation of bits in the BPSW corresponds to that in the PSW. 2.2.2.
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RX23W Group 2. CPU 2.2.2.
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RX23W Group 2. CPU Bit Symbol Bit Name Description R/W b31 FS Floating-Point Error Summary Flag This bit reflects the logical OR of the FU, FZ, FO, and FV flags. R Note 1. Note 2. Note 3. Note 4. Note 5. Note 6. Note 7. Note 8. Writing 0 to the bit clears it. Writing 1 to the bit does not affect its value. Positive denormalized numbers are treated as +0, negative denormalized numbers as –0. When the EV bit is set to 0, the FV flag is enabled. When the EO bit is set to 0, the FO flag is enabled.
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RX23W Group 2. CPU operation instruction, the bit decides whether the CPU will start handling the exception. When the bit is set to 0, the exception handling is masked; when the bit is set to 1, the exception handling is enabled.
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RX23W Group 2.3 2. CPU Processor Mode The RXv2 CPU supports two processor modes, supervisor and user. These processor modes and the memory protection function enable the realization of a hierarchical CPU resource protection and memory protection mechanism. Each processor mode imposes a level on rights of access to memory and the instructions that can be executed. Supervisor mode carries greater rights than user mode. The initial state after a reset is supervisor mode. 2.3.
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RX23W Group 2.4 2. CPU Data Types The RXv2 CPU can handle four types of data: integer, floating-point, bit, and string. For details, refer to RX Family RXv2 Instruction Set Architecture User's Manual: Software. 2.4.1 Integer An integer can be signed or unsigned. For signed integers, negative values are represented by two's complements.
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RX23W Group 2.4.2 2. CPU Floating-Points Floating-point support is for the single-precision floating-point type specified in the IEEE754 standard; operands of this type can be used in eleven floating-point operation instructions: FADD, FCMP, FDIV, FMUL, FSQRT, FSUB, FTOI, FTOU, ITOF, ROUND, and UTOF. b31 Single-precision floating-point b0 S E F S: Sign (1 bit) E: Exponent (8 bits) F: Mantissa (23 bits) Value = (-1)S × (1 + F × 2-23) × 2(E-127) Figure 2.
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RX23W Group 2.4.4 2. CPU Strings The string data type consists of an arbitrary number of consecutive byte (8-bit), word (16-bit), or longword (32-bit) units. Seven string manipulation instructions are provided for use with strings: SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, and SWHILE. String of byte (8-bit) data 8 String of word (16-bit) data 16 String of longword (32-bit) data 32 Figure 2.5 String R01UH0823EJ0110 Rev.1.
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RX23W Group 2.5 2. CPU Endian For the RXv2 CPU, instructions are little endian, but the treatment of data is selectable as little or big endian. 2.5.1 Switching the Endian As arrangements of bytes, this MCU supports both big endian, where the higher-order byte (MSB) is at location 0, and little endian, where the lower-order byte (LSB) is at location 0. For details on the endian setting, see section 3, Operating Modes.
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RX23W Group Table 2.3 2.
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RX23W Group Table 2.6 2.
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RX23W Group Table 2.10 2. CPU 8-Bit Read Operations when Big Endian has been Selected Operation Address of src Reading an 8-bit unit from address 1 Reading an 8-bit unit from address 2 Reading an 8-bit unit from address 3 Address 0 Transfer to LL — — — Address 1 — Transfer to LL — — Address 2 — — Transfer to LL — Address 3 — — — Transfer to LL Writing an 8-bit unit to address 1 Writing an 8-bit unit to address 2 Writing an 8-bit unit to address 3 Table 2.
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RX23W Group 2.5.4 2. CPU Data Arrangement 2.5.4.1 Data Arrangement in Registers Figure 2.6 shows the relation between the sizes of registers and bit numbers. b7 b0 Byte (8-bit) data b15 b0 Word (16-bit) data b31 b0 MSB LSB Longword (32-bit) data Figure 2.6 Data Arrangement in Registers 2.5.4.2 Data Arrangement in Memory Data in memory have three sizes: byte (8-bit), word (16-bit), and longword (32-bit). The data arrangement is selectable as little endian or big endian. Figure 2.
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RX23W Group 2.6 2. CPU Vector Table There are two types of vector table: exception and interrupt. Each vector in the vector table consists of four bytes and specifies the address where the corresponding exception handling routine starts. 2.6.
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RX23W Group 2.6.2 2. CPU Interrupt Vector Table The address where the interrupt vector table is placed can be adjusted. The table is a 1,024-byte region that contains all vectors for unconditional traps and interrupts and starts at the address (IntBase) specified in the interrupt table register (INTB). Figure 2.9 shows the interrupt vector table. Each vector in the interrupt vector table has a vector number from 0 to 255.
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RX23W Group 2.7 2.7.1 2.7.1.1 2. CPU Operation of Instructions Restrictions on RMPA and String-Manipulation Instructions Transfer Size and Data Prefetching The RMPA instruction and the string-manipulation instructions (SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, and SWHILE instructions) transfer data in longword units to speed up the reading of data from and writing of data to the memory.
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RX23W Group 2.8 2. CPU Number of Cycles 2.8.1 Instruction and Number of Cycle Table 2.13 to Table 2.20 show the number of cycles in operation of each instruction. The listed numbers of cycles for access to memory are the numbers of cycles during no-wait access. The operands in the table below indicate the following meanings. #IMM: Immediate flag: bit, flag Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register As, Ad: Accumulator CR: Control register dsp: displacement pcdsp: displacement Table 2.
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RX23W Group Table 2.14 2.
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RX23W Group Table 2.16 2. CPU Number of Cycles for Branch Instructions Mnemonic (indicates the common operation when the size is omitted) Instruction Branch instructions Number of Cycles • BCnd “pcdsp” • {BRA, BSR} “pcdsp”/“Rs” • {JMP, JSR} “Rs” Branch taken: 3 Branch not taken: 1 • RTE 6 • RTFI 3 • RTS 5 • RTSD “#IMM” 5 • RTSD “#IMM, Rd-Rd2” Throughput: n<5?5:1+n Latency: n<4?5:2+n n: Number of registers*1 ?: Conditional operator Note 1.
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RX23W Group Table 2.19 2. CPU Number of Cycles for String Manipulation Instructions Mnemonic (indicates the common operation when the size is omitted) Instruction String manipulation instructions*1 Number of Cycles • SCMPU 2+4×floor(n/4)+4×(n%4) n: Number of comparison bytes*2 • SMOVB n>3?6+3×floor(n/4)+3×(n%4):2+3n n: Number of transfer bytes*2 • SMOVF, SMOVU 2+3×floor(n/4)+3×(n%4) n: Number of transfer bytes*2 • SSTR.B 2+floor(n/4)+n%4 n: Number of transfer bytes*2 • SSTR.
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RX23W Group 2.8.2 2. CPU Numbers of Cycles for Response to Interrupts Table 2.21 lists numbers of cycles taken by processing for response to interrupts. Table 2.
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RX23W Group 3. Operating Modes 3. Operating Modes 3.1 Operating Mode Types and Selection There are two types of operating-mode selection: one is be selected by the level on pins at the time of release from the reset state, and the other is selected by software after release from the reset state. Table 3.1 shows the relationship between levels on the mode-setting pins (MD, UB) on release from the reset state and the operating mode selected at that time.
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RX23W Group 3.2 3. Operating Modes Register Descriptions 3.2.1 Mode Monitor Register (MDMONR) Address(es): 0008 0000h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — — — — — — — — MD 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0/1*1 Value after reset: Bit Symbol Bit Name Description R/W b0 MD MD Pin Status Flag 0: The MD pin is low. 1: The MD pin is high. R b7 to b1 — Reserved These bits are read as 0.
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RX23W Group 3.2.2 3. Operating Modes System Control Register 1 (SYSCR1) Address(es): 0008 0008h Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — — — — — — — — RAME 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R/W b0 RAME RAM Enable 0: The RAM is disabled. 1: The RAM is enabled. R/W b15 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note: Set the PRCR.
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RX23W Group 3.3 3.3.1 3. Operating Modes Details of Operating Modes Single-Chip Mode In this mode, all I/O ports can be used as general input/output ports, peripheral function input/output, or interrupt input pins. The chip starts up in single-chip mode if the high level is on the MD pin on release from the reset state. 3.3.2 Boot Mode In this mode, the on-chip flash memory modifying program (boot program) stored in a dedicated area within the MCU operates.
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RX23W Group 3.4 3. Operating Modes Transitions of Operating Modes 3.4.1 Operating Mode Transitions Determined by the Mode-Setting Pins Figure 3.1 shows operating mode transitions determined by the settings of the MD pin and the UB pin. Reset MD = High RES# = High RES# = Low MD = Low UB = Low RES# = High RES# = Low Single-chip mode MD = Low UB = High RES# = High Boot mode (SCI) RES# = Low Boot mode (USB interface) Figure 3.1 Mode-Setting Pin Levels and Operating Modes R01UH0823EJ0110 Rev.1.
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RX23W Group 4. Address Space 4.1 Address Space 4. Address Space This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figure 4.1 shows the memory maps in the respective operating modes. R01UH0823EJ0110 Rev.1.
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RX23W Group 4. Address Space Single-chip mode*1 0000 0000h RAM*2 0001 0000h Reserved area*3 0008 0000h Peripheral I/O registers 0010 0000h On-chip ROM (E2 Data Flash) 0010 2000h Reserved area*3 007F C000h 007F C500h Peripheral I/O registers 007F FC00h 0080 0000h Peripheral I/O registers Reserved area*3 Reserved area*3 FFF8 0000h FFFF FFFFh On-chip ROM (program ROM) (read only)*2 Note 1. The capacity of ROM differs depending on the products.
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RX23W Group 5. 5. I/O Registers I/O Registers This section provides information on the on-chip I/O register addresses and bit configuration. The information is given as shown below. Notes on writing to registers are also given below. (1) I/O register addresses (address order) • Registers are listed from the lower allocation addresses. • Registers are classified according to module symbols. • Numbers of cycles for access indicate numbers of cycles of the given base clock.
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RX23W Group 5. I/O Registers • Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L #SFR_DATA, [R1] CMP [R1].L, R1 ;; Next process If multiple registers are written to and a subsequent instruction should be executed after the write operations are entirely completed, only read the I/O register that was last written to and execute the operation using the value; it is not necessary to read or execute operation for all the registers that were written to.
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RX23W Group 5.1 5. I/O Registers I/O Register Addresses (Address Order) Table 5.1 List of I/O Registers (Address Order) (1/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (2/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size 0008 2004h DMAC0 DMA Destination Address Register DMDAR 32 32 2 ICLK section 18. 0008 2008h DMAC0 DMA Transfer Count Register DMCRA 32 32 2 ICLK section 18. ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (3/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (4/31) Number of Access Cycles Module Symbol Register Name Register Symbol Number of Bits 0008 8006h CMT0 Compare Match Constant Register CMCOR 16 16 2 or 3 PCLKB 2 ICLK section 27. 0008 8008h CMT1 Compare Match Timer Control Register CMCR 16 16 2 or 3 PCLKB 2 ICLK section 27. section 27.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (5/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (6/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (7/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size 0008 838Fh RSPI0 RSPI Control Register 2 SPCR2 8 8 2 or 3 PCLKB 2 ICLK section 38. 0008 8390h RSPI0 RSPI Command Register 0 SPCMD0 16 16 2 or 3 PCLKB 2 ICLK section 38. 0008 8392h RSPI0 RSPI Command Register 1 SPCMD1 16 16 2 or 3 PCLKB 2 ICLK section 38.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (8/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (9/31) Number of Access Cycles Module Symbol Register Name 0008 90E7h S12AD A/D Sampling State Register 7 ADSSTR7 8 8 2 or 3 PCLKB 2 ICLK section 44. 0008 A020h SCI1 Serial Mode Register SMR 8 8 2 or 3 PCLKB 2 ICLK section 33. 0008 A020h SMCI1 Serial Mode Register SMR 8 8 2 or 3 PCLKB 2 ICLK section 33. 0008 A021h SCI1 Bit Rate Register BRR 8 8 2 or 3 PCLKB 2 ICLK section 33.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (10/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5.
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RX23W Group Table 5.1 5.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (13/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (14/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (15/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (16/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (17/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (18/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (20/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size 000A 007Ch USB0 Pipe7 Control Register PIPE7CTR 16 000A 007Eh USB0 Pipe8 Control Register PIPE8CTR 000A 0080h USB0 Pipe9 Control Register 000A 0090h USB0 000A 0092h Reference Section ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (22/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (23/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (24/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size 000A 83DEh RSCAN Receive Buffer Register 3DH RMDF33 16 16 2 or 3 PCLKB 2 ICLK section 36. 000A 83E0h RSCAN Receive Rule Entry Register 5BL GAFLML5 16 16 2 or 3 PCLKB 2 ICLK section 36. 000A 83E0h RSCAN Receive Buffer Register 4AL RMIDL4 16 16 2 or 3 PCLKB 2 ICLK section 36.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (25/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (26/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (27/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size 000A 8496h RSCAN Receive Buffer Register 15BH RMPTR15 16 16 2 or 3 PCLKB 2 ICLK section 36. 000A 8498h RSCAN Receive Buffer Register 15CL RMDF015 16 16 2 or 3 PCLKB 2 ICLK section 36.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (28/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (29/31) Number of Access Cycles Address Module Symbol Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group Table 5.1 5.
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RX23W Group Table 5.1 5. I/O Registers List of I/O Registers (Address Order) (31/31) Number of Access Cycles Module Symbol Address Register Name Register Symbol Number of Bits Access Size ICLK ≥ PCLK ICLK
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RX23W Group 6. Resets 6. Resets 6.1 Overview The following resets are implemented: RES# pin reset, power-on reset, voltage monitoring 0 reset, voltage monitoring 1 reset, independent watchdog timer reset, watchdog timer reset, and software reset. Table 6.1 lists the reset names and sources. Table 6.1 Reset Names and Sources Reset Name Source RES# pin reset Voltage input to the RES# pin is driven low.
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RX23W Group 6. Resets The internal state and pins are initialized by a reset. Table 6.2 lists the reset targets to be initialized. Table 6.2 Targets Initialized by Each Reset Source Reset Source Target to be Initialized RES# Pin Reset Power-On Reset Voltage Monitoring 0 Reset Independent Watchdog Timer Reset Watchdog Timer Reset Voltage Monitoring 1 Reset Software Reset  — — — — — — —*1  — — — — — Voltage monitoring 0 reset detect flag (RSTSR0.
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RX23W Group 6.2 6. Resets Register Descriptions 6.2.1 Reset Status Register 0 (RSTSR0) Address(es): 0008 C290h Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 LVD1R LVD0R PORF F F 0*1 0*1 0*1 Bit Symbol Bit Name Description R/W b0 PORF Power-On Reset Detect Flag 0: Power-on reset not detected. 1: Power-on reset detected. R(/W) Voltage Monitoring 0 Reset Detect Flag 0: Voltage monitoring 0 reset not detected. 1: Voltage monitoring 0 reset detected.
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RX23W Group 6.2.2 6. Resets Reset Status Register 1 (RSTSR1) Address(es): 0008 C291h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — CWSF 0 0 0 0 0 0 0 0/1*1 Bit Symbol Bit Name Description R/W b0 CWSF Cold/Warm Start Determination Flag 0: Cold start 1: Warm start R(/W) These bits are read as 0. The write value should be 0. R/W b7 to b1 — Reserved *2 Note 1. The value after reset depends on the reset source. Note 2.
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RX23W Group 6.2.3 6. Resets Reset Status Register 2 (RSTSR2) Address(es): 0008 00C0h Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 SWRF WDTR IWDTR F F 0*1 0*1 0*1 Bit Symbol Bit Name Description R/W b0 IWDTRF Independent Watchdog Timer Reset Detect Flag 0: Independent watchdog timer reset not detected. 1: Independent watchdog timer reset detected. *2 Watchdog Timer Reset Detect Flag 0: Watchdog timer reset not detected. 1: Watchdog timer reset detected.
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RX23W Group 6.2.4 6. Resets Software Reset Register (SWRR) Address(es): 0008 00C2h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 SWRR[15:0] Value after reset: 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b15 to b0 SWRR[15:0] Software Reset Writing A501h resets the MCU. These bits are read as 0000h. R/W Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register. R01UH0823EJ0110 Rev.1.
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RX23W Group 6.3 6.3.1 6. Resets Operation RES# Pin Reset This is a reset generated by the RES# pin. When the RES# pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to unfailingly reset the LSI, the RES# pin should be held low for the specified power supply stabilization time at a power-on.
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RX23W Group 6. Resets VCC 4.7 kΩ (reference value) RES# Vdet0 *4 VPOR *1 External voltage VCC RES# pin*2 Power-on reset state Voltage monitoring 0 reset state POR detection signal (Low is valid) LVD0 enable/disable signal (Low is valid) Set by OFS1.LVDAS Voltage detection 0 signal (Low is valid) Internal reset signal RSTSR0.PORF tPOR*3 tLVD*3 Reset by a pin reset RSTSR0.LVD0RF Note: For details on the electrical characteristics, see the Electrical Characteristics section. Note 1.
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RX23W Group 6.3.3 6. Resets Voltage Monitoring 1 Reset The voltage monitoring 1 reset is internal resets generated by the voltage monitoring circuit.
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RX23W Group 6.3.4 6. Resets Independent Watchdog Timer Reset Independent watchdog timer reset is an internal reset generated by the independent watchdog timer. Output of the independent watchdog timer reset from the independent watchdog timer can be selected by setting the IWDT reset control register (IWDTRCR) and option function select register 0 (OFS0).
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RX23W Group 6.3.7 6. Resets Determination of Cold/Warm Start By reading the CWSF flag in RSTSR1, the type of reset processing caused can be identified; that is, whether a power-on reset has caused the reset processing (cold start) or a reset signal input during operation has caused the reset processing (warm start). The CWSF flag in RSTSR1 is set to 0 when a power-on reset occurs (cold start); otherwise the flag is not set to 0.
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RX23W Group 6.3.8 6. Resets Determination of Reset Generation Source Reading RSTSR0 and RSTSR2 determines which reset was used to execute the reset exception handling. Figure 6.4 shows an example of the flow to identify a reset generation source. Reset exception handling RSTSR2. SWRF = 1 Yes No RSTSR0. LVD1RF = 1 Yes No RSTSR2. WDTRF = 1 Yes No RSTSR2. IWDTRF = 1 Yes No RSTSR0. LVD0RF = 1 Yes No RSTSR0. PORF = 1 Yes Software reset Figure 6.
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RX23W Group 7. Option-Setting Memory (OFSM) 7. Option-Setting Memory (OFSM) 7.1 Overview Option-setting memory (OFSM) refers to a set of registers that are provided for selecting the state of the microcontroller after a reset. The option-setting memory is allocated in the ROM. Figure 7.1 shows the option-setting memory area.
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RX23W Group 7.2 7. Option-Setting Memory (OFSM) Register Descriptions 7.2.1 Option Function Select Register 0 (OFS0) Address(es): OFSM.
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RX23W Group 7.
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RX23W Group 7. Option-Setting Memory (OFSM) counted by the counter. The value of the window end position must be smaller than the value of the window start position (window start position > window end position). If the value for the window end position is greater than the value for the window start position, only the value for the window start position is effective.
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RX23W Group 7. Option-Setting Memory (OFSM) WDTRPSS[1:0] Bits (WDT Window Start Position Select) These bits select the position where the window for the down-counter starts as 25%, 50%, 75%, or 100% of the value being counted (the point at which counting starts is 100% and the point at which an underflow occurs is 0%). The interval between the positions where the window starts and ends becomes the period in which refreshing is possible, and refreshing is not possible outside this period.
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RX23W Group 7.2.2 7. Option-Setting Memory (OFSM) Option Function Select Register 1 (OFS1) Address(es): OFSM.
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RX23W Group 7. Option-Setting Memory (OFSM) HOCOEN Bit (HOCO Oscillation Enable) This bit selects whether the HOCO oscillation is effective or not after a reset. Setting the HOCOEN bit to 0 allows the HOCO oscillation to be started before the CPU starts operation, and therefore reduces the wait time for oscillation stabilization. Note that even if the HOCOEN bit is set to 0, the system clock source is not switched to HOCO.
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RX23W Group 7.3 7.3.1 7. Option-Setting Memory (OFSM) Usage Note Setting Example of Option-Setting Memory Since the option-setting memory is allocated in the ROM, values cannot be written by executing instructions. Write appropriate values when writing the program. Examples of the settings are shown below. • To set FFFF FFF8h in the OFS0 register .ORG 0FFFFFF8CH .LWORD 0FFFFFFF8H • To set FFFF FEF0h in the OFS1 register .ORG 0FFFFFF88H .LWORD 0FFFFFEF0H .ORG 0FFFF7F88H .
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RX23W Group 8. 8. Voltage Detection Circuit (LVDAb) Voltage Detection Circuit (LVDAb) The voltage detection circuit (LVD) monitors the voltage level input to the VCC pin using a program. 8.1 Overview In voltage detection 0, the detection voltage can be selected from three levels using option function select register 1 (OFS1). In voltage detection 1, the detection voltage can be selected from 10 levels using the voltage detection level select register (LVDLVLR).
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RX23W Group 8.
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RX23W Group 8.2 8. Voltage Detection Circuit (LVDAb) Register Descriptions 8.2.
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RX23W Group 8.2.2 8.
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RX23W Group 8.2.3 8. Voltage Detection Circuit (LVDAb) Voltage Monitoring Circuit Control Register (LVCMPCR) Address(es): 0008 C297h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — LVD1E — — — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 8.2.4 8. Voltage Detection Circuit (LVDAb) Voltage Detection Level Select Register (LVDLVLR) Address(es): 0008 C298h Value after reset: b7 b6 b5 b4 — — — — 0 0 0 0 b3 b2 b1 b0 LVD1LVL[3:0] 0 1 1 1 Bit Symbol Bit Name Description R/W b3 to b0 LVD1LVL[3:0] Voltage Detection 1 Level Select (Standard voltage during drop in voltage) b3 R/W b7 to b4 — Reserved These bits are read as 0. The write value should be 0. R/W Note: b0 0 1 0 0: 3.10 V 0 1 0 1: 3.
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RX23W Group 8.2.5 8. Voltage Detection Circuit (LVDAb) Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0) Address(es): 0008 C29Ah b7 b6 LVD1R LVD1RI N Value after reset: 1 0 b5 b4 b3 b2 b1 b0 — — — LVD1C MPE — LVD1RI E 0 0 X 0 0 0 x: Undefined Bit Symbol Bit Name Description R/W b0 LVD1RIE Voltage Monitoring 1 Interrupt/Reset Enable 0: Disabled 1: Enabled R/W b1 — Reserved This bit is read as 0. The write value should be 0.
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RX23W Group 8.3 8.3.1 8. Voltage Detection Circuit (LVDAb) VCC Input Voltage Monitor Monitoring Vdet0 Monitoring Vdet0 is not possible. 8.3.2 Monitoring Vdet1 After making the following settings, the LVD1SR.LVD1MON flag can be used to monitor the results of comparison by voltage monitor 1. (1) Specify the detection voltage by setting the LVDLVLR.LVD1LVL[3:0] bits (voltage detection 1 level select). (2) Set the LVCMPCR.LVD1E bit to 1 (voltage detection 1 circuit enabled).
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RX23W Group 8.4 8. Voltage Detection Circuit (LVDAb) Reset from Voltage Monitor 0 When using the reset from voltage monitor 0, clear the voltage detection 0 circuit start bit (OFS1.LVDAS) to 0 (enabling the voltage monitor 0 reset after a reset). Figure 8.3 shows an example of operations for a voltage monitoring 0 reset.
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RX23W Group 8.5 8. Voltage Detection Circuit (LVDAb) Interrupt and Reset from Voltage Monitoring 1 Table 8.2 shows the procedures for setting bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset. Table 8.3 shows the procedures for stopping bits related to the voltage monitoring 1 interrupt and voltage monitoring 1 reset. Figure 8.4 shows an example of operations for a voltage monitoring 1 interrupt. For the operation of the voltage monitoring 1 reset, see Figure 6.
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RX23W Group 8. Voltage Detection Circuit (LVDAb) VCC Vdet1 Lower limit on VCC voltage (VCCmin) Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 10b (when drop and rise are detected) Voltage monitoring 1 interrupt request Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 00b (when rise is detected). Voltage monitoring 1 interrupt request Set to 0 by a program LVD1DET bit LVD1IDTSEL[1:0] bits are set to 01b (when drop is detected).
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RX23W Group 8.6 8. Voltage Detection Circuit (LVDAb) Event Link Output The LVD can output the event signals to the event link controller (ELC). (1) Vdet1 passage detection event output The LVD outputs the event signal when it is detected that the voltage has passed the Vdet1 voltage while both the voltage detection 1 circuit and the voltage monitoring 1 circuit comparison result output are enabled.
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RX23W Group 9. Clock Generation Circuit 9. Clock Generation Circuit 9.1 Overview This MCU incorporates a clock generation circuit. Table 9.1 lists the specifications of the clock generation circuit. Figure 9.1 and Figure 9.2 show a block diagram of the clock generation circuit. Table 9.1 Specifications of Clock Generation Circuit (1/2) Item Specification Uses • Generates the system clock (ICLK) to be supplied to the CPU, DMAC, DTC, ROM, and RAM.
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RX23W Group Table 9.1 9. Clock Generation Circuit Specifications of Clock Generation Circuit (2/2) Item Specification High-speed on-chip oscillator (HOCO) Oscillation frequency: 32 and 54 MHz Low-speed on-chip oscillator (LOCO) Oscillation frequency: 4 MHz IWDT-dedicated on-chip oscillator Oscillation frequency: 15 kHz Bluetooth-dedicated clock oscillator • Frequency of oscillation: 32 MHz • Connectable resonator: Crystal (The 83-pin LGA package product includes a crystal resonator.
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RX23W Group 9.
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RX23W Group 9.
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RX23W Group 9. Clock Generation Circuit Table 9.2 lists the I/O pins of the clock generation circuit. Table 9.2 I/O Pins of Clock Generation Circuit Pin Name I/O Description XTAL Output EXTAL Input These pins are used to connect a crystal. The EXTAL pin can also be used to input an external clock. For details, refer to section 9.3.2, External Clock Input. XCIN Input XCOUT Output CLKOUT Output Clock output pin XTAL1_RF Input Connect a 32-MHz oscillator.
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RX23W Group 9.2 9. Clock Generation Circuit Register Descriptions 9.2.
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RX23W Group Bit Symbol b31 to b28 FCK[3:0] 9. Clock Generation Circuit Bit Name Description R/W FlashIF Clock (FCLK) Select b31 R/W b28 0 0 0 0: ×1 0 0 0 1: ×1/2 0 0 1 0: ×1/4 0 0 1 1: ×1/8 0 1 0 0: ×1/16 0 1 0 1: ×1/32 0 1 1 0: ×1/64 Settings other than above are prohibited. Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register. Note 1. Do not set the frequency division ratio of ICLK = 1 when a clock of frequency higher than 32 MHz is selected by the SCKCR3.
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RX23W Group 9.2.2 9. Clock Generation Circuit System Clock Control Register 3 (SCKCR3) Address(es): 0008 0026h Value after reset: b15 b14 b13 b12 b11 — — — — — 0 0 0 0 0 b10 b9 b8 CKSEL[2:0] 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 9.2.3 9. Clock Generation Circuit PLL Control Register (PLLCR) Address(es): 0008 0028h Value after reset: b15 b14 — — 0 0 b13 b12 b11 b10 b9 b8 STC[5:0] 0 0 1 1 1 1 b7 b6 b5 b4 b3 b2 b1 — — — — — — PLIDIV[1:0] 0 0 0 0 0 0 0 Bit Symbol Bit Name b1, b0 PLIDIV[1:0] PLL Input Frequency Division Ratio Select b7 to b2 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 9.2.4 9. Clock Generation Circuit PLL Control Register 2 (PLLCR2) Address(es): 0008 002Ah Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — PLLEN 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R/W b0 PLLEN PLL Stop Control 0: PLL is operating. 1: PLL is stopped. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
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RX23W Group 9.2.5 9. Clock Generation Circuit USB-dedicated PLL Control Register (UPLLCR) Address(es): 0008 002Ch Value after reset: b15 b14 — — 0 0 b13 b12 b11 b10 b9 b8 USTC[5:0] 0 0 1 1 1 1 b7 b6 b5 b4 b3 b2 — — — UCKUP LLSEL — — 0 0 0 0 0 0 b1 b0 UPLIDIV[1:0] 0 0 Bit Symbol Bit Name Description R/W b1, b0 UPLIDIV[1:0] USB-dedicated PLL Input Frequency Division Ratio Select b1 b0 R/W b3, b2 — Reserved These bits are read as 0.
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RX23W Group 9.2.6 9. Clock Generation Circuit USB-dedicated PLL Control Register 2 (UPLLCR2) Address(es): 0008 002Eh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — UPLLE N 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R/W b0 UPLLEN USB-dedicated PLL Stop Control 0: USB-dedicated PLL is operating. 1: USB-dedicated PLL is stopped. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note: Set the PRCR.
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RX23W Group 9.2.7 9. Clock Generation Circuit Main Clock Oscillator Control Register (MOSCCR) Address(es): 0008 0032h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — MOSTP 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R/W b0 MOSTP Main Clock Oscillator Stop 0: Main clock oscillator is operating. 1: Main clock oscillator is stopped. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note: Set the PRCR.
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RX23W Group 9.2.8 9. Clock Generation Circuit Sub-Clock Oscillator Control Register (SOSCCR) Address(es): 0008 0033h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — SOSTP 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 SOSTP Sub-Clock Oscillator Stop 0: Sub-clock oscillator is operating. 1: Sub-clock oscillator is stopped. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note: Set the PRCR.
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RX23W Group 9.2.9 9. Clock Generation Circuit Low-Speed On-Chip Oscillator Control Register (LOCOCR) Address(es): 0008 0034h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — LCSTP 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 LCSTP LOCO Stop 0: LOCO is operating. 1: LOCO is stopped. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note: Set the PRCR.PRC0 bit to 1 (write enabled) before rewriting this register.
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RX23W Group 9.2.10 9. Clock Generation Circuit IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR) Address(es): 0008 0035h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — ILCSTP 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R/W b0 ILCSTP IWDT-Dedicated On-Chip Oscillator Stop 0: IWDT-dedicated on-chip oscillator is operating. 1: IWDT-dedicated on-chip oscillator is stopped. R/W b7 to b1 — Reserved These bits are read as 0.
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RX23W Group 9.2.11 9. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register (HOCOCR) Address(es): 0008 0036h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — HCSTP 0 0 0 0 0 0 0 0/1*1 Bit Symbol Bit Name Description R/W b0 HCSTP HOCO Stop 0: HOCO is operating. 1: HOCO is stopped. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note: Set the PRCR.
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RX23W Group 9.2.12 9. Clock Generation Circuit High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) Address(es): 0008 0037h Value after reset: b7 b6 b5 b4 b3 b2 b1 — — — — — — HCFRQ[1:0] 0 0 0 0 0 0 0 b0 0 Bit Symbol Bit Name Description R/W b1, b0 HCFRQ[1:0] HOCO Frequency Setting b1 b0 R/W b7 to b1 — Reserved Note: 0 0: 32 MHz 1 1: 54 MHz Settings other than above are prohibited. These bits are read as 0. The write value should be 0. R/W Set the PRCR.
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RX23W Group 9.2.13 9. Clock Generation Circuit Oscillation Stabilization Flag Register (OSCOVFSR) Address(es): 0008 003Ch Value after reset: b7 b6 b5 b4 — — UPLOV F — 0 0 0 0 b3 b2 HCOVF PLOVF 0/1*1 0 b1 b0 — MOOV F 0 0 Bit Symbol Bit Name Description R/W b0 MOOVF Main Clock Oscillation Stabilization Flag 0: Main clock is stopped 1: Oscillation is stable and the clock can be used as the system clock*2 R b1 — Reserved This bit is read as 0.
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RX23W Group 9. Clock Generation Circuit HCOVF Flag (HOCO Clock Oscillation Stabilization Flag) This flag indicates whether oscillation of the HOCO clock is stable. [Setting condition] • After the HOCOCR.HCSTP bit is set to 0 (HOCO is operating) when the HCSTP bit is 1 (HOCO is stopped), supply of the HOCO clock is started to the MCU internally. [Clearing condition] • After the HOCOCR.HCSTP bit is set to 1, the processing to stop the oscillation of the HOCO is completed.
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RX23W Group 9.2.14 9. Clock Generation Circuit Oscillation Stop Detection Control Register (OSTDCR) Address(es): 0008 0040h b7 b6 b5 b4 b3 b2 b1 b0 OSTDE — — — — — — OSTDI E 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b0 OSTDIE Oscillation Stop Detection Interrupt Enable 0: The oscillation stop detection interrupt is disabled. Oscillation stop detection is not notified to the POE. 1: The oscillation stop detection interrupt is enabled.
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RX23W Group 9.2.15 9. Clock Generation Circuit Oscillation Stop Detection Status Register (OSTDSR) Address(es): 0008 0041h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — OSTDF 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 OSTDF Oscillation Stop Detection Flag 0: The main clock oscillation stop has not been detected. 1: The main clock oscillation stop has been detected. R/(W) *1 b7 to b1 — Reserved These bits are read as 0 and cannot be modified.
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RX23W Group 9.2.16 9. Clock Generation Circuit Main Clock Oscillator Wait Control Register (MOSCWTCR) Address(es): 0008 00A2h Value after reset: b7 b6 b5 — — — 0 0 0 b4 b3 b2 b1 b0 0 0 MSTS[4:0] 0 0 1 Bit Symbol Bit Name Description R/W b4 to b0 MSTS[4:0] Main Clock Oscillator Wait Time b4 R/W b7 to b5 — Reserved Note: b0 0 0 0 0 0: Wait time = 2 cycles (0.
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RX23W Group 9.2.17 9. Clock Generation Circuit CLKOUT Output Control Register (CKOCR) Address(es): 0008 003Eh b15 b14 CKOST P Value after reset: 1 b13 b12 b11 CKODIV[2:0] 0 0 b10 b9 b8 CKOSEL[3:0] 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 9.2.18 9. Clock Generation Circuit Main Clock Oscillator Forced Oscillation Control Register (MOFCR) Address(es): 0008 C293h b7 — Value after reset: b6 b5 b4 b3 b2 b1 b0 — — — — — 0 0 0 0 0 MOSEL MODR V21 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 — Reserved These bits are read as 0. The write value should be 0. R/W b5 MODRV21 Main Clock Oscillator Drive Capability Switch VCC ≥ 2.
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RX23W Group 9.2.19 9. Clock Generation Circuit Memory Wait Cycle Setting Register (MEMWAIT) Address(es): 0008 0031h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — MEMW AIT 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 MEMWAIT Memory Wait Cycle Setting*1 0: No wait states 1: Wait states R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note: Set the PRCR.
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RX23W Group 9. Clock Generation Circuit Start Change to high-speed mode*1 MEMWAIT.MEMWAIT bit = 1 MEMWAIT.MEMWAIT bit = 1? No Yes Change ICLK frequency to higher than 32 MHz End Note 1. Resetting is not necessary in high-speed mode. Figure 9.3 Example of MEMWAIT Bit Setting Procedure When Changing ICLK Frequency to Higher than 32 MHz Start Change ICLK frequency to lower than 32 MHz MEMWAIT.MEMWAIT bit = 0 MEMWAIT.MEMWAIT bit = 0? No Yes Change operating power control state*1 End Note 1.
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RX23W Group 9.2.20 9. Clock Generation Circuit Low-Speed On-Chip Oscillator Trimming Register (LOCOTRR) Address(es): 0008 0060h Value after reset: b7 b6 b5 — — — 0 0 0 b4 b3 b2 b1 b0 LOCOTRD[4:0] *1 *1 *1 *1 *1 Bit Symbol Bit Name Description R/W b4 to b0 LOCOTRD[ 4:0] Low-Speed On-Chip Oscillator Frequency Adjustment b4 R/W b7 to b5 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 9.2.22 9. Clock Generation Circuit High-Speed On-Chip Oscillator Trimming Register n (HOCOTRRn) (n = 0, 3) Address(es): HOCOTRR0 0008 0068h, HOCOTRR3 0008 006Bh Value after reset: b7 b6 — — 0 0 b5 b4 b3 b2 b1 b0 *1 *1 HOCOTRD[5:0] *1 *1 *1 *1 Bit Symbol Bit Name Description R/W b5 to b0 HOCOTRD[ 5:0] High-Speed On-Chip Oscillator Frequency Adjustment b5 R/W b7, b6 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 9.3 9. Clock Generation Circuit Main Clock Oscillator There are two ways of supplying the clock signal from the main clock oscillator: connecting an oscillator or the input of an external clock signal. 9.3.1 Connecting a Crystal Figure 9.5 shows an example of connecting a crystal. A damping resistor (Rd) should be added, if necessary. Since the resistor values vary depending on the resonator and the oscillation drive capability, use values recommended by the resonator manufacturer.
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RX23W Group 9.3.2 9. Clock Generation Circuit External Clock Input Figure 9.7 shows connection of an external clock. If operation is to be driven by an external clock, set the MOFCR.MOSEL bit to 1 and leave the XTAL pin open-circuit. EXTAL XTAL Figure 9.7 9.3.3 External clock input Open Connection Example of External Clock Handling of Pins When the Main Clock is Not Used For details on pin handling when the main clock is not used, refer to section 21.5, Handling of Unused Pins. 9.3.
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RX23W Group 9.4 9. Clock Generation Circuit Sub-Clock Oscillator The only way of supplying the clock signal from the sub-clock oscillator is connecting a crystal. 9.4.1 Connecting 32.768-kHz Crystal To supply a clock to the sub-clock oscillator, connect a 32.768-kHz crystal, as shown in Figure 9.8. A damping resistor Rd should be added, if necessary. Since the resistor values vary depending on the resonator and the oscillation drive capability, use values recommended by the resonator manufacturer.
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RX23W Group 9.4.2 9. Clock Generation Circuit Handling of Pins When Sub-Clock is Not Used If the sub-clock is not in use, connect the XCIN pin to VSS via a resistor (to pull VSS down) and leave the XCOUT pin open-circuit as shown in Figure 9.10. In addition, if an oscillator is not connected, set the sub-clock oscillator stop bit (SOSCCR.SOSTP) to 1 (stopping the oscillator) and the sub-clock oscillator control bit in RTC control register 3 (RCR3.RTCEN) to 0 (stopping the sub-clock oscillator).
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RX23W Group 9.5 9. Clock Generation Circuit Dedicated Clock Oscillator for Bluetooth In the case of the 85-pin BGA and 56-pin QFN products, operating Bluetooth requires connection to the 32-MHz clock oscillator. The 83-pin LGA product does not require the connection of a resonator because the package includes a 32MHz crystal resonator.
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RX23W Group 9. Clock Generation Circuit EXTAL EXTAL Specified from Bluetooth middleware Frequency divider XTAL1_RF 32MHz Dedicated clock oscillator for Bluetooth 1/8 1/16 1/32 XTAL2_RF Frequency divider XTAL1_RF Dedicated clock oscillator for Bluetooth P47/CLKOUT_RF 1/8 1/16 1/32 P47/CLKOUT_RF XTAL2_RF 85-pin BGA, 56-pin QFN Figure 9.12 Specified from Bluetooth middleware 83-pin LGA Example of Connection of the Bluetooth-dedicated clock output pin R01UH0823EJ0110 Rev.1.
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RX23W Group 9.6 9.6.1 9. Clock Generation Circuit Oscillation Stop Detection Function Oscillation Stop Detection and Operation after Detection The oscillation stop detection function is used to detect the main clock oscillator stop and to supply LOCO clock pulses from the low-speed on-chip oscillator as the system clock source instead of the main clock. An oscillation stop detection interrupt request can be generated when an oscillation stop is detected.
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RX23W Group 9. Clock Generation Circuit Start Switch to SCKCR3.CKSEL[2:0] = 000b (LOCO) Setting OSTDCR.OSTDIE = 0 Reading OSTDSR.OSTDF = 1 Yes Setting OSTDSR.OSTDF = 0 OSTDSR.OSTDF = 0 No Try again? Yes Switch to SCKCR3.CKSEL[2:0] = 010b (main clock oscillator) End No Note: On return from the oscillation-stopped state, the factor responsible for stopping the main clock oscillation circuit must be removed on the user system to allow the return of oscillation. Figure 9.13 9.6.
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RX23W Group 9.7 9. Clock Generation Circuit PLL Circuit The PLL circuit has a function to multiply the frequency from the oscillator. 9.8 Internal Clock Clock sources of internal clock signals are the main clock, sub-clock, HOCO clock, LOCO clock, PLL clock, USB-dedicated PLL clock, and dedicated low-speed clock for the IWDT. The internal clocks listed below are produced from these sources.
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RX23W Group 9.8.4 9. Clock Generation Circuit USB Clock The USB clock (UCLK) is an operating clock for the USB module. The UCLK frequency is specified by the SCKCR3.CKSEL[2:0] bits, and the PLLCR.STC[5:0], PLIDIV[1:0] bits, and the UPLLCR.UPLIDIV[1:0] and USTC[5:0] bits. A 48-MHz clock must be supplied to the USB module. When the USB module is used, setting must be made so that UCLK is 48 MHz. 9.8.5 CAN Clock The CAN clock (CANMCLK) is an operating clock for the CAN module.
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RX23W Group 9.9 9.9.1 9. Clock Generation Circuit Usage Notes Notes on Clock Generation Circuit (1) The frequencies of the system clock (ICLK), peripheral module clocks (PCLKA, PCLKB, and PCLKD), and FlashIF clock (FCLK) supplied to each module can be selected by the SCKCR register. Each frequency should meet the following: Select each frequency that is within the operation guaranteed range of clock cycle time (tcyc) specified in AC characteristics of electrical characteristics.
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RX23W Group 9. Clock Generation Circuit Prohibited Signal A Signal B Prohibited MCU CL2 XTAL EXTAL CL1 Figure 9.14 Point for Caution on Board Design for the Oscillation Circuit (Applicable to the Main Clock Oscillator as well as the Sub Clock Oscillator and Bluetooth-Dedicated Osillator) R01UH0823EJ0110 Rev.1.
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RX23W Group 9.9.5 9. Clock Generation Circuit Notes on Resonator Connection Pins When the main clock is not used, the EXTAL and XTAL pins can be used as general ports P36 and P37. When using these pins as general ports, be sure to stop the main clock (MOSCCR.MOSTP = 1). However, do not use the EXTAL and XTAL pins as general ports P36 and P37 in a system that uses the main clock. When the main clock is used, do not set P36 and P37 to output. 9.9.
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RX23W Group 9. Clock Generation Circuit • When using the sub-clock only as the count source of the realtime clock, perform initial settings according to the flowchart example shown in Figure 9.16. After that, perform the clock setting procedure shown in section 28.3.2, Clock and Count Mode Setting Procedure. Start SOSCCR. Sub-clock oscillation state SOSTP 0 Set the SOSCCR.SOSTP bit to 1 (sub-clock oscillator is stopped). Read the SOSCCR.SOSTP bit and confirm that it is 1. RCR3.
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RX23W Group 9. Clock Generation Circuit • When using the sub-clock only as the system clock, perform initial settings according to the flowchart example shown in Figure 9.17. Start SOSCCR. Sub-clock oscillation state SOSTP 0 Set the SOSCCR.SOSTP bit to 1 (sub-clock oscillator is stopped). Read the SOSCCR.SOSTP bit and confirm that it is 1. RCR3. RTCEN Oscillating Undefined Set the RCR3.RTCEN bit to 0 (sub-clock oscillator is stopped). Read the RCR3.RTCEN bit and confirm that it is 0.
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RX23W Group 9. Clock Generation Circuit • When not using the sub-clock, perform initial settings according to the flowchart example in Figure 9.18. Start SOSCCR. Sub-clock oscillation state SOSTP 0 Set the SOSCCR.SOSTP bit to 1 (sub-clock oscillator is stopped). Undefined Read the SOSCCR.SOSTP bit and confirm that it is 1. Set the RCR3.RTCEN bit to 0 (sub-clock oscillator is stopped). RCR3. RTCEN Stopped Read the RCR3.RTCEN bit and confirm that it is 0.*1 1 0 End Note 1.
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RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10. Clock Frequency Accuracy Measurement Circuit (CAC) 10.1 Overview The clock frequency accuracy measurement circuit (CAC) counts pulses of the clock to be measured (measurement target clock) within the time generated by the clock to be used as a measurement reference (measurement reference clock), and determines the accuracy depending on whether the number of pulses is within the allowable range.
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RX23W Group 10.
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RX23W Group 10.2 10. Clock Frequency Accuracy Measurement Circuit (CAC) Register Descriptions 10.2.1 CAC Control Register 0 (CACR0) Address(es): 0008 B000h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — CFME 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 CFME Clock Frequency Measurement Enable 0: Clock frequency measurement is disabled. 1: Clock frequency measurement is enabled. R/W b7 to b1 — Reserved These bits are read as 0.
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RX23W Group 10.2.2 10. Clock Frequency Accuracy Measurement Circuit (CAC) CAC Control Register 1 (CACR1) Address(es): 0008 B001h b7 b6 EDGES[1:0] Value after reset: 0 0 b5 b4 b3 TCSS[1:0] 0 0 b2 b1 b0 CACRE FE FMCS[2:0] 0 0 0 0 Bit Symbol Bit Name Description R/W b0 CACREFE CACREF Pin Input Enable 0: CACREF pin input is disabled. 1: CACREF pin input is enabled.
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RX23W Group 10.2.3 10.
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RX23W Group 10.2.4 10. Clock Frequency Accuracy Measurement Circuit (CAC) CAC Interrupt Request Enable Register (CAICR) Address(es): 0008 B003h b7 — Value after reset: b6 b5 b4 OVFFC MENDF FERRF L CL CL 0 0 0 0 b3 — 0 b2 b1 b0 OVFIE MENDI FERRI E E 0 0 0 Bit Symbol Bit Name Description R/W b0 FERRIE Frequency Error Interrupt Request Enable 0: Frequency error interrupt request is disabled. 1: Frequency error interrupt request is enabled.
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RX23W Group 10.2.5 10. Clock Frequency Accuracy Measurement Circuit (CAC) CAC Status Register (CASTR) Address(es): 0008 B004h Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 OVFF MENDF FERRF 0 0 0 Bit Symbol Bit Name Description R/W b0 FERRF Frequency Error Flag 0: The clock frequency is within the range corresponding to the settings. 1: The clock frequency has deviated beyond the range corresponding to the settings (frequency error).
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RX23W Group 10.2.6 10. Clock Frequency Accuracy Measurement Circuit (CAC) CAC Upper-Limit Value Setting Register (CAULVR) Address(es): 0008 B006h Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAULVR is a 16-bit readable/writable register that specifies the upper-limit value of the counter used for measuring the frequency.
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RX23W Group 10.3 10. Clock Frequency Accuracy Measurement Circuit (CAC) Operation 10.3.1 Measuring Clock Frequency The clock frequency accuracy measurement circuit measures the clock frequency using the CACREF pin input or the internal clock as a reference. Figure 10.2 shows an operating example of the clock frequency accuracy measurement circuit. The clock frequency accuracy measurement circuit operates as shown below when measuring the clock frequency.
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RX23W Group 10. Clock Frequency Accuracy Measurement Circuit (CAC) clock frequency is erroneous. If the FERRIE bit in CAICR is 1, a frequency error interrupt is generated. Also, the MENDF flag in CASTR is set to 1. If the MENDIE bit in CAICR is 1, a measurement end interrupt is generated. (5) When the next valid edge is input, the counter value is transferred in CACNTBR and compared with the values of CAULVR and CALLVR.
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RX23W Group 10.5 10.5.1 10. Clock Frequency Accuracy Measurement Circuit (CAC) Usage Notes Module Stop Function Setting CAC operation can be disabled or enabled using module stop control register C (MSTPCRC). The initial setting is for the CAC to be halted. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption. R01UH0823EJ0110 Rev.1.
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RX23W Group 11. Low Power Consumption 11. Low Power Consumption 11.1 Overview This MCU has several functions for reducing power consumption, by setting clock dividers, stopping modules, changing to low power consumption mode in normal operation, and changing to operating power control mode. Table 11.1 lists the specifications of low power consumption functions, and Table 11.
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RX23W Group Table 11.2 11.
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RX23W Group 11. Low Power Consumption Reset state *3 Normal operation mode (Program execution state) *4 1 WAIT instruction* SSBY = 0 WAIT instruction*1 SSBY = 0 All interrupts MSTPCRA.MSTPA28 = 1 MSTPCRC.DSLPE = 1 Sleep mode All interrupts Deep sleep mode WAIT instruction*1 SSBY = 1 Interrupt*2 Software standby mode Low power consumption mode (Program stopped state) : A transition is made by setting registers. : A transition is made by executing exception handling. Note 1.
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RX23W Group 11. Low Power Consumption Reset state Software standby mode Deep sleep mode Software standby mode Deep sleep mode Exit the reset state High-speed operating mode Sleep mode Set the OPCCR register Middle-speed operating mode Set the SOPCCR register Set the SOPCCR register *1 Sleep mode Deep sleep mode Low-speed operating mode Low-speed operating mode Software standby mode Software standby mode Sleep mode *1 Sleep mode Deep sleep mode : WAIT instruction : Interrupt Note 1.
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RX23W Group 11.2 11. Low Power Consumption Register Descriptions 11.2.1 Standby Control Register (SBYCR) Address(es): 0008 000Ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 SSBY — — — — — — — — — — — — — — — 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b14 to b0 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 11.2.2 11.
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RX23W Group 11.2.3 11.
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RX23W Group Bit Symbol 11. Low Power Consumption Bit Name Description R/W b29 to b27 — Reserved These bits are read as 1. The write value should be 1. R/W b30 MSTPB30 Serial Communication Interface 1 Module Stop Target module: SCI1 0: This module clock is enabled 1: This module clock is disabled R/W b31 — Reserved This bit is read as 1. The write value should be 1. R/W Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register. Note 1.
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RX23W Group 11.2.4 11.
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RX23W Group 11.2.5 11.
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RX23W Group 11.2.6 11. Low Power Consumption Operating Power Control Register (OPCCR) Address(es): 0008 00A0h Value after reset: b7 b6 b5 b4 b3 — — — OPCM TSF — 0 0 0 0 0 b2 b1 b0 OPCM[2:0] 0 1 0 Bit Symbol Bit Name Description R/W b2 to b0 OPCM[2:0] Operating Power Control Mode Select b2 R/W b3 — Reserved This bit is read as 0. The write value should be 0.
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RX23W Group 11.2.7 11. Low Power Consumption Sub Operating Power Control Register (SOPCCR) Address(es): 0008 00AAh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — SOPC MTSF — — — SOPC M 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 SOPCM Sub Operating Power Control Mode Select 0: High-speed operating mode or middle-speed operating mode*1 1: Low-speed operating mode R/W b3 to b1 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 11. Low Power Consumption SOPCMTSF Flag (Sub Operating Power Control Mode Transition Status Flag) The SOPCMTSF flag indicates the switching control state when the sub operating power control mode is switched. This flag becomes 1 when the value of the SOPCM bit is rewritten, and 0 when mode transition is completed. Read this flag and confirm that it is 0 before proceeding to the next processing. Only rewrite the SOPCM bit when this flag is 0. Table 11.
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RX23W Group 11. Low Power Consumption • High-Speed Operating Mode The maximum operating frequency during FLASH read is 54 MHz for ICLK, PCLKA, and PCLKD; 32 MHz for PCLKB, and FCLK. The operating voltage range is 1.8 to 3.6 V during FLASH read. However, the maximum operating frequency during FLASH read is 16 MHz for ICLK, FCLK, PCLKA, and PCLKB, and 32 MHz for PCLKD when the operating voltage is 2.4 V or larger and smaller than 2.7 V.
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RX23W Group 11. Low Power Consumption • Middle-Speed Operating Mode As compared to high-speed operating mode, this mode reduces power consumption for low-speed operation. The maximum operating frequency during FLASH read is 12 MHz for ICLK, FCLK, PCLKA, PCLKB, and PCLKD. The operating voltage range is 1.8 to 3.6 V during FLASH read. The maximum operating frequency during FLASH read is 8 MHz for all the clocks when the operating voltage is 1.8 V or larger and smaller than 2.4 V.
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RX23W Group 11. Low Power Consumption • Low-Speed Operating Mode A transition to low-speed operating mode is set by writing 1 to the SOPCM bit in the SOPCCR register. The setting of the OPCM[2:0] bits cannot be modified during low-speed operating mode. This mode is used only for the sub oscillator of 32.768 kHz. During reading the flash memory (FLASH), the maximum operating frequency of ICLK, FCLK, PCLKA, PCLKB, and PCLKD is 32.768 kHz. The operating voltage is in the range of 1.8 to 3.6 V.
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RX23W Group 11.2.8 11. Low Power Consumption Sleep Mode Return Clock Source Switching Register (RSTCKCR) Address(es): 0008 00A1h b7 b6 b5 b4 b3 RSTCK EN — — — — 0 0 0 0 0 Value after reset: b2 b1 b0 RSTCKSEL[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 RSTCKSEL [2:0] Sleep Mode Return Clock Source Select b2 R/W b6 to b3 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 11. Low Power Consumption RSTCKEN Bit (Sleep Mode Return Clock Source Switching Enable) The RSTCKEN bit enables or disables clock source switching when sleep mode is exited. The clock source can be switched when exiting sleep mode only while the sub-clock oscillator is selected as the clock for entering sleep mode. Do not enable this bit when entering sleep mode while the HOCO, LOCO, main clock oscillator, or PLL is selected as the clock source.
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RX23W Group 11.3 11. Low Power Consumption Reducing Power Consumption by Switching Clock Signals The clock frequency can change by setting the SCKCR.FCK[3:0], ICK[3:0], PCKA[3:0], PCKB[3:0], and PCKD[3:0] bits. The CPU, DMAC, DTC, ROM, and RAM clocks can be set by the ICK[3:0] bits. The peripheral module clocks can be set by the PCKA[3:0], PCKB[3:0], and PCKD[3:0] bits. The flash memory clock can be set by the FCK[3:0] bits. For details, refer to section 9, Clock Generation Circuit. 11.
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RX23W Group 11. Low Power Consumption • Example 2: From high-speed/middle-speed operating mode to low-speed operating mode (High-speed operation in high-speed operating mode/middle-speed operation in middle-speed operating mode) ↓ Set the frequency of each clock to lower than the maximum operating frequency for low-speed operating mode ↓ Confirm that all clock sources but the sub-clock oscillator are stopped ↓ Confirm that the SOPCCR.SOPCMTSF flag is 0 (transition completed) ↓ Set the SOPCCR.
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RX23W Group 11.6 11. Low Power Consumption Low Power Consumption Modes 11.6.1 11.6.1.1 Sleep Mode Entry to Sleep Mode When the WAIT instruction is executed while the SBYCR.SSBY bit is 0, the CPU enters sleep mode. In sleep mode, the CPU stops operating but the contents of its internal registers are retained. Other peripheral functions do not stop. When the WDT is used, the WDT stops counting when sleep mode is entered.
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RX23W Group 11.6.1.2 11. Low Power Consumption Exit from Sleep Mode Exit from sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow. • Initiated by an interrupt An interrupt initiates exit from sleep mode and the interrupt exception handling starts. If a maskable interrupt has been masked by the CPU (the priority level*1 of the interrupt has been set to a value lower than that of the PSW.
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RX23W Group 11.6.2 11.6.2.1 11. Low Power Consumption Deep Sleep Mode Entry to Deep Sleep Mode When a WAIT instruction is executed with the MSTPCRC.DSLPE bit set to 1, the MSTPCRA.MSTPA28 bit set to 1, and the SBYCR.SSBY bit cleared to 0, a transition to deep sleep mode is made. In deep sleep mode, the CPU and the DMAC, DTC, ROM, and RAM clocks stop. Peripheral functions do not stop. When the WDT is used, the WDT stops counting when deep sleep mode is entered.
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RX23W Group 11.6.2.2 11. Low Power Consumption Exit from Deep Sleep Mode Exit from deep sleep mode is initiated by any interrupt, a RES# pin reset, a power-on reset, a voltage monitoring reset, or a reset caused by an IWDT underflow. • Initiated by an interrupt An interrupt initiates exit from deep sleep mode and the interrupt exception handling starts. If a maskable interrupt has been masked by the CPU (the priority level*1 of the interrupt has been set to a value lower than that of the PSW.
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RX23W Group 11.6.3 11.6.3.1 11. Low Power Consumption Software Standby Mode Entry to Software Standby Mode When a WAIT instruction is executed with the SBYCR.SSBY bit set to 1, a transition to software standby mode is made. In this mode, the CPU, on-chip peripheral functions, and all the other functions except the sub-clock oscillator stop. However, the contents of the CPU internal registers, RAM data, the states of on-chip peripheral functions, the I/O ports, and the sub-clock oscillator are retained.
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RX23W Group 11.6.3.2 11. Low Power Consumption Exit from Software Standby Mode Exit from software standby mode is initiated by an external pin interrupt (the NMI, IRQ0, IRQ1, IRQ4 to IRQ7), peripheral function interrupts (the RTC alarm, RTC interval, IWDT, voltage monitoring, VBATT pin voltage drop detection, USB, and ELC (LPT-dedicated interrupt)), a RES# pin reset, a power-on reset, a voltage monitoring reset, or an independent watchdog timer reset.
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RX23W Group 11.6.3.3 11. Low Power Consumption Example of Software Standby Mode Application Figure 11.6 shows an example of entry to software standby mode by the falling edge of the IRQn pin, and exit from software standby mode by the rising edge of the IRQn pin. In this example, an IRQn interrupt is accepted with the IRQCRi.IRQMD[1:0] bits of the ICU set to 01b (falling edge), and then the IRQCRi.IRQMD[1:0] bits are set to 10b (rising edge). After that, the SBYCR.
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RX23W Group 11.7 11.7.1 11. Low Power Consumption Usage Notes I/O Port States I/O port states are retained in software standby mode. Therefore, the supply current is not reduced if output signals are high level. 11.7.2 Module Stop State of DMAC and DTC Before setting the MSTPCRA.MSTPA28 bit to 1, set the DMAST.DMST bit of the DMAC and the DTCST.DTCST bit of the DTC to 0 to avoid activating the DMAC and DTC.
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RX23W Group 12. Battery Backup Function 12. Battery Backup Function 12.1 Overview When the voltage at the VCC pin is dropped, power can be supplied to the realtime clock (RTC) and the sub-clock oscillator placed in the battery backup power area from the battery backup power pin (VBATT pin). When the battery backup function is not used, connect the VBATT pin to the VCC pin and disable the battery backup function (set the VBATTCR.VBATTDIS bit to 1).
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RX23W Group 12.2 12. Battery Backup Function Register Descriptions 12.2.1 VBATT Control Register (VBATTCR) Address(es): 0008 C29Dh b7 b6 VBTLVDLVL[1:0] Value after reset: 0 0 b5 b4 b3 b2 b1 b0 — VBTLV DEN — — — VBATT DIS 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 VBATTDIS Battery Backup Function Disable 0: Battery backup function enabled 1: Battery backup function disabled R/W b3 to b1 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 12.2.2 12. Battery Backup Function VBATT Status Register (VBATTSR) Address(es): 0008 C29Eh b7 Value after reset: b6 b5 b4 b3 b2 — — — — — — 0 0 0 0 0 0 b1 b0 VBTLV VBATRL DMON VDETF 1 X x: Undefined Bit Symbol Bit Name b0 VBATRLVDETF Battery Backup Power 0: Battery backup power voltage drop (< 1.8 V) not detected Voltage Drop Detection Flag 1: Battery backup power voltage drop (< 1.
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RX23W Group 12.2.3 12.
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RX23W Group 12.3 12. Battery Backup Function Operation 12.3.1 Battery Backup Function When the voltage at the VCC pin is dropped, power can be supplied to the RTC and sub-clock oscillator from the VBATT pin. When the power supply reduction from the VCC pin is detected, connection to power is switched to the power supply from the VBATT pin. The power supply from the VCC pin is resumed when the voltage at the VCC pin exceeds VDETBATT while the RTC is operating on the power supply from the VBATT pin.
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RX23W Group 12. Battery Backup Function VCC pin voltage VCC VDETBATT VBATT pin voltage VBATT pin voltage drop detected VBATT VBATT pin voltage rise detected VBATT operating range Vdetvbt VBATT pin voltage monitor flag 1 0 VBATT pin voltage ≥ Vdetvbt Figure 12.
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RX23W Group 12.4 12. Battery Backup Function Usage Notes 1. When the VBATT pin is not used, connect the VBATT pin to the VCC pin. 2. When the battery backup function is not used, set the VBATTCR.VBATTDIS bit to 1 (battery backup function disabled). 3. When the voltage level at the VBATT is lower than the guaranteed operation range, operation of the sub-clock and RTC cannot be guaranteed. The RTC must be initialized to restart power supply after the VBATT pin falls below the operation guaranteed voltage.
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RX23W Group 13. 13. Register Write Protection Function Register Write Protection Function The register write protection function protects important registers from being overwritten for in case a program runs out of control. The registers to be protected are set with the protect register (PRCR). Table 13.1 lists the association between the PRCR bits and the registers to be protected. Table 13.
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RX23W Group 13.1 13. Register Write Protection Function Register Descriptions 13.1.1 Protect Register (PRCR) Address(es): 0008 03FEh b15 b14 b13 b12 b11 b10 b9 b8 PRKEY[7:0] Value after reset: 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — — — PRC3 PRC2 PRC1 PRC0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 PRC0 Protect Bit 0 Enables writing to the registers related to the clock generation circuit.
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RX23W Group 14. Exception Handling 14. Exception Handling 14.1 Exception Events During execution of a program by the CPU, the occurrence of a certain event may cause execution of that program to be suspended and execution of another program to be started. Such kinds of events are called exception events. The RXv2 CPU supports eight types of exceptions. The types of exception events are shown in Figure 14.1. The occurrence of an exception causes the processor mode to shift to supervisor mode.
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RX23W Group 14.1.1 14. Exception Handling Undefined Instruction Exception An undefined instruction exception occurs when execution of an undefined instruction (an instruction not implemented) is detected. 14.1.2 Privileged Instruction Exception A privileged instruction exception occurs when execution of a privileged instruction is detected in user mode. Privileged instructions can be executed only in supervisor mode. 14.1.
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RX23W Group 14.2 14. Exception Handling Exception Handling Procedure In the exception handling, part of the processing is handled automatically by hardware and part of it is handled by a program (exception handling routine) that has been written by the user. Figure 14.2 shows the processing procedure when an exception other than a reset is accepted.
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RX23W Group 14. Exception Handling When an exception is accepted, hardware processing by the RXv2 CPU is followed by access to the vector to acquire the address of the branch destination. In the vector, a vector address is allocated to each exception, and the branch destination address of the exception handling routine is written to each vector address. Hardware pre-processing by the RXv2 CPU handles saving of the contents of the program counter (PC) and processor status word (PSW).
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RX23W Group 14.3 14. Exception Handling Acceptance of Exception Events When an exception occurs, the CPU suspends the execution of the program and processing branches to the exception handling routine. 14.3.1 Acceptance Timing and Saved PC Value Table 14.1 lists the timing of acceptance and the program counter (PC) value to be saved for each exception event. Table 14.
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RX23W Group 14.3.2 14. Exception Handling Vector and Site for Saving the Values in the PC and PSW The vector for each type of exception and the site for saving the values of the program counter (PC) and processor status word (PSW) are listed in Table 14.2. The addresses where the exception vector table and interrupt vector table start must be set. For details, see section 2.6, Vector Table. Table 14.
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RX23W Group 14.4 14. Exception Handling Hardware Processing for Accepting and Returning from Exceptions This section describes the hardware processing for accepting and returning from exceptions other than a reset. (1) Hardware Pre-Processing for Accepting an Exception (a) Saving PSW • For a fast interrupt PSW → BPSW • For exceptions other than a fast interrupt PSW → Stack Note: (b) The values in FPSW are not saved by hardware pre-processing.
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RX23W Group 14.5 14. Exception Handling Hardware Pre-Processing The hardware pre-processing from reception of each exception request to execution of the associated exception handling routine are explained below. 14.5.1 Undefined Instruction Exception 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2. The processor mode select bit (PM), the stack pointer select bit (U), and the interrupt enable bit (I) in PSW are cleared to 0. 3.
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RX23W Group 14.5.6 14. Exception Handling Non-Maskable Interrupt 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2. The processor mode select bit (PM), the stack pointer select bit (U), and the interrupt enable bit (I) in PSW are cleared to 0. 3. If the interrupt was generated during the execution of an RMPA, SCMPU, SMOVB, SMOVF, SMOVU, SSTR, SUNTIL, or SWHILE instruction, the value of the program counter (PC) for that instruction is saved on the stack (ISP).
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RX23W Group 14.6 14. Exception Handling Return from Exception Handling Routine Executing the instruction listed in Table 14.3 at the end of the corresponding exception handling routine restores the values of the program counter (PC) and processor status word (PSW) that were saved on the stack or in the control registers (BPC and BPSW) immediately before the exception handling sequence. Table 14.
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RX23W Group 15. Interrupt Controller (ICUb) 15. Interrupt Controller (ICUb) 15.1 Overview The interrupt controller receives interrupt requests from peripheral modules and external pins, and generates an interrupt request to the CPU and a transfer request to the DTC and DMAC. Table 15.1 lists the specifications of the interrupt controller, and Figure 15.1 shows a block diagram of the interrupt controller. Table 15.
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RX23W Group 15.
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RX23W Group 15.2 15. Interrupt Controller (ICUb) Register Descriptions 15.2.1 Interrupt Request Register n (IRn) (n = interrupt vector number) Address(es): ICU.IR016 0008 7010h to ICU.
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RX23W Group 15.2.2 15. Interrupt Controller (ICUb) Interrupt Request Enable Register m (IERm) (m = 02h to 1Fh) Address(es): ICU.IER02 0008 7202h to ICU.
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RX23W Group 15.2.3 15. Interrupt Controller (ICUb) Interrupt Source Priority Register n (IPRn) (n = interrupt vector number) Address(es): ICU.IPR000 0008 7300h to ICU.IPR255 0008 73FFh Value after reset: b7 b6 b5 b4 — — — — 0 0 0 0 b3 b2 b1 b0 IPR[3:0] 0 0 0 0 Bit Symbol Bit Name Description R/W b3 to b0 IPR[3:0] Interrupt Priority Level Select b3 R/W b7 to b4 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 15.2.4 15. Interrupt Controller (ICUb) Fast Interrupt Set Register (FIR) Address(es): ICU.FIR 0008 72F0h Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 FIEN — — — — — — — 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 FVCT[7:0] 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 FVCT[7:0] Fast Interrupt Vector Number Specify the vector number of an interrupt source to be a fast interrupt.
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RX23W Group 15.2.5 15. Interrupt Controller (ICUb) Software Interrupt Generation Register (SWINTR) Address(es): ICU.SWINTR 0008 72E0h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — SWINT 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 SWINT Software Interrupt Generation This bit is read as 0. Writing 1 issues a software interrupt request. Writing 0 to this bit has no effect. R/(W) *1 b7 to b1 — Reserved These bits are read as 0.
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RX23W Group 15.2.6 15. Interrupt Controller (ICUb) DTC Transfer Request Enable Register n (DTCERn) (n = interrupt vector number) Address(es): ICU.DTCER027 0008 711Bh to ICU.DTCER255 0008 71FFh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — DTCE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 DTCE DTC Transfer Request Enable 0: The corresponding interrupt source is not selected as the DTC R/W trigger.
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RX23W Group 15.2.7 15. Interrupt Controller (ICUb) DMAC Trigger Select Register m (DMRSRm) (m = DMAC channel number) Address(es): ICU.DMRSR0 0008 7400h, ICU.DMRSR1 0008 7404h, ICU.DMRSR2 0008 7408h, ICU.DMRSR3 0008 740Ch b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 DMRS[7:0] Value after reset: 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 DMRS[7:0] DMAC Trigger Select These bits specify the vector number for the DMA transfer request.
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RX23W Group 15.2.8 15. Interrupt Controller (ICUb) IRQ Control Register i (IRQCRi) (i = 0, 1, and 4 to 7) Address(es): ICU.IRQCR0 0008 7500h, ICU.IRQCR1 0008 7501h, ICU.IRQCR4 0008 7504h to ICU.IRQCR7 0008 7507h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — IRQMD[1:0] — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b1, b0 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 15.2.9 15. Interrupt Controller (ICUb) IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) Address(es): ICU.IRQFLTE0 0008 7510h b7 b6 b5 b4 FLTEN FLTEN FLTEN FLTEN 7 6 5 4 Value after reset: 0 0 0 0 b3 b2 — — 0 0 b1 b0 FLTEN FLTEN 1 0 0 0 Bit Symbol Bit Name Description R/W b0 FLTEN0 IRQ0 Digital Filter Enable 0: Digital filter is disabled 1: Digital filter is enabled R/W b1 FLTEN1 IRQ1 Digital Filter Enable b3, b2 — Reserved These bits are read as 0.
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RX23W Group 15.2.10 15. Interrupt Controller (ICUb) IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) Address(es): ICU.
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RX23W Group 15.2.11 15. Interrupt Controller (ICUb) Non-Maskable Interrupt Status Register (NMISR) Address(es): ICU.
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RX23W Group 15. Interrupt Controller (ICUb) WDTST Flag (WDT Underflow/Refresh Error Status Flag) This flag indicates the WDT underflow/refresh error interrupt request. The WDTST flag is read-only, and cleared by the NMICLR.WDTCLR bit. [Setting condition] • When the WDT underflow/refresh error interrupt is generated [Clearing condition] • When 1 is written to the NMICLR.WDTCLR bit IWDTST Flag (IWDT Underflow/Refresh Error Status Flag) This flag indicates the IWDT underflow/refresh error interrupt request.
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RX23W Group 15.2.12 15. Interrupt Controller (ICUb) Non-Maskable Interrupt Enable Register (NMIER) Address(es): ICU.
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RX23W Group 15. Interrupt Controller (ICUb) VBATEN Bit (VBATT Voltage Monitoring Interrupt Enable) This bit enables the VBATT voltage monitoring interrupt. A 1 can be written to this bit only once, and subsequent write accesses are no longer enabled. Writing 0 to this bit is disabled. R01UH0823EJ0110 Rev.1.
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RX23W Group 15.2.13 15. Interrupt Controller (ICUb) Non-Maskable Interrupt Status Clear Register (NMICLR) Address(es): ICU.NMICLR 0008 7582h Value after reset: b7 b6 b5 — VBATC LR — 0 0 0 b4 b3 b2 b1 b0 LVD1C IWDTC WDTCL OSTCL NMICL LR LR R R R 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 NMICLR NMI Clear This bit is read as 0. Writing 1 to this bit clears the NMISR.NMIST flag. Writing 0 to this bit has no effect. R/(W) *1 b1 OSTCLR OST Clear This bit is read as 0.
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RX23W Group 15.2.14 15. Interrupt Controller (ICUb) NMI Pin Interrupt Control Register (NMICR) Address(es): ICU.NMICR 0008 7583h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — NMIMD — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 — Reserved These bits are read as 0. The write value should be 0. R/W b3 NMIMD NMI Detection Set 0: Falling edge 1: Rising edge R/W b7 to b4 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 15.2.16 15. Interrupt Controller (ICUb) NMI Pin Digital Filter Setting Register (NMIFLTC) Address(es): ICU.NMIFLTC 0008 7594h Value after reset: b7 b6 b5 b4 b3 b2 — — — — — — 0 0 0 0 0 0 b1 b0 NFCLKSEL[1:0] 0 0 Bit Symbol Bit Name Description R/W b1, b0 NFCLKSEL[1:0] NMI Digital Filter Sampling Clock b1 b0 R/W b7 to b2 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 15.3 15. Interrupt Controller (ICUb) Vector Table There are two types of interrupts detected by the interrupt controller: maskable interrupts and non-maskable interrupts. When the CPU accepts an interrupt or non-maskable interrupt, it acquires a 4-byte vector address from the vector table. 15.3.1 Interrupt Vector Table The interrupt vector table is placed in the 1024-byte range (4 bytes × 256 sources) beginning at the address specified in the interrupt table register (INTB) of the CPU.
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RX23W Group Name Vector No.*1 Vector Address Offset Form of Interrupt Detection DTC DMAC sstb Return Interrupt Vector Table (1/6) CPU Table 15.3 15.
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RX23W Group Name Vector No.*1 Vector Address Offset Form of Interrupt Detection DTC DMAC sstb Return Interrupt Vector Table (2/6) CPU Table 15.3 15. Interrupt Controller (ICUb) IER IPR DTCER SPEI0 44 00B0h Level  N/A N/A N/A IER05.IEN4 IPR044 — SPRI0 45 00B4h Edge    N/A IER05.IEN5 DTCER045 SPTI0 46 00B8h Edge    N/A IER05.IEN6 DTCER046 SPII0 47 00BCh Level  N/A N/A N/A IER05.
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RX23W Group Form of Interrupt Detection sstb Return RTC Name Vector Address Offset DMAC VBATT Vector No.*1 DTC Source of Interrupt Request Generation Interrupt Vector Table (3/6) CPU Table 15.3 15. Interrupt Controller (ICUb) IER IPR DTCER VBTLVDI 91 016Ch Edge  N/A N/A  IER0B.IEN3 IPR091 — ALM 92 0170h Edge  N/A N/A  IER0B.IEN4 IPR092 —  N/A N/A  IER0B.
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RX23W Group Name Vector Address Offset Form of Interrupt Detection DMAC sstb Return MTU4 Vector No.*1 DTC Source of Interrupt Request Generation Interrupt Vector Table (4/6) CPU Table 15.3 15. Interrupt Controller (ICUb) IER IPR DTCER TGIA4 134 0218h Edge    N/A IER10.IEN6 IPR134 DTCER134 TGIB4 135 021Ch Edge   N/A N/A IER10.IEN7 DTCER135 TGIC4 136 0220h Edge   N/A N/A IER11.IEN0 DTCER136 TGID4 137 0224h Edge   N/A N/A IER11.
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RX23W Group TMR3 Name Vector Address Offset Form of Interrupt Detection DMAC sstb Return TMR2 Vector No.*1 DTC Source of Interrupt Request Generation Interrupt Vector Table (5/6) CPU Table 15.3 15. Interrupt Controller (ICUb) IER IPR DTCER CMIA2 180 02D0h Edge   N/A N/A IER16.IEN4 IPR180 DTCER180 CMIB2 181 02D4h Edge   N/A N/A IER16.IEN5 OVI2 182 02D8h Edge  N/A N/A N/A IER16.IEN6 CMIA3 183 02DCh Edge   N/A N/A IER16.
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RX23W Group SCI8 Name Vector Address Offset Form of Interrupt Detection DMAC sstb Return BLE Vector No.*1 DTC Source of Interrupt Request Generation Interrupt Vector Table (6/6) CPU Table 15.3 15. Interrupt Controller (ICUb) IER IPR DTCER ERI 226 0388h Level  N/A N/A N/A IER1C.IEN2 IPR226 — RXI 227 038Ch Edge    N/A IER1C.IEN3 DTCER227 TXI 228 0390h Edge    N/A IER1C.IEN4 DTCER228 TEI 229 0394h Level  N/A N/A N/A IER1C.
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RX23W Group 15.4 15. Interrupt Controller (ICUb) Interrupt Operation The interrupt controller performs the following processing. • Detecting interrupts • Enabling and disabling interrupts • Selecting interrupt request destinations (CPU interrupt, DTC trigger, or DMAC trigger) • Determining priority 15.4.1 Detecting Interrupts Interrupt requests are detected in either of two ways: the detection of edges of the interrupt signal or the detection of a level of the interrupt signal.
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RX23W Group 15. Interrupt Controller (ICUb) Figure 15.3 to Figure 15.6 show the interrupt signals of the interrupt controller. Note that the timings of the interrupts with interrupt vector numbers 64 to 95 are different from those of other interrupts. For the IRQ pin interrupts with interrupt vector numbers 64 to 79, “internal delay + 2 PCLK cycles” of delay is added after the IRQ pin input. For the interrupts with interrupt vector numbers 80 to 95, “2 PCLK cycles” of delay is added.
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RX23W Group 15.4.1.2 15. Interrupt Controller (ICUb) Operation of Status Flags for Level-Detected Interrupts Figure 15.6 shows the operation of the interrupt status flag (IR flag) in IRn (n = interrupt vector number) in the case of level detection of an interrupt from a peripheral module or an external pin. The IR flag in IRn remains set to 1 as long as the interrupt signal is asserted. To clear the IRn.IR flag to 0, clear the interrupt request in the source generating the interrupt.
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RX23W Group 15.4.2 15. Interrupt Controller (ICUb) Enabling and Disabling Interrupt Sources Enabling requests from a given interrupt source requires the following settings. 1. In the case of interrupt requests from peripheral modules, setting the interrupt enable bit for the peripheral module to permit the output of interrupt requests from the source 2. Enabling of the interrupt by the IERm.
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RX23W Group 15.4.3 15. Interrupt Controller (ICUb) Selecting Interrupt Request Destinations Possible settings for the request destination of each interrupt are fixed. That is, settings for request destination other than those indicated in Table 15.3, Interrupt Vector Table, are not possible. Do not make an interrupt request destination setting that is not indicated by a “” in Table 15.3.
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RX23W Group (3) 15. Interrupt Controller (ICUb) CPU Interrupt Request If the interrupt request destination is neither the DMAC nor the DTC, the interrupt request is sent to the CPU. Set the IERm.IENj bit (m = 02h to 1Fh, j = 0 to 7) to 1 while neither the DMAC trigger settings nor the DTC trigger settings described above are in place. Table 15.4 shows operation when the DMAC or DTC is the request destination. Table 15.
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RX23W Group 15.4.4 15. Interrupt Controller (ICUb) Determining Priority Interrupt priority is determined for each interrupt request destination. The priority for each interrupt request destination is determined as follows. (1) Determining Priority when the CPU is the Request Destination of the Interrupt A source selected for the fast interrupt has the highest priority. After that, an interrupt source with a larger value of the interrupt priority level select bits (IPR[3:0]) in IPRn takes priority.
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RX23W Group 15.4.7 15. Interrupt Controller (ICUb) Digital Filter The digital filter function is provided for the external interrupt request IRQi pins (i = 0, 1, and 4 to 7) and NMI pin interrupt. The digital filter samples input signals at the filter sampling clock (PCLK) and removes the pulses of which length is less than three sampling cycles. To use the digital filter for the IRQi pin, set the sampling clock cycle (PCLK, PCLK/8, PCLK/32, or PCLK/64) with the IRQFLTC0.
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RX23W Group 15.5 15. Interrupt Controller (ICUb) Non-maskable Interrupt Operation There are six types of non-maskable interrupt: the NMI pin interrupt, oscillation stop detection interrupt, WDT underflow/refresh error, IWDT underflow/refresh error, voltage monitoring 1 interrupt, and VBATT voltage monitoring interrupt. Non-maskable interrupts are only usable as interrupts for the CPU; that is, they are not capable of DTC or DMAC trigger.
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RX23W Group 15.6 15. Interrupt Controller (ICUb) Return from Power-Down States The interrupt sources that can be used to return operation from sleep mode, deep sleep mode, or software standby mode are listed in Table 15.3, Interrupt Vector Table. For details, refer to section 11, Low Power Consumption. The following describes how to use an interrupt to return operation from each low power consumption mode. 15.6.
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RX23W Group 15.7 15.7.1 15. Interrupt Controller (ICUb) Usage Note Note on WAIT Instruction Used with Non-Maskable Interrupt Before executing the WAIT instruction, check to see that all the status flags in NMISR are 0. R01UH0823EJ0110 Rev.1.
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RX23W Group 16. Buses 16. Buses 16.1 Overview Table 16.1 lists the bus specifications, Figure 16.1 shows the bus configuration, and Table 16.2 lists the addresses assigned for each bus. Table 16.
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RX23W Group 16.
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RX23W Group 16.2 16.2.1 16. Buses Description of Buses CPU Buses The CPU buses consist of the instruction and operand buses, which are connected to internal main bus 1. As the names suggest, the instruction bus is used to fetch instructions for the CPU, while the operand bus is used for operand access. The instruction bus is 64 bits while the operand bus is 32 bits. Connection of the instruction and operand buses to RAM and ROM provides the CPU with direct access to these areas, i.e.
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RX23W Group Table 16.3 Priority High 16. Buses Order of Priority for Bus Masters Internal main buses Bus Master 2 DMAC DTC Low Note: 1 CPU The above applies when the priority order of the buses is fixed. The priority order of internal main bus 1 and another bus (internal main bus 2) can be toggled by the bus priority control register (BUSPRI) (round-robin method). 16.2.4 Internal Peripheral Buses Connection of peripheral modules to the internal peripheral buses is as described in Table 16.4.
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RX23W Group 16. Buses R11 R12 (R13) (R13) > > > R24 R25 R21 R22 R23 (R11) R11 (R12) Internal main bus 2 R13 > (R11) > (R11) > (R11) > Internal main bus 1 > Priority order fixed: > > R22 (1) R23 R24 (2) > (R22) R13 > R21 R12 > > Internal main bus 2 > Internal main bus 1 > Priority order toggled: R25 (1), (2) : The priority order does not change because the priority of the accepted request is low.
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RX23W Group 16.2.6 16. Buses Parallel Operation Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For example, if the CPU is fetching an instruction from ROM and an operand from RAM, the DMAC is able to handle transfer between a peripheral bus and the peripheral bus at the same time. An example of parallel operations is shown in Figure 16.4.
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RX23W Group 16.3 16. Buses Register Descriptions 16.3.1 Bus Error Status Clear Register (BERCLR) Address(es): 0008 1300h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — STSCL R 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 STSCLR Status Clear 0: Invalid 1: Bus error status register cleared (W)*1 b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note 1. Only writing 1 is effective; i.e. writing 0 has no effect.
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RX23W Group 16.3.3 16. Buses Bus Error Status Register 1 (BERSR1) Address(es): 0008 1308h b7 b6 — Value after reset: 0 b5 b4 MST[2:0] 0 0 b3 b2 b1 b0 — — TO IA 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 IA Illegal Address Access 0: Illegal address access not made 1: Illegal address access made R b1 TO Timeout 0: Timeout not generated 1: Timeout generated R b3, b2 — Reserved These bits are read as 0. Writing to these bits has no effect.
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RX23W Group 16.3.5 16.
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RX23W Group 16. Buses When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted. BPGB[1:0] Bits (Internal Peripheral Bus 2 and 3 Priority Control) These bits specify the priority order for internal peripheral buses 2 and 3. When the priority order is fixed, internal main bus 2 has priority over internal main bus 1. When the priority order is toggled, a bus has a lower priority when the request of that bus is accepted.
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RX23W Group 16.4 16. Buses Bus Error Monitoring Section The bus error monitoring section monitors the individual areas for bus errors, and when a bus error occurs, the error is indicated to the bus master. 16.4.1 Types of Bus Error There are two types of bus error: illegal address access and timeout. Illegal address access is the detection of illegal access to an area, and time-out is the detection of a bus-access operation not being completed within 768 cycles. 16.4.1.
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RX23W Group 16.4.2 16. Buses Operations When a Bus Error Occurs When a bus error occurs, the error is indicated to the CPU. Operation is not guaranteed when a bus error occurs. • Bus error indication to the CPU An interrupt is generated. The IERn register in the ICU can specify whether to generate an interrupt in the case of a bus error. 16.4.3 Conditions Leading to Bus Errors Table 16.5 lists the types of bus errors for each area in the respective address space.
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RX23W Group 16.5 16. Buses Interrupt 16.5.1 Interrupt Source An illegal address access error or detection of a timeout leads to a bus error signal for the interrupt controller. Table 16.6 Interrupt Source Name Interrupt Source DTC Activation DMAC Activation BUSERR Illegal address access error or timeout Not possible Not possible R01UH0823EJ0110 Rev.1.
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RX23W Group 17. Memory-Protection Unit (MPU) 17. Memory-Protection Unit (MPU) 17.1 Overview The RXv2 CPU incorporates a memory-protection unit that checks the addresses of CPU access to the overall address space (0000 0000h to FFFF FFFFh). Access-control information can be set for up to eight regions, and permission for access to each region is in accord with this information.
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RX23W Group 17.
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RX23W Group 17.1.1 17. Memory-Protection Unit (MPU) Types of Access Control There are three types of access control information: permission for instruction execution, permission to read operands, and permission to write operands. Violations of these types of access control are only detected when programs are running in user mode. Violations are not detected when programs are running in supervisor mode. 17.1.2 Regions for Access Control Up to eight regions for access control are definable.
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RX23W Group 17.2 17. Memory-Protection Unit (MPU) Register Descriptions 17.2.
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RX23W Group 17.2.2 17.
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RX23W Group 17.2.3 17.
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RX23W Group 17.2.4 17.
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RX23W Group 17.2.5 17.
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RX23W Group 17.2.6 17.
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RX23W Group 17.2.7 17.
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RX23W Group 17.2.9 17. Memory-Protection Unit (MPU) Region Search Operation Register (MPOPS) Address(es): 0008 6524h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — — — — — — — — S 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b0 S Region Search Operation Activation [Reading] 0: Fixed value for reading [Writing] 0: Nothing is done. 1: A region-search operation proceeds.
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RX23W Group 17.2.11 17.
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RX23W Group 17. Memory-Protection Unit (MPU) UHACI[2:0] Bits (Instruction-Hit Region Access Control Bits in User Mode) These bits hold the user-mode access control bits (REPAGEn.UAC[2:0]) for the region where the instruction memoryprotection error was generated. If the error was generated in an overlap between regions, the value stored here is the logical OR of the user-mode access control bits for the corresponding regions (including the background region).
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RX23W Group 17.2.12 17.
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RX23W Group 17. Memory-Protection Unit (MPU) HITD[7:0] Bits (Data-Hit Region) These bits indicate the region where a data memory-protection error was generated or the region that produced a hit in a region search. These bits are set to 0000 0000b for a data memory-protection error generated in the background region. Note: When access to a register of memory protection unit in user mode generates a data memory-protection error, the value in this register is cleared to 0000 0000h. R01UH0823EJ0110 Rev.1.
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RX23W Group 17.3 17.3.1 17. Memory-Protection Unit (MPU) Functions Memory Protection Memory protection means monitoring, in accord with the access-control information that has been set for the individual access-control regions and the background region, whether or not access by programs running in user mode violates the access-control settings.
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RX23W Group 17.3.4 17. Memory-Protection Unit (MPU) Flow for Determination of Access by the Memory-Protection Function Figure 17.2 shows the flow of determination in the case of data access and Figure 17.3 shows the flow of determination in the case of instruction access.
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RX23W Group 17. Memory-Protection Unit (MPU) Instruction access by the CPU Processor mode? Supervisor mode Permit instruction access User mode Is memory protection enabled? No Permit instruction access Yes Is access to an accesscontrol region? No Yes Determination in accord with the access-control information for the given region*1 Access prohibited Access permitted Permit instruction access Note 1. Figure 17.
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RX23W Group 17.4 17.4.1 17. Memory-Protection Unit (MPU) Procedures for Using Memory Protection Setting Access-Control Information Access-control information for the various regions is set in supervisor mode. Settings for up to eight access-control regions are made in the region-n start page number registers (RSPAGEn) and region-n end page number registers (REPAGEn), where n = 0 to 7. Settings for the background access-control region are made in the background access-control register (MPBAC). 17.4.
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RX23W Group (1) 17. Memory-Protection Unit (MPU) When a data memory-protection error is generated Access-exception processing by the CPU saves the address of the instruction that led to the memory-protection error on the stack.
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RX23W Group 18. 18. DMA Controller (DMACA) DMA Controller (DMACA) This MCU incorporates a 4-channel direct memory access controller (DMAC). The DMAC module performs data transfers without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address. 18.1 Overview Table 18.1 lists the specifications of the DMAC, and Figure 18.1 shows a block diagram of the DMAC. Table 18.
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RX23W Group 18.
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RX23W Group 18.2 18. DMA Controller (DMACA) Register Descriptions 18.2.1 DMA Source Address Register (DMSAR) Address(es): DMAC0.DMSAR 0008 2000h, DMAC1.DMSAR 0008 2040h, DMAC2.DMSAR 0008 2080h, DMAC3.
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RX23W Group 18.2.3 18. DMA Controller (DMACA) DMA Transfer Count Register (DMCRA) Address(es): DMAC0.DMCRA 0008 2008h, DMAC1.DMCRA 0008 2048h, DMAC2.DMCRA 0008 2088h, DMAC3.
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RX23W Group (2) 18. DMA Controller (DMACA) Repeat Transfer Mode (MD[1:0] Bits in DMACm.DMTMD = 01b) DMCRAH specifies the repeat size and DMCRAL functions as a 10-bit transfer counter. The number of transfer operations is one when the setting is 001h, 1023 when it is 3FFh, and 1024 when it is 000h. In repeat transfer mode, a value in the range of 000h to 3FFh (1 to 1024) can be set for DMCRAH and DMCRAL. Setting bits 15 to 10 in DMCRAL is invalid. Write 0 to these bits.
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RX23W Group 18.2.4 18. DMA Controller (DMACA) DMA Block Transfer Count Register (DMCRB) Address(es): DMAC0.DMCRB 0008 200Ch, DMAC1.DMCRB 0008 204Ch, DMAC2.DMCRB 0008 208Ch, DMAC3.DMCRB 0008 20CCh Value after reset: b15 b14 b13 b12 b11 b10 — — — — — — 0 0 0 0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 Bit Description Setting Range R/W b9 to b0 Specifies the number of block transfer operations or repeat transfer operations.
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RX23W Group 18.2.5 18. DMA Controller (DMACA) DMA Transfer Mode Register (DMTMD) Address(es): DMAC0.DMTMD 0008 2010h, DMAC1.DMTMD 0008 2050h, DMAC2.DMTMD 0008 2090h, DMAC3.
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RX23W Group 18.2.6 18. DMA Controller (DMACA) DMA Interrupt Setting Register (DMINT) Address(es): DMAC0.DMINT 0008 2013h, DMAC1.DMINT 0008 2053h, DMAC2.DMINT 0008 2093h, DMAC3.
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RX23W Group 18. DMA Controller (DMACA) RPTIE Bit (Repeat Size End Interrupt Enable) When this bit is set to 1 in repeat transfer mode, the DTE bit in DMCNT is cleared to 0 after completion of a 1-repeat size data transfer. At the same time, the ESIF flag in DMSTS is set to 1 to indicate that the repeat size end interrupt request has been generated. The repeat size end interrupt request can be generated even when the DTS[1:0] bits in DMTMD are 10b (= repeat area or block area is not specified).
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RX23W Group 18.2.7 18. DMA Controller (DMACA) DMA Address Mode Register (DMAMD) Address(es): DMAC0.DMAMD 0008 2014h, DMAC1.DMAMD 0008 2054h, DMAC2.DMAMD 0008 2094h, DMAC3.
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RX23W Group 18. DMA Controller (DMACA) SARA[4:0] Bits (Source Address Extended Repeat Area) These bits specify the extended repeat area on the source address. The extended repeat area function is realized by updating the specified lower address bits with the remaining upper address bits fixed. The size of the extended repeat area can be any power of two between 21 (2 bytes) and 217 (128 Mbytes).
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RX23W Group Table 18.2 18.
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RX23W Group 18.2.8 18. DMA Controller (DMACA) DMA Offset Register (DMOFR) Address(es): DMAC0.
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RX23W Group 18.2.9 18. DMA Controller (DMACA) DMA Transfer Enable Register (DMCNT) Address(es): DMAC0.DMCNT 0008 201Ch, DMAC1.DMCNT 0008 205Ch, DMAC2.DMCNT 0008 209Ch, DMAC3.DMCNT 0008 20DCh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — DTE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 DTE DMA Transfer Enable 0: Disables DMA transfer. 1: Enables DMA transfer. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 18.2.10 18. DMA Controller (DMACA) DMA Software Start Register (DMREQ) Address(es): DMAC0.DMREQ 0008 201Dh, DMAC1.DMREQ 0008 205Dh, DMAC2.DMREQ 0008 209Dh, DMAC3.DMREQ 0008 20DDh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — CLRS — — — SWRE Q 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 SWREQ DMA Software Start 0: DMA transfer is not requested. 1: DMA transfer is requested. R/W b3 to b1 — Reserved These bits are read as 0.
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RX23W Group 18.2.11 18. DMA Controller (DMACA) DMA Status Register (DMSTS) Address(es): DMAC0.DMSTS 0008 201Eh, DMAC1.DMSTS 0008 205Eh, DMAC2.DMSTS 0008 209Eh, DMAC3.DMSTS 0008 20DEh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ACT — — DTIF — — — ESIF 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 ESIF Transfer Escape End Interrupt Flag 0: A transfer escape end interrupt has not been generated. 1: A transfer escape end interrupt has been generated.
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RX23W Group 18. DMA Controller (DMACA) DTIF Flag (Transfer End Interrupt Flag) This flag indicates that the transfer end interrupt has been generated.
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RX23W Group 18.2.12 18. DMA Controller (DMACA) DMA Activation Source Flag Control Register (DMCSL) Address(es): DMAC0.DMCSL 0008 201Fh, DMAC1.DMCSL 0008 205Fh, DMAC2.DMCSL 0008 209Fh, DMAC3.DMCSL 0008 20DFh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — DISEL 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 DISEL Interrupt Select 0: At the beginning of transfer, clear the interrupt flag of the activation source to 0.
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RX23W Group 18.2.13 18. DMA Controller (DMACA) DMA Module Activation Register (DMAST) Address(es): 0008 2200h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — DMST 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 DMST DMAC Operation Enable 0: DMAC activation is disabled. 1: DMAC activation is enabled. R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 18.3 Operation 18.3.1 (1) 18. DMA Controller (DMACA) Transfer Mode Normal Transfer Mode In normal transfer mode, one data is transferred by one transfer request. A maximum of 65535 can be set as the number of transfer operations using the DMCRAL of DMACm. When these bits are set to 0000h, no specific number of transfer operations is set; data transfer is performed with the transfer counter stopped (free running mode). Setting DMCRB of DMACm is invalid in normal transfer mode.
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RX23W Group (2) 18. DMA Controller (DMACA) Repeat Transfer Mode In repeat transfer mode, one data is transferred by one transfer request. A maximum of 1K data can be set as a total repeat transfer size using DMCRA of the DMACm. A maximum of 1K can be set as the number of repeat transfer operations using DMCRB of the DMACm; therefore, a maximum of 1M data (1K data × 1K count of repeat transfer operations) can be set as a total data transfer size.
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RX23W Group 18. DMA Controller (DMACA) Transfer source data area (Specified as a repeat area) Transfer destination data area Data 1 Data 1 DMSAR Data 2 Transfer DMDAR Data 2 Data 3 Data 3 Data 4 Data 4 Data 1 Data 2 Data 3 Data 4 Figure 18.3 Operation in Repeat Transfer Mode R01UH0823EJ0110 Rev.1.
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RX23W Group (3) 18. DMA Controller (DMACA) Block Transfer Mode In block transfer mode, a single block data is transferred by one transfer request. A maximum of 1K data can be set as a total block transfer size using DMCRA of the DMACm. A maximum of 1K can be set as the number of block transfer operations using DMCRB of the DMACm; therefore, a maximum of 1M data (1K data × 1K count of block transfer operations) can be set as a total data transfer size.
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RX23W Group 18.3.2 18. DMA Controller (DMACA) Extended Repeat Area Function The DMAC supports a function to specify the extended repeat areas on the transfer source and destination addresses. With the extended repeat areas set, the address registers repeatedly indicate the addresses of the specified extended repeat areas. The extended repeat areas can be specified separately to the transfer source address register (DMSAR) and transfer destination address register (DMDAR) of DMACm.
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RX23W Group 18. DMA Controller (DMACA) When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary.
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RX23W Group 18.3.3 18. DMA Controller (DMACA) Address Update Function Using Offset The source and destination addresses can be updated by fixing, increment, decrement, or offset addition. When the offset addition is selected, the offset specified by the DMA offset register (DMOFR of DMAC0) is added to the address every time the DMAC performs one data transfer. This function realizes a data transfer where addresses are allocated to separated areas.
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RX23W Group (1) 18. DMA Controller (DMACA) Basic Transfer Using Offset Addition Figure 18.7 shows an example of address updating using offset addition.
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RX23W Group (2) 18. DMA Controller (DMACA) Example of XY Conversion Using Offset Addition Figure 18.8 shows the XY conversion using offset addition in repeat transfer mode. Settings are as follows: • DMAC0.DMAMD: Transfer source address update mode: Offset addition • DMAC0.DMAMD: Transfer destination address update mode: Destination address is incremented. • DMAC0.DMTMD: Transfer data size select: 32 bits • DMAC0.DMTMD: Transfer mode select: Repeat transfer • DMAC0.
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RX23W Group 18. DMA Controller (DMACA) Figure 18.9 shows a flowchart of the XY conversion. Start Set the address, repeat size, and number of repeat operations. Set repeat transfer mode. Enable repeat size end interrupts. Write 1 to the DTE bit in DMAC0.DMCNT. Receive a transfer request. Data transfer Repeat size and number of repeat operations decremented. No Number of repeat operations = 0 Yes No Repeat size = 0 Yes Return to the transfer source address. Generate a repeat size end interrupt.
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RX23W Group 18.3.4 18. DMA Controller (DMACA) Activation Sources Software, the interrupt requests from the peripheral modules, and the external interrupt requests can be specified as the DMAC activation sources. Setting the DCTG[1:0] bits in DMTMD of DMACm selects the activation source. (1) DMAC Activation by Software Setting the DCTG[1:0] bits in DMTMD of DMACm to 00b enables the DMAC activation by software.
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RX23W Group 18.3.5 18. DMA Controller (DMACA) Operation Timing Figure 18.10 and Figure 18.11 show DMAC operation timing examples. System clock IRn in the ICU DMAC activation request DMAC access R W Data transfer Figure 18.10 DMAC Operation Timing Example (1) (DMA Activation by Interrupt from Peripheral Module/ External Interrupt Input Pin, Normal Transfer Mode, Repeat Transfer Mode) System clock IRn in the ICU DMAC activation request DMAC access Data transfer Figure 18.
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RX23W Group 18.3.6 18. DMA Controller (DMACA) DMAC Execution Cycles Table 18.7 lists execution cycles in one DMAC data transfer operation. Table 18.7 DMAC Execution Cycles Transfer Mode Data Transfer (Read) Data Transfer (Write) Normal Cr+1 Cw Repeat Cr+1 Cw Block*1 P × Cr P × Cw Note 1. This is the case when the block size is 2 or more. When the block size is 1, normal transfer cycle is applied.
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RX23W Group 18.3.7 18. DMA Controller (DMACA) Activating the DMAC Figure 18.12 shows the register setting procedure. Start of initial settings To use peripheral function interrupts as DMA activation sources Set the peripheral module as a DMACm request source. To use external pin interrupts as DMA activation sources To use on-chip peripheral interrupts or external pin interrupts as DMA activation sources Set the IRQ pin function using the interrupt controller (ICU).
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RX23W Group 18.3.8 18. DMA Controller (DMACA) Starting DMA Transfer Setting the DTE bit in DMCNT of DMACm to 1 (DMA transfer enabled) and setting the DMST bit in DMAST to 1 (DMAC start enabled) enable DMA transfer of channel m (m = 0 to 3). Another activation request cannot be accepted during the transfer of other DMAC channel or DTC.
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RX23W Group (6) 18. DMA Controller (DMACA) DMA Active Flag (DMACm.DMSTS.ACT) The ACT bit in DMSTS of DMACm indicates whether the DMACm is in the idle or active state. This flag is set to 1 when the DMAC starts data transfer, and is cleared to 0 when data transfer in response to one transfer request is completed. Even when DMA transfer is stopped by writing 0 to the DTE bit in DMCNT of DMACm during DMA transfer, this flag remains 1 until DMA transfer is completed.
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RX23W Group 18.4 18. DMA Controller (DMACA) Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the DTE bit in DMCNT and the ACT flag in DMSTS of DMACm are changed from 1 to 0, indicating that DMA transfer has ended. 18.4.1 (1) Transfer End by Completion of Specified Total Number of Transfer Operations In Normal Transfer Mode (DMACm.DMTMD.
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RX23W Group 18.4.3 18. DMA Controller (DMACA) Transfer End by Interrupt on Extended Repeat Area Overflow When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DMINT of DMACm is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMCNT of DMACm is cleared to 0, and the ESIF flag in DMSTS of DMACm is set to 1.
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RX23W Group 18.5 18. DMA Controller (DMACA) Interrupts Each DMAC channel can output an interrupt request to the CPU or the DTC after transfer in response to one request is completed. When the transfer destination is the on-chip peripheral bus, an interrupt request is generated upon completion of data write to the write buffer not to the actual transfer destination. Table 18.8 lists the relation among the interrupt sources, the interrupt status flags, and the interrupt enable bits. Figure 18.
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RX23W Group 18. DMA Controller (DMACA) Specifically, the different procedures are used for canceling an interrupt to restart DMA transfer in the following two cases: (1) discontinuing or terminating DMA transfer and (2) continuing DMA transfer. (1) When Discontinuing or Terminating DMA Transfer Write 0 to the DTIF bit in DMSTS of DMACm to clear a transfer end interrupt, and to the ESIF bit in DMSTS of DMACm to clear a repeat size interrupt and an extended repeat area overflow interrupt.
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RX23W Group 18.7 18. DMA Controller (DMACA) Low Power Consumption Function Before transition to the module stop state or software standby mode, clear the DMAST.DMST bit to 0 (DMAC activation is disabled), and then perform the following. (1) Module Stop Function Writing 1 to the MSTPA28 bit (transition to the module-stop state) in MSTPCRA enables the module-stop function of the DMAC.
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RX23W Group 18.8 18.8.1 18. DMA Controller (DMACA) Usage Notes DMA Transfer to Peripheral Modules In DMA transfer to a peripheral module, the ACT bit in DMSTS of DMACm may be cleared to 0 (DMAC transfer suspended) during the period from the beginning of the final data write to the end of the peripheral bus access. 18.8.
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RX23W Group 19. 19. Data Transfer Controller (DTCa) Data Transfer Controller (DTCa) This MCU incorporates a data transfer controller (DTC). The DTC is triggered by an interrupt request to perform data transfers. 19.1 Overview Table 19.1 lists the specifications of the DTC, and Figure 19.1 shows a block diagram of the DTC. Table 19.1 DTC Specifications Item Description Number of transfer channels • The same number as all interrupt sources that can start the DTC transfer.
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RX23W Group 19. Data Transfer Controller (DTCa) DTC MRA MRB DTC internal bus CRA Register control Vector number CRB SAR DAR Interrupt controller Activation control Transfer request DTC response Bus interface DTCCR DTC response control DTCVBR DTCADMOD DTCST DTCSTS Internal peripheral bus 1 Internal main bus 1 Internal main bus 2 MRA: MRB: CRA: CRB: SAR: DAR: Figure 19.
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RX23W Group 19.2 19. Data Transfer Controller (DTCa) Register Descriptions Registers MRA, MRB, SAR, DAR, CRA, and CRB are DTC internal registers, which cannot be directly accessed from the CPU. Values to be set in these DTC internal registers are placed in the RAM area as transfer information. When accepting a transfer request, the DTC reads the transfer information from the RAM area and sets it in the internal registers.
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RX23W Group 19.2.2 19. Data Transfer Controller (DTCa) DTC Mode Register B (MRB) Address(es): (inaccessible directly from the CPU) b7 CHNE x Value after reset: b6 b5 CHNS DISEL x x b4 b3 DTS x b2 DM[1:0] x x b1 b0 — — x x x: Undefined Bit Symbol Bit Name Description R/W b1, b0 — Reserved Set these bits to 0. — b3, b2 DM[1:0] Transfer Destination Address Addressing Mode b3 b2 — b4 DTS DTC Transfer Mode Select 0: Transfer destination side is repeat area or block area.
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RX23W Group 19.2.3 19. Data Transfer Controller (DTCa) DTC Transfer Source Register (SAR) Address(es): (inaccessible directly from the CPU) Value after reset: Value after reset: b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 x x x x x x x x x x x x x x x x b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 x x x x x x x x x x x x x x x x x: Undefined SAR register is used to set the transfer source start address.
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RX23W Group 19.2.5 19.
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RX23W Group 19.2.6 19. Data Transfer Controller (DTCa) DTC Transfer Count Register B (CRB) Address(es): (inaccessible directly from the CPU) Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 x x x x x x x x x x x x x x x x x: Undefined CRB register is used to set the block transfer count for block transfer mode and cannot be accessed directly from the CPU.
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RX23W Group 19.2.8 19. Data Transfer Controller (DTCa) DTC Vector Base Register (DTCVBR) Address(es): DTC.
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RX23W Group 19.2.10 19. Data Transfer Controller (DTCa) DTC Module Start Register (DTCST) Address(es): DTC.DTCST 0008 240Ch Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — DTCST 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 DTCST DTC Module Start 0: DTC module stop 1: DTC module start R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0.
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RX23W Group 19.2.11 19. Data Transfer Controller (DTCa) DTC Status Register (DTCSTS) Address(es): DTC.DTCSTS 0008 240Eh Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 ACT — — — — — — — 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 VECN[7:0] 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 VECN[7:0] DTC Active Vector Number Monitoring Flag These bits indicate the vector number for the request source when data transfer is in progress.
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RX23W Group 19.3 19. Data Transfer Controller (DTCa) Request Sources The DTC data transfer is triggered by an interrupt request. Setting the ICU.DTCERn.DTCE bit (n = interrupt vector number) to 1 selects the corresponding interrupt request as a request source for the DTC. For the correspondence between the DTC request sources and the vector addresses, refer to section 15.3.1, Interrupt Vector Table in section 15, Interrupt Controller (ICUb). For request by software, refer to section 15.2.
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RX23W Group 19. Data Transfer Controller (DTCa) DTC vector table Transfer information 0 DTC vector base address Start address of transfer information 0 Start address of transfer information 1 Start address of transfer information 2 +4 +8 +4n Transfer information 1 Start address of transfer information n 4 bytes Transfer information n Vector address = DTCVBR + vector number × 4 Figure 19.
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RX23W Group 19.4 19. Data Transfer Controller (DTCa) Operation The DTC transfers data in accordance with the transfer information. Storage of the transfer information in the RAM area is required before DTC operation. When the DTC accepts a transfer request, it reads the DTC vector corresponding to the vector number. Next, the DTC reads transfer information from the address pointed by the DTC vector, transfers data, and then writes back the transfer information after the data transfer.