RX23W Group 19. Data Transfer Controller (DTCa) Start Match and RRS bit = 1 Compare vector numbers.
RX23W Group Table 19.3 19.
RX23W Group 19.4.2 19. Data Transfer Controller (DTCa) Transfer Information Write-Back Skip Function When the MRA.SM[1:0] bits or the MRB.DM[1:0] bits are set to “address is fixed” (00b or 01b), a part of transfer information is not written back. This function is performed independently of the setting of short-address mode or fulladdress mode. Table 19.4 lists transfer information write-back skip conditions and applicable registers.
RX23W Group 19.4.3 19. Data Transfer Controller (DTCa) Normal Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single transfer request. The transfer count can be set to 1 to 65536. Transfer source addresses and transfer destination addresses can be set to increment, decrement, or fixed independently. This mode enables an interrupt request to the CPU to be generated at the end of specified-count transfer. Table 19.
RX23W Group 19.4.4 19. Data Transfer Controller (DTCa) Repeat Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single transfer request. Specify either transfer source or transfer destination for the repeat area by the MRB.DTS bit. The transfer count can be set to 1 to 256. When the specified-count transfer is completed, the initial value of the address register specified in the transfer counter and the repeat area is restored and transfer is repeated.
RX23W Group 19.4.5 19. Data Transfer Controller (DTCa) Block Transfer Mode This mode allows single-block data transfer on a single transfer request. Specify either transfer source or transfer destination for the block area by the MRB.DTS bit. The block size can be set to 1 to 256 bytes, 1 to 256 words, or 1 to 256 longwords. When transfer of the specified one block is completed, the initial values of the block size counter CRAL and the address register (the SAR register when the MRB.
RX23W Group 19.4.6 19. Data Transfer Controller (DTCa) Chain Transfer Setting the MRB.CHNE bit to 1 allows chain transfer to be performed continuously on a single transfer request. If the MRB.CHNE bit is 1 and the MRB.CHNS bit is 0, an interrupt request to the CPU is not generated when the specified number of data transfers is completed, or while the MRB.DISEL bit is 1 (an interrupt request to the CPU is generated for every data transfer).
RX23W Group 19.4.7 19. Data Transfer Controller (DTCa) Operation Timing Figure 19.9 to Figure 19.13 show examples of DTC operation timing. System clock ICU.IRn DTC transfer request DTC access R Vector read Transfer information read W Data transfer Transfer information write n = Vector number Figure 19.9 Example (1) of DTC Operation Timing (Short-Address Mode, Normal Transfer Mode, Repeat Transfer Mode) System clock ICU.
RX23W Group 19. Data Transfer Controller (DTCa) System clock ICU.IRn DTC transfer request DTC access R Vector read Transfer information read W Data transfer n = Vector number Figure 19.11 R Transfer information read Transfer information write W Data transfer Transfer information write Example (3) of DTC Operation Timing (Short-Address Mode, Chain Transfer) System clock ICU.
RX23W Group 19. Data Transfer Controller (DTCa) System clock ICU.IRn (2) (1) DTC transfer request Read skip enable R DTC access Vector read Transfer information read W Data transfer RR W Transfer information write Data transfer Transfer information write n = Vector number Note: When request sources (vector numbers) of (1) and (2) are the same and the DTCCR.RRS bit is 1, the transfer information read for request (2) is skipped. Figure 19.
RX23W Group 19.4.8 19. Data Transfer Controller (DTCa) Execution Cycles of the DTC Table 19.8 lists the execution cycles of single data transfer of the DTC. For the order of the execution states, refer to section 19.4.7, Operation Timing. Table 19.
RX23W Group 19.5 19. Data Transfer Controller (DTCa) DTC Setting Procedure Before using the DTC, set the DTC vector base register (DTCVBR). Figure 19.14 shows the procedure to set the DTC. Set the ICU.IERm.IENj bit corresponding to the request source interrupt to 0 and provide the following settings. Start [1] Setting the DTCCR.RRS bit to 0 resets the transfer information read skip flag. After that, transfer information read is not skipped during the data transfer.
RX23W Group 19.6 19. Data Transfer Controller (DTCa) Examples of DTC Usage 19.6.1 Normal Transfer As an example of DTC usage, its employment in the reception of 128 bytes of data by an SCI is described below. (1) Transfer Information Setting Set the MRA.MD[1:0] bits to 00b (normal transfer mode), the MRA.SZ[1:0] bits to 00b (byte transfer), and the MRA.SM[1:0] bits to 00b (source address is fixed). Set the MRB.CHNE bit to 0 (chain transfer is disabled), the MRB.
RX23W Group 19.6.2 19. Data Transfer Controller (DTCa) Chain Transfer When the Counter is 0 The second data transfer is performed only when the transfer counter is set to 0 in the first data transfer, and the first data transfer information is repeatedly changed in the second data transfer. Repeating this chain transfer enables transfers to be repeated more than 256 times.
RX23W Group 19. Data Transfer Controller (DTCa) Input circuit Transfer information allocated in the on-chip memory space Input buffer First data transfer Transfer information Chain transfer (counter = 0) Second data transfer Transfer information Upper 8 bits of DAR Figure 19.15 19.7 Chain Transfer When the Counter is 0 Interrupt Source When the DTC has finished data transfer of specified count or when data transfer with the MRB.
RX23W Group 19.9 19. Data Transfer Controller (DTCa) Low Power Consumption Function Before making a transition to the module stop state, deep sleep mode, or software standby mode, set the DTCST.DTCST bit to 0 (DTC module stop), and then perform the following. (1) Module Stop Function Writing 1 (transition to the module-stop state is made) to the MSTPCRA.MSTPA28 bit enables the module stop function of the DTC. If data transfer is in progress at the time 1 is written to the MSTPCRA.
RX23W Group 19. Data Transfer Controller (DTCa) 19.10 Usage Notes 19.10.1 Start Address of Transfer Information Set multiples of 4 for the start addresses of the transfer information to be specified in the DTC vector table. If any value other than a multiple of 4 is specified, access still proceeds with the lower 2 bits of the address regarded as 00b. 19.10.2 Allocating Transfer Information Allocate transfer information in the memory area according to the endian of the area as shown in Figure 19.16.
RX23W Group 19.10.3 19. Data Transfer Controller (DTCa) Setting the DTC Transfer Request Enable Register in the Interrupt Controller (ICU.DTCERn) The DMA request should not be issued by setting the DMAC trigger select register (ICU.DMRSRm (m = DMAC channel number)) to the same vector number that has been specified by setting the ICU.DTCERn.DTCE bit to 1 (the corresponding interrupt source is selected as the DTC trigger). For details on the ICU.DTCERn and ICU.
RX23W Group 20. Event Link Controller (ELC) 20. Event Link Controller (ELC) 20.1 Overview The event link controller (ELC) uses the interrupt requests generated by various peripheral modules as event signals, and interconnects (links) peripheral modules. As a result, peripheral modules can directly perform interlinked operation among them without using software. Event signals can be output regardless of the settings of the corresponding interrupt request enable bits. Table 20.
RX23W Group 20.2 20. Event Link Controller (ELC) Register Descriptions 20.2.1 Event Link Control Register (ELCR) Address(es): ELC.ELCR 0008 B100h b7 b6 b5 b4 b3 b2 b1 b0 ELCON — — — — — — — 0 1 1 1 1 1 1 1 Value after reset: Bit Symbol Bit Name Description R/W b6 to b0 — Reserved These bits are read as 1. The write value should be 1. R/W b7 ELCON All Event Link Enable 0: ELC function is disabled. 1: ELC function is enabled.
RX23W Group 20.2.2 20. Event Link Controller (ELC) Event Link Setting Register n (ELSRn) (n = 1 to 4, 7, 8, 10, 12, 14 to 16, 18 to 29) Address(es): ELC.ELSR1 0008 B102h, ELC.ELSR2 0008 B103h, ELC.ELSR3 0008 B104h, ELC.ELSR4 0008 B105h, ELC.ELSR7 0008 B108h, ELC.ELSR8 0008 B109h, ELC.ELSR10 0008 B10Bh, ELC.ELSR12 0008 B10Dh, ELC.ELSR14 0008 B10Fh, ELC.ELSR15 0008 B110h, ELC.ELSR16 0008 B111h, ELC.ELSR18 0008 B113h, ELC.ELSR19 0008 B114h, ELC.ELSR20 0008 B115h, ELC.ELSR21 0008 B116h, ELC.
RX23W Group Table 20.3 20. Event Link Controller (ELC) Correspondence between Values Set in ELSRn.
RX23W Group Table 20.3 20. Event Link Controller (ELC) Correspondence between Values Set in ELSRn.
RX23W Group 20.2.3 20. Event Link Controller (ELC) Event Link Option Setting Register A (ELOPA) Address(es): ELC.ELOPA 0008 B11Fh b7 b6 MTU3MD[1:0] Value after reset: 1 1 b5 b4 MTU2MD[1:0] 1 1 b3 b2 MTU1MD[1:0] 1 1 b1 b0 — — 1 1 Bit Symbol Bit Name Description R/W b1, b0 — Reserved These bits are read as 1. The write value should be 1.
RX23W Group 20.2.5 20. Event Link Controller (ELC) Event Link Option Setting Register C (ELOPC) Address(es): ELC.ELOPC 0008 B121h Value after reset: b7 b6 b5 — — LPTMD[1:0] 1 1 1 b4 1 b3 b2 CMT1MD[1:0] 1 1 b1 b0 — — 1 1 Bit Symbol Bit Name Description R/W b1, b0 — Reserved These bits are read as 1. The write value should be 1.
RX23W Group 20.2.7 20. Event Link Controller (ELC) Port Group Setting Register n (PGRn) (n = 1, 2) Address(es): ELC.PGR1 0008 B123h, ELC.PGR2 0008 B124h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PGR7 PGR6 PGR5 PGR4 PGR3 PGR2 PGR1 PGR0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 PGR0 Port Group Setting 0 R/W b1 PGR1 Port Group Setting 1 0: Does not specify the port as a member of the port group. 1: Specifies the port as a member of the port group.
RX23W Group 20.2.8 20. Event Link Controller (ELC) Port Group Control Register n (PGCn) (n = 1, 2) Address(es): ELC.PGC1 0008 B125h, ELC.PGC2 0008 B126h b7 b6 — Value after reset: 1 b5 b4 PGCO[2:0] 0 0 0 b3 b2 — PGCO VE 1 0 b1 b0 PGCI[1:0] 0 0 Bit Symbol Bit Name Description R/W b1, b0 PGCI[1:0] Event Output Edge Select b1 b0 R/W b2 PGCOVE PDBF Overwrite 0: Overwriting the PDBFn register is disabled. 1: Overwriting the PDBFn register is enabled.
RX23W Group 20.2.9 20. Event Link Controller (ELC) Port Buffer Register n (PDBFn) (n = 1, 2) Address(es): ELC.PDBF1 0008 B127h, ELC.PDBF2 0008 B128h b7 b6 b5 b4 b3 b2 b1 b0 PDBF7 PDBF6 PDBF5 PDBF4 PDBF3 PDBF2 PDBF1 PDBF0 Value after reset: 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 PDBF0 Port Buffer 0 Specify the data to be transferred to the PODR register when an event signal is input. The setting value is valid when the PGCn.PGCO[2:0] bits are 011b or 1xxb.
RX23W Group 20.2.10 20. Event Link Controller (ELC) Event Link Port Setting Register m (PELm) (m = 0 to 3) Address(es): ELC.PEL0 0008 B129h, ELC.PEL1 0008 B12Ah, ELC.PEL2 0008 B12Bh, ELC.PEL3 0008 B12Ch b7 Value after reset: b6 b5 b4 b3 — PSM[1:0] PSP[1:0] 1 0 0 0 0 b2 b1 b0 PSB[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 PSB[2:0] Bit Number Specification Set a bit number for a port to be specified as a single port.
RX23W Group 20.2.11 20. Event Link Controller (ELC) Event Link Software Event Generation Register (ELSEGR) Address(es): ELC.ELSEGR 0008 B12Dh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 WI WE — — — — — SEG 1 0 1 1 1 1 1 0 Bit Symbol Bit Name Description R/W b0 SEG Software Event Generation 0: Normal operation 1: Software event is generated. W b5 to b1 — Reserved These bits are read as 1. The write value should be 1.
RX23W Group 20.3 20. Event Link Controller (ELC) Operation 20.3.1 Relation between Interrupt Handling and Event Linking The peripheral modules incorporated in the MCU are provided with the interrupt request status flags and the interrupt enable bits to enable/disable these interrupt requests. When an interrupt request is generated in a peripheral module, the corresponding interrupt request status flag becomes 1.
RX23W Group 20.3.2 20. Event Link Controller (ELC) Event Linkage When events are specified in the ELSRn registers, the corresponding peripheral modules can be operated at generation of the specified events. A single peripheral module can link only with a single event. Set the ELSRn register after completing the initialization of the peripheral module to operate by an event. Table 20.5 lists the operations of peripheral modules when an event signal is input. Table 20.
RX23W Group 20.3.3 20. Event Link Controller (ELC) Operation of Peripheral Timer Modules When Event Signal is Input For the timer modules, set the ELOPA to ELOPD register to specify the operation for when an event signal is input. (1) Count Start Operation When an event signal is input, the timer starts counting and the count start bit*1 in each timer control register becomes 1. An event signal that is input while the count start bit is 1 is ignored.
RX23W Group (2) 20. Event Link Controller (ELC) Event Generation in Single Input Ports A single port that is set as input generates an event signal when the input signal to the corresponding pin changes. The event generation condition is specified using the PELm.PSM[1:0] bits (m = 0 to 3). An example of operation is shown in Figure 20.3 (1).
RX23W Group (5) 20. Event Link Controller (ELC) Input Port Group Operation When Event Signal is Input When an event signal is input to an input port group, the level of the corresponding pins is transferred to the PDBFn register. Values of the bits corresponding to ports that are not specified as members of the input port group do not change. An example of operation is shown in Figure 20.4.
RX23W Group 20. Event Link Controller (ELC) (7) Operation of the PDBFn Registers (a) Input Port Groups When an event signal is input to an input port group, the level of the corresponding pins is transferred to the PDBFn register (n = 1, 2). When another event signal is input to the input port group in this condition, different operations are performed depending on the PGCn.PGCOVE bit setting described as below. • When the PGCn.
RX23W Group (8) 20. Event Link Controller (ELC) Restrictions on Writing to PODR and PDBF Registers When the ELCR.ELCON bit is 1 (ELC function is enabled), write access to the PODR and PDBFn registers (n = 1, 2) becomes disabled at the following conditions. • When a port is specified as a member of the input port group and when the event linkage is set, write access to the corresponding bit in the PDBFn register becomes disabled.
RX23W Group 20.4 Usage Notes 20.4.1 (1) 20. Event Link Controller (ELC) Setting ELSRn Register Setting ELSR8 Register Set this register to 32h (LPT compare match). (2) Setting ELSR18 and ELSR19 Registers Specify an event number from among 63h to 6Ah. Do not set the value other than preceding numbers. (3) Setting ELSR24, ELSR25, ELSR26, and ELSR27 Registers Do not set the DOC data operation condition met signal (6Ah). 20.4.
RX23W Group 21. I/O Ports 21. I/O Ports 21.1 Overview The I/O ports function as a general I/O port, an I/O pin of a peripheral module, an input pin for an interrupt, or a bus control pin. Some of the pins are also configurable as an I/O pin of a peripheral module or an input pin for an interrupt. All pins function as input pins immediately after a reset, and pin functions are switched by register settings.
RX23W Group Table 21.2 21.
RX23W Group 21.2 21. I/O Ports I/O Port Configuration Internal bus Port 0: P03, P05 1: ON 0: OFF PCR PDR PODR PMR Reading the port ASEL bit DA output enable signal Analog output Internal bus Port 0: P07 1: ON PCR 0: OFF PDR 0 1 Enable peripheral module output PODR 0 1 Peripheral module output signal Input signal of peripheral module/interrupt PMR Reading the port Figure 21.1 I/O Port Configuration (1) R01UH0823EJ0110 Rev.1.
RX23W Group 21.
RX23W Group 21.
RX23W Group 21. I/O Ports Internal bus Port 3: P30, P31 1: ON 0: OFF PCR ODR0, ODR1 PDR 0 1 Enable peripheral module output *1 PODR 0 1 Peripheral module output signal Input signal of peripheral module/interrupt PMR Reading the port ISEL bit RTC time capture event input signal Note 1. Control signal for N-channel open-drain output. NMI input signal Internal bus Port 3: P35 Reading the port Figure 21.4 I/O Port Configuration (4) R01UH0823EJ0110 Rev.1.
RX23W Group 21. I/O Ports Internal bus Port 3: P36/EXTAL 1: ON PCR 0: OFF ODR0, ODR1 PDR *1 PODR PMR Reading the port MOSCCR.MOSTP MOFCR.MOSEL 0: ON 1: OFF Main clock Internal bus Port 3: P37/XTAL 1: ON 0: OFF PCR ODR0, ODR1 PDR *1 PODR PMR Reading the port Note 1. Control signal for N-channel open-drain output. Figure 21.5 I/O Port Configuration (5) R01UH0823EJ0110 Rev.1.
RX23W Group 21. I/O Ports Internal bus Port 4: P40 to P46 PCR 1: ON 0: OFF PDR PODR PMR Reading the port ASEL bit Analog input Internal bus Port 4: P47 PCR 1: ON 0: OFF PDR PODR PMR Reading the port ASEL bit Analog input *1 CLKOUT_RF Note 1. Specify from the Bluetooth middleware. Figure 21.6 I/O Port Configuration (6) R01UH0823EJ0110 Rev.1.
RX23W Group 21. I/O Ports Internal bus Port B: PB0, PB1, PB3, PB5, PB7 Port C: PC7 1: ON 0: OFF PCR ODR0, ODR1 PDR 0 1 Enable peripheral module output *1 PODR 0 1 Peripheral module output signal Input signal of peripheral module/interrupt PMR Reading the port ISEL bit *2 Note 1. Control signal for N-channel open-drain output. Note 2. An external interrupt function is multiplexed on this pin. Figure 21.7 I/O Port Configuration (7) R01UH0823EJ0110 Rev.1.
RX23W Group 21.
RX23W Group 21. I/O Ports Internal bus Port E: PE0 to PE4 1: ON 0: OFF PCR ODR0, ODR1 PDR 0 1 Enable peripheral module output *1 PODR 0 1 Peripheral module output signal Input signal of peripheral module/ interrupt PMR Reading the port ISEL bit *2 ASEL bit Analog input Note 1. Control signal for N-channel open-drain output (other than PE1) Control signal for N-channel open-drain and P-channel open-drain (PE1) Note 2. An external interrupt function is multiplexed on this pin Figure 21.
RX23W Group 21.3 21. I/O Ports Register Descriptions 21.3.1 Port Direction Register (PDR) Address(es): PORT0.PDR 0008 C000h, PORT1.PDR 0008 C001h, PORT2.PDR 0008 C002h, PORT3.PDR 0008 C003h, PORT4.PDR 0008 C004h, PORTB.PDR 0008 C00Bh, PORTC.PDR 0008 C00Ch, PORTD.PDR 0008 C00Dh, PORTE.PDR 0008 C00Eh, PORTJ.
RX23W Group 21.3.2 21. I/O Ports Port Output Data Register (PODR) Address(es): PORT0.PODR 0008 C020h, PORT1.PODR 0008 C021h, PORT2.PODR 0008 C022h, PORT3.PODR 0008 C023h, PORT4.PODR 0008 C024h, PORTB.PODR 0008 C02Bh, PORTC.PODR 0008 C02Ch, PORTD.PODR 0008 C02Dh, PORTE.PODR 0008 C02Eh, PORTJ.PODR 0008 C032h Value after reset: Bit b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 Symbol Bit Name Description R/W Holds output data.
RX23W Group 21.3.3 21. I/O Ports Port Input Data Register (PIDR) Address(es): PORT0.PIDR 0008 C040h, PORT1.PIDR 0008 C041h, PORT2.PIDR 0008 C042h, PORT3.PIDR 0008 C043h, PORT4.PIDR 0008 C044h, PORTB.PIDR 0008 C04Bh, PORTC.PIDR 0008 C04Ch, PORTD.PIDR 0008 C04Dh, PORTE.PIDR 0008 C04Eh, PORTJ.
RX23W Group 21.3.4 21. I/O Ports Port Mode Register (PMR) Address(es): PORT0.PMR 0008 C060h, PORT1.PMR 0008 C061h, PORT2.PMR 0008 C062h, PORT3.PMR 0008 C063h, PORT4.PMR 0008 C064h, PORTB.PMR 0008 C06Bh, PORTC.PMR 0008 C06Ch, PORTD.PMR 0008 C06Dh, PORTE.PMR 0008 C06Eh, PORTJ.PMR 0008 C072h Value after reset: Bit b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 Symbol Bit Name Description 0: Use pin as general I/O port.
RX23W Group 21.3.5 21. I/O Ports Open Drain Control Register 0 (ODR0) Address(es): PORT2.ODR0 0008 C084h, PORT3.ODR0 0008 C086h, PORTB.ODR0 0008 C096h, PORTC.ODR0 0008 C098h, PORTE.ODR0 0008 C09Ch, PORTJ.ODR0 0008 C0A4h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 B0 Pm0 Output Type Select 0: CMOS output 1: N-channel open-drain R/W b1 B1 Reserved This bit is read as 0.
RX23W Group 21.3.6 21. I/O Ports Open Drain Control Register 1 (ODR1) Address(es): PORT1.ODR1 0008 C083h, PORT2.ODR1 0008 C085h, PORT3.ODR1 0008 C087h, PORTB.ODR1 0008 C097h, PORTC.ODR1 0008 C099h, PORTE.ODR1 0008 C09Dh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 B0 Pm4 Output Type Select 0: CMOS output 1: N-channel open-drain R/W b1 B1 Reserved This bit is read as 0.
RX23W Group 21.3.7 21. I/O Ports Pull-Up Control Register (PCR) Address(es): PORT0.PCR 0008 C0C0h, PORT1.PCR 0008 C0C1h, PORT2.PCR 0008 C0C2h, PORT3.PCR 0008 C0C3h, PORT4.PCR 0008 C0C4h, PORTB.PCR 0008 C0CBh, PORTC.PCR 0008 C0CCh, PORTD.PCR 0008 C0CDh, PORTE.PCR 0008 C0CEh, PORTJ.PCR 0008 C0D2h Value after reset: Bit b7 b6 b5 b4 b3 b2 b1 b0 B7 B6 B5 B4 B3 B2 B1 B0 0 0 0 0 0 0 0 0 Symbol Bit Name Description R/W 0: Disables an input pull-up resistor.
RX23W Group 21.3.8 21. I/O Ports Drive Capacity Control Register (DSCR) Address(es): PORT1.DSCR 0008 C0E1h, PORT2.DSCR 0008 C0E2h, PORT3.DSCR 0008 C0E3h, PORTB.DSCR 0008 C0EBh, PORTC.DSCR 0008 C0ECh, PORTD.DSCR 0008 C0EDh, PORTE.DSCR 0008 C0EEh, PORTJ.
RX23W Group 21.4 21. I/O Ports Initialization of the Port Direction Register (PDR) Initialize reserved bits in the PDR register according to Table 21.3 and Table 21.4. • The blank columns in Table 21.3 and Table 21.4 indicate the bits corresponding to the pins listed in Table 21.1, Specifications of I/O Ports. The corresponding bits should be set to 1 (output) or 0 (input) depending on the user system. However, the PORT3.PDR.B5 bit of the input-only P35 pin is reserved.
RX23W Group 21.5 21. I/O Ports Handling of Unused Pins The configuration of unused pins is listed in Table 21.5. Table 21.5 Unused Pin Configuration Pin Name Description VBATT Connect this pin to VCC. MD (Always used as mode pins) RES# Connect this pin to VCC via a pull-up resistor. P35/NMI Connect this pin to VCC via a pull-up resistor. USB0_DM, USB0_DP Leave this pin open. P36/EXTAL When the main clock is not used, set the MOSCCR.MOSTP bit to 1 (general port P36).
RX23W Group 22. Multi-Function Pin Controller (MPC) 22. Multi-Function Pin Controller (MPC) 22.1 Overview The multi-function pin controller (MPC) is used to allocate input and output signals for peripheral modules and input interrupt signals to pins from among multiple ports. Table 22.1 shows the allocation of pin functions to multiple pins. The symbols and × in the table indicate whether the pins are or are not present on the given package.
RX23W Group Table 22.1 22.
RX23W Group Table 22.1 22.
RX23W Group Table 22.1 22.
RX23W Group Table 22.1 22. Multi-Function Pin Controller (MPC) Allocation of Pin Functions to Multiple Pins (5/6) Package Module/Function Channel SD host interface USB 2.
RX23W Group Table 22.1 22.
RX23W Group 22.2 22. Multi-Function Pin Controller (MPC) Register Descriptions Registers and bits for pins that are not present due to differences according to the package are reserved. Write the value after a reset when writing to such bits. 22.2.1 Write-Protect Register (PWPR) Address(es): 0008 C11Fh b7 b6 B0WI PFSWE Value after reset: 1 0 b5 b4 b3 b2 b1 b0 — — — — — — 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b5 to b0 — Reserved These bits are read as 0.
RX23W Group 22.2.2 22. Multi-Function Pin Controller (MPC) P0n Pin Function Control Register (P0nPFS) (n = 3, 5, 7) Address(es): P03PFS 0008 C143h, P05PFS 0008 C145h, P07PFS 0008 C147h Value after reset: b7 b6 b5 ASEL — — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below.
RX23W Group 22.2.3 22. Multi-Function Pin Controller (MPC) P1n Pin Function Control Registers (P1nPFS) (n = 4 to 7) Address(es): P14PFS 0008 C14Ch, P15PFS 0008 C14Dh, P16PFS 0008 C14Eh, P17PFS 0008 C14Fh Value after reset: b7 b6 b5 ASEL ISEL — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below.
RX23W Group 22.2.4 22. Multi-Function Pin Controller (MPC) P2n Pin Function Control Register (P2nPFS) (n = 1, 2, 5 to 7) Address(es): P21PFS 0008 C151h, P22PFS 0008 C152h, P25PFS 0008 C155h, P26PFS 0008 C156h, P27PFS 0008 C157h Value after reset: b7 b6 b5 ASEL — — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below.
RX23W Group 22.2.5 22. Multi-Function Pin Controller (MPC) P3n Pin Function Control Registers (P3nPFS) (n = 0, 1) Address(es): P30PFS 0008 C158h, P31PFS 0008 C159h Value after reset: b7 b6 b5 — ISEL — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below. R/W b5 — Reserved This bit is read as 0.
RX23W Group 22.2.6 22. Multi-Function Pin Controller (MPC) P4n Pin Function Control Registers (P4nPFS) (n = 0 to 7) Address(es): P40PFS 0008 C160h, P41PFS 0008 C161h, P42PFS 0008 C162h, P43PFS 0008 C163h, P44PFS 0008 C164h, P45PFS 0008 C165h, P46PFS 0008 C166h, P47PFS 0008 C167h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ASEL — — — — — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b6 to b0 b7 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 22.2.7 22. Multi-Function Pin Controller (MPC) PBn Pin Function Control Registers (PBnPFS) (n = 0, 1, 3, 5, 7) Address(es): PB0PFS 0008 C198h, PB1PFS 0008 C199h, PB3PFS 0008 C19Bh, PB5PFS 0008 C19Dh, PB7PFS 0008 C19Fh Value after reset: b7 b6 b5 — ISEL — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below.
RX23W Group 22.2.8 22. Multi-Function Pin Controller (MPC) PCn Pin Function Control Registers (PCnPFS) (n = 0, 2 to 7) Address(es): PC0PFS 0008 C1A0h, PC2PFS 0008 C1A2h, PC3PFS 0008 C1A3h, PC4PFS 0008 C1A4h, PC5PFS 0008 C1A5h, PC6PFS 0008 C1A6h, PC7PFS 0008 C1A7h Value after reset: b7 b6 b5 — — — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function.
RX23W Group 22.2.9 22. Multi-Function Pin Controller (MPC) PDn Pin Function Control Registers (PDnPFS) (n = 3) Address(es): PD3PFS 0008 C1ABh Value after reset: b7 b6 b5 ASEL ISEL — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below. R/W b6, b5 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 22.2.10 22. Multi-Function Pin Controller (MPC) PEn Pin Function Control Registers (PEnPFS) (n = 0 to 4) Address(es): PE0PFS 0008 C1B0h, PE1PFS 0008 C1B1h, PE2PFS 0008 C1B2h, PE3PFS 0008 C1B3h, PE4PFS 0008 C1B4h Value after reset: b7 b6 b5 ASEL ISEL — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below.
RX23W Group Table 22.12 22. Multi-Function Pin Controller (MPC) Register Settings for Input/Output Pin Function in 56-Pin Pin PSEL[4:0] Settings PE2 PE3 PE4 00000b (initial value) Hi-Z 00001b MTIOC4A MTIOC4B MTIOC4D 00010b — — MTIOC1A 00111b — POE8# — 01001b — CLKOUT CLKOUT 10111b — AUDIO_MCLK — —: Do not specify this value. R01UH0823EJ0110 Rev.1.
RX23W Group 22.2.11 22. Multi-Function Pin Controller (MPC) PJn Pin Function Control Registers (PJnPFS) (n = 3) Address(es): PJ3PFS 0008 C1D3h Value after reset: b7 b6 b5 — — — 0 0 0 b4 b3 b2 b1 b0 0 0 PSEL[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 PSEL[4:0] Pin Function Select These bits select the peripheral function. For individual pin functions, see the tables below. R/W b7 to b5 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 22.3 22.3.1 22. Multi-Function Pin Controller (MPC) Usage Notes Procedure for Specifying Input/Output Pin Function Use the following procedure to specify the input/output pin functions. (1) Clear the port mode register (PMR) to 0 to select the general I/O port function. (2) Specify the assignments of input/output signals for peripheral functions to the desired pins. (3) Enable writing to the Pmn pin function control register (PmnPFS) through the write-protect register (PWPR) setting.
RX23W Group Table 22.14 22. Multi-Function Pin Controller (MPC) Register Settings PmnPFS Item PMR.Bn PDR.Bn ASEL After a reset 0 0 0 ISEL 0 PSEL[4:0] 00000b Point to Note General input ports 0 0 0 0/1 x General output ports 0 1 0 0 x Peripheral functions 1 x 0 0/1 Peripheral functions (see Table 22.2 to Table 22.13) Interrupt inputs 0 0 0 1 x NMI x x x x*1 x Register settings are not required.
RX23W Group 23. 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Multi-Function Timer Pulse Unit 2 (MTU2a) In this section, “PCLK” is used to refer to PCLKA. 23.1 Overview This MCU has an on-chip multi-function timer pulse unit 2 (MTU). Each unit comprises a 16-bit timer with five channels (MTU0 to MTU4). Table 23.1 lists the specifications of the MTU, and Table 23.2 lists the functions of the MTU. Figure 23.1 shows a block diagram of the MTU. Table 23.
RX23W Group Table 23.2 23.
RX23W Group Table 23.2 23.
Interrupt request signals TGRD TADCOBRB TGRD TGRB TADCORB TADCOBRA TGRB TGRC TCBR TITCR TDDR TITCNT TBTER TGRC TADCORA TCNT TCNT TADCR TGRA TCDR TDER TOLBR TGCR TCNTS TWCR TGRA TIORH TIORL TIER TSR TBTM TIORH TIORL TIER TSR TBTM TOCR1 TOER TOCR2 MTU3: MTIOC3A MTIOC3B MTIOC3C MTIOC3D MTU4: MTIOC4A MTIOC4B MTIOC4C MTIOC4D MTU4 TCR TMDR I/O pins MTU3 TCR TMDR 23.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.3 lists the I/O pins to be used by the MTU. Table 23.
RX23W Group 23.2 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Register Descriptions 23.2.1 Timer Control Register (TCR) Address(es): MTU0.TCR 000D 0B00h, MTU1.TCR 000D 0B80h, MTU2.TCR 000D 0C00h, MTU3.TCR 000D 0A00h, MTU4.TCR 000D 0A01h b7 b6 b5 CCLR[2:0] Value after reset: 0 0 b4 b3 b2 CKEG[1:0] 0 0 0 b1 b0 TPSC[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 TPSC[2:0] Time Prescaler Select Refer to Table 23.6 to Table 23.9.
RX23W Group Table 23.4 Channel 23.
RX23W Group Table 23.7 Channel 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TPSC[2:0] (MTU1) Bit 2 Bit 1 Bit 0 TPSC[2] TPSC[1] TPSC[0] MTU1 Note: 0 0 0 Internal clock: counts on PCLK/1 0 0 1 Internal clock: counts on PCLK/4 0 1 0 Internal clock: counts on PCLK/16 0 1 1 Internal clock: counts on PCLK/64 1 0 0 External clock: counts on MTCLKA pin input 1 0 1 External clock: counts on MTCLKB pin input 1 1 0 Internal clock: counts on PCLK/256 1 1 1 Counts on MTU2.
RX23W Group 23.2.2 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Mode Register (TMDR) Address(es): MTU0.TMDR 000D 0B01h, MTU1.TMDR 000D 0B81h, MTU2.TMDR 000D 0C01h, MTU3.TMDR 000D 0A02h, MTU4.TMDR 000D 0A03h b7 b6 b5 b4 — BFE BFB BFA 0 0 0 0 Value after reset: b3 b2 b1 b0 MD[3:0] 0 0 0 0 Bit Symbol Bit Name Description R/W b3 to b0 MD[3:0] Mode Select These bits specify the timer operating mode. Refer to Table 23.10 for details.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) BFA Bit (Buffer Operation A) This bit specifies normal operation for the TGRA register or buffered operation of the combination of registers TGRA and TGRC. When the TGRC register is used as a buffer register, the TGRC input capture/output compare does not take place in modes other than complementary PWM mode, but compare match with the TGRC register occurs in complementary PWM mode.
RX23W Group 23.2.3 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer I/O Control Register (TIOR) • MTU0.TIORH, MTU1.TIOR, MTU2.TIOR, MTU3.TIORH, MTU4.TIORH Address(es): MTU0.TIORH 000D 0B02h, MTU1.TIOR 000D 0B82h, MTU2.TIOR 000D 0C02h, MTU3.TIORH 000D 0A04h, MTU4.TIORH 000D 0A06h b7 b6 b5 b4 b3 IOB[3:0] Value after reset: 0 0 b2 b1 b0 IOA[3:0] 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b3 to b0 IOA[3:0] I/O Control A Refer to the following tables.*1 MTU0.TIORH: Table 23.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) The MTU has a total of seven TIOR registers, one for MTU0, MTU1, and MTU2, two each for MTU3, and MTU4. The TIOR register should be set when the TMDR register is set to select normal mode, PWM mode, or phase counting mode. The initial output specified by the TIOR register is valid when the counter is stopped (the TSTR.CSTn bit is set to 0). Note also that, in PWM mode 2, the output at the point at which the counter is set to 0 is specified.
RX23W Group Table 23.12 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TIOR (MTU1) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU1.TGRB Function MTIOC1B Pin Function 0 0 0 0 Output compare register Output prohibited 0 0 0 1 Initial output is low. Low output at compare match. 0 0 1 0 Initial output is low. High output at compare match. 0 0 1 1 Initial output is low. Toggle output at compare match.
RX23W Group Table 23.13 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TIOR (MTU2) Bit 7 Bit 6 Bit 5 Bit 4 Description IOB[3] IOB[2] IOB[1] IOB[0] MTU2.TGRB Function MTIOC2B Pin Function 0 0 0 0 Output compare register Output prohibited 0 0 0 1 Initial output is low. Low output at compare match. 0 0 1 0 Initial output is low. High output at compare match. 0 0 1 1 Initial output is low. Toggle output at compare match.
RX23W Group Table 23.15 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TIORL (MTU3) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD[3] IOD[2] IOD[1] IOD[0] MTU3.TGRD Function MTIOC3D Pin Function 0 0 0 0 Output compare register*1 Output prohibited 0 0 0 1 Initial output is low. Low output at compare match. 0 0 1 0 Initial output is low. High output at compare match. 0 0 1 1 Initial output is low. Toggle output at compare match.
RX23W Group Table 23.17 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TIORL (MTU4) Bit 7 Bit 6 Bit 5 Bit 4 Description IOD[3] IOD[2] IOD[1] IOD[0] MTU4.TGRD Function MTIOC4D Pin Function 0 0 0 0 Output compare register*1 Output prohibited 0 0 0 1 Initial output is low. Low output at compare match. 0 0 1 0 Initial output is low. High output at compare match. 0 0 1 1 Initial output is low. Toggle output at compare match.
RX23W Group Table 23.19 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TIORL (MTU0) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] MTU0.TGRC Function MTIOC0C Pin Function 0 0 0 0 Output compare register*1 Output prohibited 0 0 0 1 Initial output is low. Low output at compare match. 0 0 1 0 Initial output is low. High output at compare match. 0 0 1 1 Initial output is low. Toggle output at compare match.
RX23W Group Table 23.21 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TIOR (MTU2) Bit 3 Bit 2 Bit 1 Bit 0 Description IOA[3] IOA[2] IOA[1] IOA[0] MTU2.TGRA Function MTIOC2A Pin Function 0 0 0 0 Output compare register Output prohibited 0 0 0 1 Initial output is low. Low output at compare match. 0 0 1 0 Initial output is low. High output at compare match. 0 0 1 1 Initial output is low. Toggle output at compare match.
RX23W Group Table 23.23 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TIORL (MTU3) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] MTU3.TGRC Function MTIOC3C Pin Function 0 0 0 0 Output compare register*1 Output prohibited 0 0 0 1 Initial output is low. Low output at compare match. 0 0 1 0 Initial output is low. High output at compare match. 0 0 1 1 Initial output is low. Toggle output at compare match.
RX23W Group Table 23.25 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TIORL (MTU4) Bit 3 Bit 2 Bit 1 Bit 0 Description IOC[3] IOC[2] IOC[1] IOC[0] MTU4.TGRC Function MTIOC4C Pin Function 0 0 0 0 Output compare register*1 Output prohibited 0 0 0 1 Initial output is low. Low output at compare match. 0 0 1 0 Initial output is low. High output at compare match. 0 0 1 1 Initial output is low. Toggle output at compare match.
RX23W Group 23.2.4 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Interrupt Enable Register (TIER) • MTU0.TIER, MTU3.TIER Address(es): MTU0.TIER 000D 0B04h, MTU3.TIER 000D 0A08h Value after reset: b7 b6 b5 TTGE — — 0 0 0 b4 b3 b2 b1 b0 TCIEV TGIED TGIEC TGIEB TGIEA 0 0 0 0 0 b1 b0 • MTU1.TIER, MTU2.TIER Address(es): MTU1.TIER 000D 0B84h, MTU2.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TGIEA and TGIEB Bits (TGR Interrupt Enable A and B) Each bit enables or disables interrupt requests (TGIm) (m = A, B). TGIEC and TGIED Bits (TGR Interrupt Enable C and D) Each bit enables or disables interrupt requests (TGIm) in MTU0, MTU3, and MTU4 (m = C, D). In MTU1 and MTU2, these bits are reserved. They are read as 0. The write value should be 0. TCIEV Bit (Overflow Interrupt Enable) This bit enables or disables interrupt requests (TCIV).
RX23W Group 23.2.5 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Status Register (TSR) Address(es): MTU0.TSR 000D 0B05h, MTU1.TSR 000D 0B85h, MTU2.TSR 000D 0C05h, MTU3.TSR 000D 0A2Ch, MTU4.TSR 000D 0A2Dh b7 b6 b5 b4 b3 b2 b1 b0 TCFD — — — — — — — 1 1 x x x x x x Value after reset: x: Undefined Bit Symbol Bit Name Description R/W b5 to b0 — Reserved These bits are read as undefined. The write value should be 1. R/W b6 — Reserved This bit is read as 1.
RX23W Group 23.2.6 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Buffer Operation Transfer Mode Register (TBTM) • MTU0.TBTM Address(es): MTU0.TBTM 000D 0B26h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — TTSE TTSB TTSA 0 0 0 0 0 0 0 0 • MTU3.TBTM, MTU4.TBTM Address(es): MTU3.TBTM 000D 0A38h, MTU4.
RX23W Group 23.2.7 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Input Capture Control Register (TICCR) Address(es): MTU1.TICCR 000D 0B90h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — I2BE I2AE I1BE I1AE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 I1AE Input Capture Enable 0: Does not include the MTIOC1A pin in the MTU2.TGRA input capture conditions 1: Includes the MTIOC1A pin in the MTU2.
RX23W Group 23.2.8 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer A/D Converter Start Request Control Register (TADCR) Address(es): MTU4.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Table 23.26 Bit 15 Setting of Transfer Timing by TADCR.BF[1:0] Bits Bit 14 Description BF[1] BF[0] In Complementary PWM Mode In Reset-Synchronized PWM Mode In PWM Mode 1 In Normal Mode 0 0 Data is not transferred from the cycle set buffer register (MTU4.TADCOBRA, MTU4.TADCOBRB) to the cycle set register (MTU4.TADCORA, MTU4.TADCORB). Data is not transferred from the cycle set buffer register (MTU4.TADCOBRA, MTU4.
RX23W Group 23.2.10 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer A/D Converter Start Request Cycle Set Buffer Registers A and B (TADCOBRA and TADCOBRB) Address(es): MTU4.TADCOBRA 000D 0A48h, MTU4.TADCOBRB 000D 0A4Ah Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: MTU4.TADCOBRA and MTU4.TADCOBRB must not be accessed in 8-bit units; they should be accessed in 16bit units.
RX23W Group 23.2.12 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer General Register (TGR) Address(es): MTU0.TGRA 000D 0B08h, MTU0.TGRB 000D 0B0Ah, MTU0.TGRC 000D 0B0Ch, MTU0.TGRD 000D 0B0Eh, MTU0.TGRE 000D 0B20h, MTU0.TGRF 000D 0B22h, MTU1.TGRA 000D 0B88h, MTU1.TGRB 000D 0B8Ah, MTU2.TGRA 000D 0C08h, MTU2.TGRB 000D 0C0Ah, MTU3.TGRA 000D 0A18h, MTU3.TGRB 000D 0A1Ah, MTU3.TGRC 000D 0A24h, MTU3.TGRD 000D 0A26h, MTU4.TGRA 000D 0A1Ch, MTU4.TGRB 000D 0A1Eh, MTU4.TGRC 000D 0A28h, MTU4.
RX23W Group 23.2.13 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Start Register (TSTR) Address(es): MTU.TSTR 000D 0A80h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 CST4 CST3 — — — CST2 CST1 CST0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 CST0 Counter Start 0 0: MTU0.TCNT performs count stop 1: MTU0.TCNT performs count operation R/W b1 CST1 Counter Start 1 0: MTU1.TCNT performs count stop 1: MTU1.
RX23W Group 23.2.14 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Synchronous Register (TSYR) Address(es): MTU.TSYR 000D 0A81h b7 b6 SYNC4 SYNC3 Value after reset: 0 0 b5 b4 b3 — — — 0 0 0 b2 b1 b0 SYNC2 SYNC1 SYNC0 0 0 0 Bit Symbol Bit Name Description R/W b0 SYNC0 Timer Synchronous Operation 0 0: MTU0.TCNT operates independently (TCNT setting/clearing is not related to other channels) 1: MTU0.TCNT performs synchronous operation.
RX23W Group 23.2.15 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Read/Write Enable Register (TRWER) Address(es): MTU.TRWER 000D 0A84h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — RWE 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R/W b0 RWE Read/Write Enable 0: Read/write access to the registers is disabled 1: Read/write access to the registers is enabled R/W b7 to b1 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 23.2.16 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Output Master Enable Register (TOER) Address(es): MTU.
RX23W Group 23.2.17 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Output Control Register 1 (TOCR1) Address(es): MTU.TOCR1 000D 0A0Eh Value after reset: Bit b0 b7 b6 b5 b4 b3 b2 b1 b0 — PSYE — — TOCL TOCS OLSN OLSP 0 0 0 0 0 0 0 0 Symbol OLSP Bit Name Description R/W Output Level Select P *2,*3 Refer to Table 23.27. R/W N *2,*3 b1 OLSN Output Level Select Refer to Table 23.28.
RX23W Group Table 23.27 Bit 0 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Output Level Select Function Function Compare Match Output OLSP Initial Output Active Level Up-Counting Down-Counting 0 High Low Low High 1 Low High High Low Table 23.
RX23W Group 23.2.18 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Output Control Register 2 (TOCR2) Address(es): MTU.TOCR2 000D 0A0Fh b7 b6 BF[1:0] Value after reset: 0 b5 b4 b3 b2 b1 b0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 OLS1P Output Level Select 1P*1, *2 This bit selects the output level on MTIOC3B in reset-synchronized PWM mode and complementary PWM mode. Refer to Table 23.29.
RX23W Group Table 23.31 Bit 2 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTIOC4A Output Level Select Function Function Compare Match Output OLS2P Initial Output Active Level Up-Counting Down-Counting 0 High Low Low High 1 Low High High Low Table 23.
RX23W Group 23.2.19 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Output Level Buffer Register (TOLBR) Address(es): MTU.TOLBR 000D 0A36h Value after reset: b7 b6 — — 0 0 b5 b4 b3 b2 b1 b0 OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 OLS1P Output Level Select 1P Specify the buffer value to be transferred to the OLS1P bit in TOCR2.
RX23W Group 23.2.20 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Gate Control Register (TGCR) Address(es): MTU.TGCR 000D 0A0Dh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — BDC N P FB WF VF UF 1 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 UF Output Phase Switch R/W b1 VF b2 WF These bits turn on or off the positive-phase/negative-phase output. The setting of these bits is valid only when the TGCR.FB bit is set to 1.
RX23W Group Table 23.36 Bit 2 23.
RX23W Group 23.2.23 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Cycle Data Register (TCDR) Address(es): MTU.TCDR 000D 0A14h Value after reset: Note: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 The TCDR registers must not be accessed in 8-bit units; they should be accessed in 16-bit units. The TCDR register specifies the count value to switch the count direction of the TCNTS counter.
RX23W Group 23.2.25 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Interrupt Skipping Set Register (TITCR) Address(es): MTU.TITCR 000D 0A30h b7 b6 T3AEN Value after reset: b5 b4 T3ACOR[2:0] 0 0 0 b3 b2 T4VEN 0 0 b1 b0 T4VCOR[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 T4VCOR[2:0] TCIV4 Interrupt Skipping Count Setting These bits specify the TCIV4 interrupt skipping count within the range from 0 to 7.*1 For details, refer to Table 23.37.
RX23W Group 23.2.26 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Interrupt Skipping Counter (TITCNT) Address(es): MTU.TITCNT 000D 0A31h b7 b6 — Value after reset: 0 b5 b4 T3ACNT[2:0] 0 0 b3 b2 b1 — 0 0 b0 T4VCNT[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 T4VCNT[2:0] TCIV4 Interrupt Counter While the T4VEN bit in TITCR is set to 1, the count in these bits is incremented every time a TCIV4 interrupt source occurs. R b3 — Reserved This bit is read as 0.
RX23W Group 23.2.27 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Buffer Transfer Set Register (TBTER) Address(es): MTU.
RX23W Group 23.2.28 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Dead Time Enable Register (TDER) Address(es): MTU.TDER 000D 0A34h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — TDER 0 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R/W b0 TDER Dead Time Enable 0: No dead time is generated 1: Dead time is generated*1 R/(W) b7 to b1 — Reserved These bits are read as 0. The write value should be 0. R/W Note 1. TDDR must be set to 1 or a larger value.
RX23W Group 23.2.29 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer Waveform Control Register (TWCR) Address(es): MTU.TWCR 000D 0A60h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 CCE — — — — — — WRE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 WRE Initial Output Inhibition Enable 0: Initial value specified in TOCR is output 1: Initial output is inhibited R/(W) *1 b6 to b1 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 23.2.30 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Noise Filter Control Registers (NFCR) Address(es): MTU0.NFCR 000D 0A90h, MTU1.NFCR 000D 0A91h, MTU2.NFCR 000D 0A92h, MTU3.NFCR 000D 0A93h, MTU4.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) NFCS[1:0] Bits (Noise Filter Clock Select) These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the selected sampling interval before setting the input-capture function. When the NFCS[1:0] bits are set to 11b, selecting the external clock as the source to drive counting, wait for two cycles of the external clock before setting the inputcapture function. 23.2.
RX23W Group 23.3 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operation 23.3.1 Basic Functions Each channel has the TCNT counter and the TGR register. The TCNT counter performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR register can be used as an input capture register or an output compare register.
RX23W Group (b) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the MTU’s TCNT counters are all designated as free-running counters. When the relevant CSTn bit in the TSTR register is set to 1, the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from FFFFh to 0000h), the MTU requests an interrupt if the corresponding TCIEV bit in the TIER register is 1.
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Waveform Output by Compare Match The MTU can output low or high or toggle output from the corresponding output pin using compare match. (a) Example of Procedure for Setting Waveform Output by Compare Match Figure 23.7 shows an example of the procedure for setting waveform output by compare match.
RX23W Group (b) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Examples of Waveform Output Operation Figure 23.8 shows an example of low output and high output. In this example, the TCNT counter has been designated as a free-running counter, and settings have been made so that high is output by compare match A and low is output by compare match B. When the pin level is the same as the specified level, the pin level does not change.
RX23W Group (3) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Input Capture Function The TCNT value can be transferred to the TGR register on detection of the input edge of the MTIOCnm (n = 0 to 4; m = A to D) pin. The rising edge, falling edge, or both edges can be selected as the detection edge. For MTU0 and MTU1, another channel’s count clock or compare match signal can also be specified as the input capture source.
RX23W Group (b) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Input Capture Operation Figure 23.11 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the MTIOCnA pin input capture input edge, the falling edge has been selected as the MTIOCnB pin input capture input edge, and counter clearing by the TGRB input capture has been designated for the TCNT counter.
RX23W Group 23.3.2 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous Operation In synchronous operation, the values in multiple TCNT counters can be modified simultaneously (synchronous setting). In addition, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in the TCR register. Synchronous operation increases the number of the TGR registers assigned to a single time base. MTU0 to MTU4 can all be designated for synchronous operation.
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Synchronous Operation Figure 23.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for MTU0 to MTU2, compare match of the MTU0.TGRB register has been set as the counter clearing source in MTU0, and synchronous clearing has been set for the counter clearing source in MTU1 and MTU2. Three-phase PWM waveforms are output from pins MTIOC0A, MTIOC1A, and MTIOC2A.
RX23W Group 23.3.3 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Buffer Operation Buffer operation, provided for MTU0, MTU3, and MTU4, enables registers TGRC and TGRD to be used as buffer registers. In MTU0, TGRF register can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Note: MTU0.
RX23W Group (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Buffer Operation Setting Procedure Figure 23.16 shows an example of the buffer operation setting procedure. [1] Designate the TGR register as an input capture Buffer operation register or output compare register by means of the TIOR register. Select TGR function [1] [2] Designate the TGR register for buffer operation with TMDR.BFA bit, TMDR.BFB bit, and TMDR.BFE bit. Set buffer operation [2] [3] Set the TSTR.
RX23W Group (b) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) When TGR register is an Input Capture Register Figure 23.18 shows an operation example in which the TGRA register has been designated as an input capture register, and buffer operation has been designated for registers TGRA and TGRC. Counter clearing by TGRA input capture has been set for the TCNT counter, and both rising and falling edges have been selected as the MTIOCnA pin input capture input edge.
RX23W Group (3) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for MTU0 or in PWM mode 1 for MTU3 and MTU4 by setting the timer buffer operation transfer mode registers (MTU0.TBTM, MTU3.TBTM, and MTU4.TBTM).
RX23W Group 23.3.4 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Cascaded Operation In cascaded operation, 16-bit counters in different two channels are used together as a 32-bit counter. This function works when overflow/underflow of the MTU2.TCNT counter is selected as the count clock for MTU1 through the TCR.TPSC[2:0] bits. Underflow occurs only when the lower 16 bits of the TCNT counter is in phase counting mode. Table 23.41 lists the register combinations used in cascaded operation.
RX23W Group (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Cascaded Operation Setting Procedure Figure 23.20 shows an example of the cascaded operation setting procedure. [1] Set the MTU1.TCR.TPSC[2:0] bits to 111b to select MTU2.TCNT overflow/underflow counting. Cascaded operation Set cascading [1] Start count [2] [2] Set the TSTR.CSTn bit for the upper and lower channels to 1 to start the count operation. Cascaded operation Figure 23.
RX23W Group (3) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Cascaded Operation Example (b) Figure 23.22 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected the MTIOC1A rising edge for the input capture timing while the MTU2.TIOR.
RX23W Group (4) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Cascaded Operation Example (c) Figure 23.23 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the I2AE and I1AE bits in TICCR register have been set to 1 to include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA input capture conditions, respectively. In this example, the IOA[3:0] bits in both MTU1.TIOR and MTU2.
RX23W Group (5) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Cascaded Operation Example (d) Figure 23.24 illustrates the operation when counters MTU1.TCNT and MTU2.TCNT have been cascaded and the TICCR.I2AE bit has been set to 1 to include the MTIOC2A pin in the MTU1.TGRA input capture conditions. In this example, the MTU1.TIOR.IOA[3:0] bits have selected occurrence of MTU0.TGRA compare match or input capture for the input capture timing while the MTU2.TIOR.
RX23W Group 23.3.5 23. Multi-Function Timer Pulse Unit 2 (MTU2a) PWM Modes PWM modes are provided to output PWM waveforms from the external pins. The output level can be selected as low, high, or toggle output in response to a compare match of each TGR register. PWM waveforms in the range of 0% to 100% duty cycle can be output according to the TGR settings. By designating TGR compare match as the counter clearing source, the PWM cycle can be specified in that register.
RX23W Group (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of PWM Mode Setting Procedure Figure 23.25 shows an example of the PWM mode setting procedure. [1] Enable TOER output when outputting a waveform from the MTIOC pin of MTU3 and MTU4. PWM mode Enable waveform output [1] Select count clock [2] [2] Set the TCR.TPSC[2:0] bits to select the count clock source. At the same time, set the TCR.CKEG[1:0] bits to select the clock edge. [3] Set the TCR.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Figure 23.27 shows an example of operation in PWM mode 2. In this example, synchronous operation is designated for MTU0 and MTU1, MTU1.TGRB compare match is set as the TCNT clearing source, and a low level is set as the initial output value and a high level as the output value for the other TGR registers (MTU0.TGRA to MTU0.TGRC and MTU1.TGRA), outputting 4-phase PWM waveforms. In this case, the value set in the MTU1.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Figure 23.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode 1. In this example, TGRA compare match is set as the TCNT clearing source, a low level is set as the initial output value and output value for the TGRA register, and a high level is set as the output value for the TGRB register. (1) Example of operation to output the PWM waveform with 0% duty.
RX23W Group 23.3.6 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Phase Counting Mode When phase counting mode is specified, an external clock is selected as the count clock and the TCNT counter operates as an up-counter/down-counter regardless of the setting of the TCR.TPSC[2:0] bits and TCR.CKEG[1:0] bits. However, the functions of the TCR.CCLR[2:0] bits and of registers TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used.
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Examples of Phase Counting Mode Operation In phase counting mode, the TCNT counter is incremented or decremented according to the phase difference between two external clocks. There are four modes according to the count conditions. (a) Phase Counting Mode 1 Figure 23.30 shows an example of operation in phase counting mode 1, and Table 23.45 lists the TCNT up-counting and down-counting conditions.
RX23W Group (b) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Phase Counting Mode 2 Figure 23.31 shows an example of operation in phase counting mode 2, and Table 23.46 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Up-counting Down-counting Time Figure 23.31 Table 23.
RX23W Group (c) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Phase Counting Mode 3 Figure 23.32 shows an example of operation in phase counting mode 3, and Table 23.47 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Down-counting Up-counting Time Figure 23.32 Table 23.
RX23W Group (d) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Phase Counting Mode 4 Figure 23.33 shows an example of operation in phase counting mode 4, and Table 23.48 lists the TCNT up-counting and down-counting conditions. MTCLKA (MTU1) MTCLKC (MTU2) MTCLKB (MTU1) MTCLKD (MTU2) TCNT value Down-counting Up-counting Time Figure 23.33 Table 23.
RX23W Group (3) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Phase Counting Mode Application Example Figure 23.34 shows an example in which MTU1 is in phase counting mode, and MTU1 is coupled with MTU0 to input 2-phase encoder pulses of a servo motor in order to detect position or speed. MTU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to MTCLKA and MTCLKB. MTU0.TGRC compare match is specified as the MTU0.TCNT clearing source and registers MTU0.TGRA and MTU0.
RX23W Group 23.3.7 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, six phases of positive and negative PWM waveforms that share a common wave transition point can be output by combining MTU3 and MTU4. When set for reset-synchronized PWM mode, the MTIOC3B, MTIOC3D, MTIOC4A, MTIOC4C, MTIOC4B, and MTIOC4D pins function as PWM output pins and the MTU3.TCNT counter functions as an up-counter. Table 23.49 lists the PWM output pins. Table 23.
RX23W Group (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Procedure for Setting Reset-Synchronized PWM Mode Figure 23.35 shows an example of procedure for setting the reset-synchronized PWM mode. Reset-synchronized PWM mode Stop count operation [1] PFS setting [2] Select count clock and counter clear source [3] Brushless DC motor control setting [1] Set the CST3 and CST4 bits in the TSTR register to 0 to stop the TCNT operation. Specify the reset-synchronized PWM mode while MTU3.
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Reset-Synchronized PWM Mode Operation Figure 23.36 shows an example of operation in the reset-synchronized PWM mode. Counters MTU3.TCNT and MTU4.TCNT operate as up-counters. The counters are cleared when a compare match occurs between the MTU3.TCNT counter and the MTU3.TGRA register, and then begin incrementing from 0000h. The output from the PWM pins toggles every time a compare match occurs in registers MTU3.TGRB, MTU4.
RX23W Group 23.3.8 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Complementary PWM Mode In complementary PWM mode, dead time can be set for PWM waveforms to be output. The dead time is the period during which the upper and lower arm transistors are set to the inactive level in order to prevent short-circuiting of the arms. Six phases of positive and negative PWM waveforms with dead time can be output by combining MTU3 and MTU4. PWM waveforms without dead time can also be output.
TCBR MTU3.TGRA TCDR TDDR Comparator Match signal TCNTS MTU3.TCNT MTU4.TCNT MTU3.TGRD MTU4.TGRC MTU4.TGRB TEMP 3 MTU4.TGRA Match signal TEMP 2 MTU3.TGRB TEMP 1 Comparator PWM cycle output Output protection circuit MTU3.TGRC Output controller MTU4.TCNT underflow interrupt 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.
RX23W Group (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Complementary PWM Mode Setting Procedure Figure 23.38 shows an example of the complementary PWM mode setting procedure. [1] Set bits CST3 and CST4 in the TSTR register to 0 to stop TCNT operation. Specify complementary PWM mode while counters MTU3.TCNT and MTU4.TCNT are stopped. [2] Set the Pmn pin function control register and the port I/O register.
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Outline of Complementary PWM Mode Operation In complementary PWM mode, six phases (three positive and three negative) of PWM waveforms can be output. Figure 23.39 illustrates counter operation in complementary PWM mode, and Figure 23.40 shows an example of operation in complementary PWM mode. (a) Counter Operation In complementary PWM mode, three counters —MTU3.TCNT, MTU4.TCNT, and TCNTS— perform up-/down-count operations. The MTU3.
RX23W Group (b) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Register Operation In complementary PWM mode, nine registers (compare registers, buffer registers, and temporary registers) are used to control the duty ratio for the PWM output. Figure 23.40 shows an example of operation in complementary PWM mode. Registers MTU3.TGRB, MTU4.TGRA, and MTU4.TGRB are constantly compared with the counters to generate PWM waveforms. When these registers match the counter, the value set in the TOCR1.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Transfer from temporary register to compare register Transfer from temporary register to compare register Tb2 MTU3.TGRA Ta Tb1 Ta Tb2 Ta TCNTS TCDR MTU3.TCNT MTU4.TGRA MTU4.TCNT MTU4.TGRC TDDR 0000h Buffer register MTU4.TGRC 6400h 0080h Temporary register 6400h 0080h Compare register MTU4.TGRA 6400h 0080h Positive-phase output Negative-phase output Output waveform is active-low Figure 23.
RX23W Group (c) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Initial Setting In complementary PWM mode, there are six registers that require initial setting. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled). Before setting complementary PWM mode with the TMDR.MD[3:0] bits, initial values should be set in the following registers. The MTU3.TGRC register operates as the buffer register for the MTU3.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Transfer from temporary register to compare register Tb1 Ta MTU3.TGRA = TCDR + 1 Ta Tb2 Ta TCNTS TCDR MTU3.TCNT MTU4.TCNT MTU4.TGRA MTU4.TGRC TDDR = 1 0000h Buffer register MTU4.TGRC Data 1 Data 2 Temporary register Data 1 Data 2 Compare register MTU4.TGRA Data 1 Data 2 Positive-phase output Initial output Negative-phase output Initial output Output waveform is active-low Figure 23.
RX23W Group (g) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) PWM Cycle Setting In complementary PWM mode, the PWM cycle is set in two registers — the MTU3.TGRA register, in which the MTU3.TCNT counter upper limit value is set, and the TCDR register, in which the MTU4.TCNT counter upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: With dead time: MTU3.TGRA setting = TCDR setting + TDDR setting Without dead time: MTU3.
Figure 23.43 R01UH0823EJ0110 Rev.1.10 Nov 30, 2020 Data 1 Temporary register Compare register Data 1 Data 1 Ta Buffer register 0000h MTU4.TGRA MTU4.TGRC MTU3.
RX23W Group (i) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the TOCR1 register or bits OLS1N to OLS3N and OLS1P to OLS3P in the TOCR2 register. This initial output is the non-active level of the PWM output and continues from when complementary PWM mode is set with the TMDR register until the MTU4.TCNT counter exceeds the value set in the TDDR register. Figure 23.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timer output control register settings TOCR1.OLSN bit = 0 (initial output: high; active level: low) TOCR1.OLSP bit = 0 (initial output: high; active level: low) MTU3.TCNT values MTU3.TCNT MTU4.TCNT TDDR MTU4.TGRA Time Initial output Positive-phase output Negative-phase output Active level Complementary PWM mode (MTU3.TMDR setting) Figure 23.45 MTU3.
RX23W Group (j) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Method for Generating PWM Output in Complementary PWM Mode In complementary PWM mode, six phases (three positive and three negative) of PWM waveforms can be output. Dead time can be set for PWM waveforms to be output. A PWM waveform is generated by output of the level selected in the timer output control register in the event of a compare match between a counter and a compare register.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) T1 interval T2 interval T1 interval Counter for generating a turn-off timing Counter for generating a turn-on timing MTU3.TGRA TEMP2 c TCDRA MTU4.TGRA a d b a b TDDRA 0000h Don't care Positive-phase output ON OFF OFF ON OFF Negative-phase output Output waveform is active-low. Buffer operation is set for transfer at the crest and trough. Figure 23.
RX23W Group (k) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) 0% and 100% Duty Cycle Output in Complementary PWM Mode In complementary PWM mode, 0% and 100% duty cycle PWM waveforms can be output as required. Figure 23.49 to Figure 23.53 show output examples. A 100% duty cycle waveform is output when the data register value is set to 0000h. The waveform in this case has a positive phase with a 100% on-state.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) T1 interval MTU3.TGRA T2 interval c TEMP2 T1 interval d Counter for generating a turn-off timing Counter for generating a turn-on timing TCDRA a b MTU4.TGRA TDDRA 0000h Positive-phase output 0% duty cycle output Don't care OFF ON 100% duty cycle output Negative-phase output Output waveform is active-low. Buffer operation is set for transfer at the crest and trough. Figure 23.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) T1 interval T2 interval c MTU3.TGRA a d T1 interval b MTU4.TGRA Counter for generating a turn-off timing Counter for generating a turn-on timing TCDRA MTU3.TCNT MTU4.TCNT TDDRA 0000h Don't care Positive-phase output 0% duty cycle output OFF 100% duty cycle output Negative-phase output Don't care Output waveform is active-low. Buffer operation is set for transfer at the crest and trough. Figure 23.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (m) Counter Clearing by Another Channel In complementary PWM mode, counters MTU3.TCNT, MTU4.TCNT, and TCNTS can be cleared by another channel source when a mode for synchronization with another channel is specified by the TSYR register and synchronous clearing is selected with the MTU3.TCR.CCLR[2:0] bits. Figure 23.55 illustrates an example of this operation.
RX23W Group (n) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the TWCR.WRE bit to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval (Tb2 interval) at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing. Initial output suppression through setting the TWCR.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) • Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in Figure 23.57.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous clearing WRE bit = 1 MTU3.TGRA TCDR MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDR 0000h Positive-phase output Negative-phase output Output waveform is active-low. Figure 23.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 23.56; TWCR.WRE Bit is 1) Synchronous clearing WRE bit = 1 MTU3.TGRA TCDR MTU3.TGRB MTU3.TCNT MTU4.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous clearing WRE bit = 1 MTU3.TGRA TCDR MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDR 0000h Positive-phase output Negative-phase output Output waveform is active-low. Figure 23.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 23.56; TWCR.WRE Bit is 1) WRE bit = 1 Synchronous clearing MTU3.TGRA TCDR MTU3.TGRB MTU3.TCNT MTU4.TCNT TDDR 0000h Positive phase output Initial value output is suppressed.
RX23W Group (o) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Counter Clearing by MTU3.TGRA Compare Match In complementary PWM mode, counters MTU3.TCNT, MTU4.TCNT, and TCNTS can be cleared by MTU3.TGRA compare match when the TWCR.CCE bit is set. Figure 23.62 shows an operation example. Note: Note: Note: Note: Use this function only in complementary PWM mode 1 (transfer at crest). Do not specify synchronous clearing by another channel (do not set the TSYR.SYNCn bits (n = 0 to 4) to 1).
RX23W Group (p) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Waveform Output for Driving AC Synchronous Motor (Brushless DC Motor) In complementary PWM mode, a brushless DC motor can easily be controlled using the TGCR register. Figure 23.63 to Figure 23.66 show examples of brushless DC motor driving waveforms created using the TGCR register. To switch the output phases for a 3-phase brushless DC motor by means of external signals detected with a Hall element, etc., set the TGCR.FB bit to 0.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) External input MTIOC0A pin MTIOC0B pin MTIOC0C pin 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin When TGCR.BDC = 1, TGCR.N = 1, TGCR.P = 1, and TGCR.FB = 0, the high level is the active level for output. Figure 23.64 Example of Output Phase Switching by External Input (2) TGCR UF bit VF bit WF bit 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin When TGCR.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) UF bit TGCR VF bit WF bit 6-phase output MTIOC3B pin MTIOC3D pin MTIOC4A pin MTIOC4C pin MTIOC4B pin MTIOC4D pin When TGCR.BDC = 1, TGCR.N = 1, TGCR.P = 1, and TGCR.FB = 1, the high level is the active level for output. Figure 23.66 (q) Example of Output Phase Switching through UF, VF, and WF Bit Settings (2) A/D Converter Start Request Setting In complementary PWM mode, an A/D converter start request can be issued using the MTU3.
RX23W Group (3) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Interrupt Skipping in Complementary PWM Mode Interrupts TGIA3 (at the crest) and TCIV4 (at the trough) in MTU3 and MTU4 can be skipped up to seven times by setting the TITCR register. Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the TBTER register.
RX23W Group (b) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Example of Interrupt Skipping Operation Figure 23.69 shows an example of MTU3.TGIA interrupt skipping in which the interrupt skipping count is set to three by the TITCR.T3ACOR[2:0] bits and the TITCR.T3AEN bit is set to 1. Interrupt skipping period Interrupt skipping period MTU3.TGRA compare match Skipping counter 00h 01h 02h 03h 00h 01h 02h 03h TGIA3 interrupt signal Figure 23.
RX23W Group (c) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the TBTER.BTE[1:0] bits. Figure 23.70 shows an example of operation when buffer transfer is disabled (BTE[1:0] = 01b).
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.TCNT MTU4.TCNT TCNTSA (1) When the buffer register is modified within one carrier cycle after a TGIA3 interrupt TGIA3 generated TGIA3 generated MTU3. TCNT MTU4. TCNT Buffer transfer-enabled period Timing for modifying the buffer register Timing for modifying the buffer register TITCR1A.T3ACOR[2:0] bits 2 0 TITCNT1A.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU3.TCNT MTU4.TCNT TCNTSA Skipping counter TITCNT1A.T3ACNT[2:0] bits 0 Skipping counter TITCNT1A.T4VCNT[2:0] bits 1 0 2 1 3 2 0 3 1 0 2 1 3 2 0 3 Buffer transfer-enabled period (TITCNT1A.T3AEN bit is set to 1) Buffer transfer-enabled period (TITCNT1A.T4VEN bit is set to 1) Buffer transfer-enabled period (TITCNT1A.T3AEN and T4VEN bits are set to 1) Note: Figure 23.72 (4) The skipping count is set to three.
RX23W Group 23.3.9 23. Multi-Function Timer Pulse Unit 2 (MTU2a) A/D Converter Start Request Delaying Function A/D converter start requests can be issued in MTU4 by making settings in registers TADCR, TADCORA, TADCORB, TADCOBRA, and TADCOBRB. The A/D converter start request delaying function compares the MTU4.TCNT counter with the MTU4.TADCORA or MTU4.TADCORB register, and when their values match, the function issues a respective A/D converter start request (TRG4AN or TRG4BN).
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Basic Example of A/D Converter Start Request Delaying Function Operation Figure 23.74 shows a basic example of A/D converter start request signal (TRG4AN) operation when the trough of the MTU4.TCNT counter is specified for the buffer transfer timing and an A/D converter start request signal is output during MTU4.TCNT down-counting.
RX23W Group (5) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) A/D Converter Start Request Delaying Function Linked with Interrupt Skipping In complementary PWM mode, A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with interrupt skipping by making settings in the TADCR.ITA3AE bit, TADCR.ITA4VE bit, TADCR.ITB3AE bit, and TADCR.ITB4VE bit. Figure 23.75 shows an example of A/D converter start request signal (TRG4AN) operation when TRG4AN output is enabled during MTU4.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU4.TCNT MTU4.TADCORA TGIA3 interrupt skipping counter 00h TCIV4 interrupt skipping counter 01h 00h 02h 01h 00h 02h 01h 00h 01h TGIA3 A/D request-enabled period TCIV4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA3 and TCIV4 interrupt skipping When linked with TGIA3 interrupt skipping When linked with TCIV4 interrupt skipping Note: Figure 23.76 TADCR.UT4AE = 1 TADCR.
RX23W Group 23.3.10 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Noise Filter Each pin for use in input capture and external pulse input to the MTU is equipped with a noise filter. The noise filter samples input signals at the sampling clock and removes the pulses of which length is less than three sampling cycles. The noise filter functionality includes enabling and disabling of the noise filter for each pin and setting of the sampling clock for each channel. Figure 23.
RX23W Group 23.4 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Interrupt Sources 23.4.1 Interrupt Sources and Priorities There are three interrupt sources; the TGR input capture/compare match, the TCNT counter overflow, and the TCNT counter underflow. Each interrupt source has its own enable/disable bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
RX23W Group (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Input Capture/Compare Match Interrupt An interrupt is requested if the TIER.TGIE bit is set to 1 when a TGR input capture/compare match occurs on a channel. The MTU has 18 input capture/compare match interrupts (six for MTU0, four each for MTU3 and MTU4, and two each for MTU1 and MTU2). (2) Overflow Interrupt An interrupt is requested if the TIER.TGIE bit is set to 1 when a TCNT counter overflow occurs on a channel.
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) A/D Converter Activation by Compare Match between MTU0.TCNT and MTU0.TGRE A compare match between the MTU0.TCNT counter and the MTU0.TGRE register activates the A/D converter. A/D converter start request signal TRG0EN is issued when a compare match occurs between the MTU0.TCNT counter and the MTU0.TGRE register. If A/D converter start signal TRG0EN from the MTU is selected as the trigger in the A/D converter, A/D conversion will start.
RX23W Group 23.5 Operation Timing 23.5.1 (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Input/Output Timing TCNT Count Timing Figure 23.78 show the TCNT count timing for TGI interrupt in internal clock operation, Figure 23.79 shows the TCNT count timing in external clock operation (normal mode), and Figure 23.80 shows the TCNT count timing in external clock operation (phase counting mode). PCLK Internal clock Falling edge Rising edge TCNT count clock TCNT Figure 23.
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Output Compare Output Timing A compare match signal is generated in the final state in which the TCNT counter and the TGR register match (the point at which the count value matched is updated by the TCNT counter). When a compare match signal is generated, the value set in the TIOR register is output to the output compare output pin (MTIOC pin).
RX23W Group (3) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Input Capture Signal Timing Figure 23.83 shows the input capture signal timing. PCLK Input capture input Input capture signal TCNT N TGR Figure 23.83 N+1 N+2 N N+2 Input Capture Input Signal Timing R01UH0823EJ0110 Rev.1.
RX23W Group (4) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Timing for Counter Clearing by Compare Match/Input Capture Figure 23.84 show the timing when counter clearing on compare match is specified, and Figure 23.85 shows the timing when counter clearing on input capture is specified. PCLK Compare match signal Counter clear signal Figure 23.84 TCNT N TGR N 0000h Counter Clear Timing (Compare Match) (MTU0 to MTU4) PCLK Input capture signal Counter clear signal TCNT N TGR Figure 23.
RX23W Group (5) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Buffer Operation Timing Figure 23.86 to Figure 23.88 show the timing in buffer operation. PCLK TCNT n n+1 TGRA, TGRB n N TGRC, TGRD N Compare match signal Figure 23.86 Buffer Operation Timing (Compare Match) PCLK Input capture signal TCNT N TGRA, TGRB n N+1 TGRC, TGRD Figure 23.87 N N+1 n N Buffer Operation Timing (Input Capture) PCLK TCNT n 0000h TCNT clear signal Buffer transfer signal Figure 23.
RX23W Group (6) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Buffer Transfer Timing (Complementary PWM Mode) Figure 23.89 to Figure 23.91 show the buffer transfer timing in complementary PWM mode. PCLK TCNTS 0000h MTU4.TGRD write signal Temporary register transfer signal Figure 23.89 Buffer register n Temporary register n N N Transfer Timing from Buffer Register to Temporary Register (TCNTS Stop) PCLK TCNTS P–x P 0000h MTU4.
RX23W Group 23.5.2 (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Interrupt Signal Timing Timing for TGI Interrupt by Compare Match Figure 23.92 show the TGI interrupt request signal timing on compare match. PCLK TCNT count clock TCNT N TGR N N+1 Compare match signal Interrupt signal Figure 23.92 (2) TGI Interrupt Timing (Compare Match) (MTU0 to MTU4) Timing for TGI Interrupt by Input Capture Figure 23.93 show TGI interrupt request signal timing on input capture.
RX23W Group (3) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) TCIV and TCIU Interrupt Timing Figure 23.94 shows the TCIV interrupt request signal timing on overflow. Figure 23.95 shows the TCIU interrupt request signal timing on underflow. PCLK TCNT count clock TCNT (overflow) FFFFh 0000h 0000h FFFFh Overflow signal Interrupt signal Figure 23.94 TCIV Interrupt Timing PCLK TCNT count clock TCNT (underflow) Underflow signal Interrupt signal Figure 23.
RX23W Group 23.6 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Usage Notes 23.6.1 Module Clock Stop Mode Setting MTU operation can be disabled or enabled using the module stop control register. MTU operation is stopped with the initial setting. Register access is enabled by releasing the module clock stop mode. For details, refer to section 11, Low Power Consumption. 23.6.2 Count Clock Restrictions The count clock source pulse width must be at least 1.
RX23W Group 23.6.4 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Contention between TCNT Write and Clear Operations If the counter clear signal is generated in a TCNT write cycle, the TCNT counter clearing takes precedence and the TCNT counter write operation is not performed. Figure 23.97 shows the timing in this case. Written by CPU PCLK Counter clear signal TCNT Figure 23.97 23.6.
RX23W Group 23.6.6 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Contention between TGR Write Operation and Compare Match If a compare match occurs in a TGR write cycle, the TGR register write operation is executed and the compare match signal is also generated. Figure 23.99 shows the timing in this case. Written by CPU PCLK Compare match signal TCNT N N+1 TGR N M TGR write data Figure 23.99 23.6.
RX23W Group 23.6.8 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Contention between Buffer Register Write and TCNT Clear Operations When the buffer transfer timing is set at the TCNT clear timing by the timer buffer operation transfer mode register (TBTM), if TCNT clearing occurs in a TGR write cycle, the data before write operation is transferred to TGR by the buffer operation. Figure 23.101 shows the timing in this case.
RX23W Group 23.6.10 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Contention between TGR Write Operation and Input Capture If an input capture signal is generated in a TGR write cycle, the input capture operation takes precedence and the TGR register write operation is not performed. Figure 23.103 show the timing in this case. Written by CPU PCLK Input capture signal M TCNT TGR Figure 23.103 23.6.
RX23W Group 23.6.12 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation With timer counters MTU1.TCNT and MTU2.TCNT in a cascade, when a contention occurs between MTU1.TCNT counting (an MTU2.TCNT counter overflow/underflow) and the MTU2.TCNT write cycle, the MTU2.TCNT write operation is performed and the MTU1.TCNT count signal is disabled. In this case, if the MTU1.
RX23W Group 23.6.13 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Counter Value When Count Operation is Stopped in Complementary PWM Mode When counting operation in counters MTU3.TCNT and MTU4.TCNT is stopped in complementary PWM mode, the MTU3.TCNT counter is set to the TDDR register value and the MTU4.TCNT counter becomes 0000h. When operation is restarted in complementary PWM mode, counting begins automatically from the initial setting state. Figure 23.106 shows this operation.
RX23W Group 23.6.15 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Buffer Operation and Compare Match Flags in Reset-Synchronized PWM Mode When setting buffer operation in reset-synchronized PWM mode, set the MTU4.TMDR.BFA bit and MTU4.TMDR.BFB bit to 0. Setting the MTU4.TMDR.BFA bit to 1 disables MTIOC4C pin waveform output. Setting the MTU4.TMDR.BFB bit to 1 also disables MTIOC4D pin waveform output. In reset-synchronized PWM mode, buffer operation in MTU3 and MTU4 depends on the settings in the MTU3.
RX23W Group 23.6.16 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Overflow Flags in Reset-Synchronized PWM Mode After reset-synchronized PWM mode is selected, counters MTU3.TCNT and MTU4.TCNT start counting when the TSTR.CST3 bit is set to 1. In this state, the MTU4.TCNT count clock source and count edge are determined by the MTU3.TCR register setting. In reset-synchronized PWM mode, with cycle register MTU3.TGRA set to FFFFh and the MTU3.
RX23W Group 23.6.17 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Contention between Overflow/Underflow and Counter Clearing If an overflow/underflow and counter clearing occur simultaneously, the TCNT counter clearing takes precedence and the corresponding TCIV interrupt is not generated. If an overflow and counter clearing due to an input capture occur simultaneously, an input capture interrupt signal is output and an overflow interrupt signal is not output. Figure 23.
RX23W Group 23.6.19 23.
RX23W Group 23.6.23 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Notes When Complementary PWM Mode Output Protection Functions are Not Used The complementary PWM mode output protection functions are initially enabled. Refer to section 24, Port Output Enable 2 (POE2a), for details. 23.6.24 Points for Caution to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode If control of the output waveform is enabled (TWCR.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Synchronous clearing MTU3.TGRA 10 MTU3. TCNT 11 10 Tb interval 11 Tb interval MTU4. TCNT TDDR TGR 0 Positive-phase output Negative-phase output Although there is no period for output of the active level over this interval, synchronous clearing leads to output of the active level. Dead time is eliminated. Initial output inhibition : Dead time Note: Figure 23.112 PWM output is active-low.
RX23W Group 23.6.25 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Continuous Output of Interrupt Signal in Response to a Compare Match When the TGR register is set to 0000h, PCLK/1 is set as the count clock, and compare match is set as the trigger for clearing of the count clock, the value of the TCNT counter remains 0000h, and the interrupt signal will be output continuously (i.e. its level will be flat) rather than output over a single cycle.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Write 0 to MTU4.TADCOBRA*1 MTU4.TCNT MTU4.TADCORA MTU4.TADCOBRA A/D converter start request (TRG4AN) An A/D converter start request is not issued during up-counting immediately after buffer transfer (trough).*1 Complementary PWM mode UT4AE = 1 DT4AE = 0 BF[1:0] = 10b (transfer at trough) UT4AE, DT4AE, BF[1:0]: Bits in TADCR Note 1. An A/D converter start request is issued when TCDR – 1 ≥ MTU4.TADCOBRA/TADCOBRB ≥ 1 is written. Figure 23.
RX23W Group 23.7 23. Multi-Function Timer Pulse Unit 2 (MTU2a) MTU Output Pin Initialization 23.7.1 Operating Modes The MTU has the following six operating modes. Waveforms can be output in any of these modes.
RX23W Group 23.7.3 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Overview of Pin Initialization Procedures and Mode Transitions in Case of Error during Operation • When making a transition to a mode (Normal, PWM1, PWM2, or PCM) in which the pin output level is selected by the TIOR register setting, initialize the pins by means of the TIOR register setting. • In PWM mode 1, waveforms are not output to the MTIOCnB and MTIOCnD (n = 3, 4) pins.
RX23W Group (1) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operation When Error Occurs in Normal Mode and Operation is Restarted in Normal Mode Figure 23.116 shows a case in which an error occurs in normal mode and operation is restarted in normal mode after resetting.
RX23W Group (2) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operation When Error Occurs in Normal Mode and Operation is Restarted in PWM Mode 1 Figure 23.117 shows a case in which an error occurs in normal mode and operation is restarted in PWM mode 1 after resetting.
RX23W Group (4) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operation When Error Occurs in Normal Mode and Operation is Restarted in Phase Counting Mode Figure 23.119 shows a case in which an error occurs in normal mode and operation is restarted in phase counting mode after re-setting.
RX23W Group (5) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operation When Error Occurs in Normal Mode and Operation is Restarted in Complementary PWM Mode Figure 23.120 shows a case in which an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting.
RX23W Group (6) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operation When Error Occurs in Normal Mode and Operation is Restarted in ResetSynchronized PWM Mode Figure 23.121 shows a case in which an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting.
RX23W Group (7) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Normal Mode Figure 23.122 shows a case in which an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting.
RX23W Group (8) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in PWM mode 1 Figure 23.123 shows a case in which an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (10) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Phase Counting Mode Figure 23.125 shows a case in which an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (11) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in Complementary PWM Mode Figure 23.126 shows a case in which an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (12) Operation When Error Occurs in PWM Mode 1 and Operation is Restarted in ResetSynchronized PWM Mode Figure 23.127 shows a case in which an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (13) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Normal Mode Figure 23.128 shows a case in which an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (14) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in PWM Mode 1 Figure 23.129 shows a case in which an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (16) Operation When Error Occurs in PWM Mode 2 and Operation is Restarted in Phase Counting Mode Figure 23.131 shows a case in which an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (17) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in Normal Mode Figure 23.132 shows a case in which an error occurs in phase counting mode and operation is restarted in normal mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (18) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 1 Figure 23.133 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (19) Operation When Error Occurs in Phase Counting Mode and Operation is Restarted in PWM Mode 2 Figure 23.134 shows a case in which an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (21) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Normal Mode Figure 23.136 shows a case in which an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (22) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in PWM Mode 1 Figure 23.137 shows a case in which an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (23) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 23.138 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time of stopping the counter).
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (24) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Complementary PWM Mode with New Settings Figure 23.139 shows a case in which an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (operation is restarted using new cycle and duty settings).
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (25) Operation When Error Occurs in Complementary PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 23.140 shows a case in which an error occurs in complementary PWM mode and operation is restarted in resetsynchronized PWM mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (26) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Normal Mode Figure 23.141 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (27) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in PWM Mode 1 Figure 23.142 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (28) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Complementary PWM Mode Figure 23.143 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting.
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a) (29) Operation When Error Occurs in Reset-Synchronized PWM Mode and Operation is Restarted in Reset-Synchronized PWM Mode Figure 23.144 shows a case in which an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting.
RX23W Group 23.8 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Operations Linked by the ELC 23.8.1 Event Signal Output to the ELC The MTU is capable of operation linked with another module set in advance when its interrupt request signal is used as an event signal by the event link controller (ELC). The MTU outputs the event signal regardless of the setting of the corresponding interrupt request enable bit. 23.8.
RX23W Group (3) 23. Multi-Function Timer Pulse Unit 2 (MTU2a) Counter Restart Operation The MTU is selected the count start operation when using the ELOPA and ELOPB registers setting of the ELC. The ELOPA register functions MTU1 to MTU3, and ELOPB register functions MTU4. The TMDR register of the channel set by MTU should be set to the value after reset, 00h. When the specified event is generated by the ELSRn register, then the TCNT counter value is rewritten to initial value. When the TSTR.
RX23W Group 24. 24.
RX23W Group 24.
RX23W Group 24. Port Output Enable 2 (POE2a) Table 24.2 lists I/O pins to be used by the POE. Table 24.2 POE I/O Pins Pin Name I/O Description POE0#, POE1#, POE3# Input Request signals to place the pins for MTU complementary PWM output in high-impedance. POE8# Input Request signal to place the MTU0 output pins in high-impedance.
RX23W Group 24.2 24. Port Output Enable 2 (POE2a) Register Descriptions 24.2.
RX23W Group 24. Port Output Enable 2 (POE2a) When low-level sampling has been set by the POE0M[1:0], POE1M[1:0], and POE3M[1:0] bits, writing 0 to the POE0F, POE1F, and POE3F flags requires high-level input on the POE0#, POE1F, and POE3# pins. For details, refer to section 24.3.6, Release from the High-Impedance. PIE1 Bit (Port Interrupt Enable 1) This bit enables or disables OEI1 interrupt requests when any one of the POE0F, POE1F, and POE3F flags is set to 1.
RX23W Group 24.2.2 24. Port Output Enable 2 (POE2a) Output Level Control/Status Register 1 (OCSR1) Address(es): 0008 8902h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 OSF1 — — — — — OCE1 OIE1 — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b7 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 24.2.3 24. Port Output Enable 2 (POE2a) Input Level Control/Status Register 2 (ICSR2) Address(es): 0008 8908h Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 — — — POE8F — — POE8E PIE2 — — — — — — POE8M[1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b0 0 Bit Symbol Bit Name Description R/W b1, b0 POE8M[1:0] POE8 Mode Select b1 b0 R/W*1 b7 to b2 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 24.2.4 24. Port Output Enable 2 (POE2a) Software Port Output Enable Register (SPOER) Address(es): 0008 890Ah Value after reset: b7 b6 b5 b4 b3 b2 — — — — — — 0 0 0 0 0 0 b1 b0 CH0HI CH34HI Z Z 0 0 Bit Symbol Bit Name Description R/W b0 CH34HIZ MTU3 and MTU4 Output HighImpedance Enable 0: Does not place the pins in high-impedance. 1: Places the pins in high-impedance.
RX23W Group 24.2.5 24. Port Output Enable 2 (POE2a) Port Output Enable Control Register 1 (POECR1) Address(es): 0008 890Bh Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 PE2ZE PE1ZE PE0ZE 0 0 0 Bit Symbol Bit Name Description R/W b0 PE0ZE MTIOC0A High-Impedance Enable 0: Does not place the pin in high-impedance. 1: Places the pin in high-impedance. R/W*1 b1 PE1ZE MTIOC0B High-Impedance Enable 0: Does not place the pin in high-impedance.
RX23W Group 24.2.6 24. Port Output Enable 2 (POE2a) Port Output Enable Control Register 2 (POECR2) Address(es): 0008 890Ch b7 — Value after reset: 0 b6 b5 b4 P1CZE P2CZE P3CZE A A A 1 1 1 b3 b2 b1 b0 — — — — 0 0 0 0 Bit Symbol Bit Name Description R/W b3 to b0 — Reserved These bits are read as 0. The write value should be 0. R/W b4 P3CZEA MTU Port 3 High-Impedance Enable 0: Comparison of output levels does not proceed and the pins are not placed in the high-impedance.
RX23W Group 24.2.7 24. Port Output Enable 2 (POE2a) Input Level Control/Status Register 3 (ICSR3) Address(es): 0008 890Eh Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 — — — OSTST F — — OSTST E — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b8 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 24.3 24. Port Output Enable 2 (POE2a) Operation The target pins for high-impedance control and conditions to place the pins in high-impedance are described below. (1) MTU0 pin (MTIOC0A) When any of the following conditions is satisfied, the pin is placed to the high-impedance state. • POE8# input level detection When the ICSR2.POE8F flag is set to 1 with POECR1.PE0ZE and ICSR2.POE8E set to 1. • SPOER setting When the SPOER.CH0HIZ bit is set to 1 with POECR1.PE0ZE set to 1.
RX23W Group 24. Port Output Enable 2 (POE2a) (5) MTU4 pins (MTIOC4A and MTIOC4C) When any of the following conditions is satisfied, the pins are placed to the high-impedance state. • POE0#, POE1#, and POE3# input level detection When the ICSR1.POE3F, POE1F, or POE0F flag is set to 1 with POECR2.P2CZEA set to 1. • MTIOC4A and MTIOC4C output level comparison When the OCSR1.OSF1 flag is set to 1 with POECR2.P2CZEA and OCSR1.OCE1 set to 1. • SPOER setting When the SPOER.CH34HIZ bit is set to 1 with POECR2.
RX23W Group 24.3.1 24. Port Output Enable 2 (POE2a) Input Level Detection Operation If the input conditions set by the ICSR1 and ICSR2 registers occur on the POE0# to POE3# and POE8# pins, the pins for the MTU complementary PWM output and MTU0 are placed in high-impedance. (1) Falling Edge Detection When a change from a high to low level is input to the POE0#, POE1#, POE3# and POE8# pins, the pins for the MTU complementary PWM output and MTU0 are placed in high-impedance.
RX23W Group (2) 24. Port Output Enable 2 (POE2a) Low-Level Detection Figure 24.3 shows the low-level detection operation. When a low level is detected 16 times continuously with the sampling clock selected by the ICSR1 and ICSR2 registers, the detected level is recognized as low, and the pins for the MTU complementary PWM output and MTU0 are placed in high-impedance. If even one high level is detected during this interval, the detected level is not recognized as low.
RX23W Group 24.3.3 24. Port Output Enable 2 (POE2a) High-Impedance Control Using Registers The high-impedance of the MTU complementary PWM output and MTU0 pins can be directly controlled by writing to the software port output enable register (SPOER). Setting the SPOER.CH34HIZ bit to 1 places the MTU complementary PWM output pins (MTU3 and MTU4) specified by the POECR2 register in the high-impedance. Setting the SPOER.
RX23W Group 24.4 24. Port Output Enable 2 (POE2a) Interrupts The POE issues a request to generate an interrupt when the corresponding condition below is matched during input-level detection, output-level comparison, or oscillation stop by the clock generation circuit. Table 24.4 lists the interrupt sources and their request conditions.
RX23W Group 25. 25. 16-Bit Timer Pulse Unit (TPUa) 16-Bit Timer Pulse Unit (TPUa) This MCU has on-chip 16-bit timer pulse units (TPU) comprising six-channel 16-bit timers. In this section, “PCLK” is used to refer to PCLKB. 25.1 Overview Specifications of the TPU are listed in Table 25.1. Functions of TPU are listed in Table 25.2. Figure 25.1 shows a block diagram of TPU. Table 25.
RX23W Group Table 25.2 25.
TGRD TGRB TGRC TCNT TGRA TSR NFCR TIER TCNT TGRA TGRB TCNT TGRA TGRB TGRD TGRB TGRB TIER: TSR: TGR (A, B, C, D): TCNT: NFCR: TGRC TCNT TGRA TGRB A/D conversion start request signal TCNT TCNT Bus interface Module data bus TPU3: TGI3A TGI3B TGI3C TGI3D TCI3V TPU4: TGI4A TGI4B TCI4V TCI4U TPU5: TGI5A TGI5B TCI5V TCI5U Internal peripheral bus TGRA TGRA NFCR TIER TSR NFCR TIER TSYR TSTR TSR NFCR TIER TSR NFCR TIER TSR TIER TCR TIOR TCR TMDR TIOR NFCR TMDR TIORH TIORL TCR [In
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Table 25.3 lists the input/output pins of the TPU. Table 25.
RX23W Group 25.2 25. 16-Bit Timer Pulse Unit (TPUa) Register Descriptions 25.2.1 Timer Control Register (TCR) Address(es): TPU0.TCR 0008 8110h, TPU1.TCR 0008 8120h, TPU2.TCR 0008 8130h, TPU3.TCR 0008 8140h, TPU4.TCR 0008 8150h, TPU5.TCR 0008 8160h b7 b6 b5 CCLR[2:0] Value after reset: 0 0 b4 b3 b2 CKEG[1:0] 0 0 0 b1 b0 TPSC[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 TPSC[2:0] Timer Prescaler Select See Table 25.4 to Table 25.9.
RX23W Group Table 25.4 25. 16-Bit Timer Pulse Unit (TPUa) Bits TPSC[2:0] (TPU0) Bits TPSC[2:0] Channel b2 b1 b0 Description TPU0 0 0 0 Internal clock: counts on PCLK/1 0 0 1 Internal clock: counts on PCLK/4 0 1 0 Internal clock: counts on PCLK/16 0 1 1 Internal clock: counts on PCLK/64 Table 25.
RX23W Group Table 25.7 25. 16-Bit Timer Pulse Unit (TPUa) Bits TPSC[2:0] (TPU3) Bits TPSC[2:0] Channel b2 b1 b0 Description TPU3 0 0 0 Internal clock: counts on PCLK/1 0 0 1 Internal clock: counts on PCLK/4 0 1 0 Internal clock: counts on PCLK/16 0 1 1 Internal clock: counts on PCLK/64 1 0 0 External clock: counts on TCLKA pin input 1 0 1 Internal clock: counts on PCLK/1024 1 1 0 Internal clock: counts on PCLK/256 1 1 1 Internal clock: counts on PCLK/4096 Table 25.
RX23W Group Table 25.10 25. 16-Bit Timer Pulse Unit (TPUa) Bits CKEG[1:0] Bits CKEG[1:0] Input Clock b4 b3 Internal Clock External clock 0 0 Counted at falling edge Counted at rising edge 0 1 Counted at rising edge Counted at falling edge 1 0 Counted at both edges Counted at both edges 1 1 Counted at both edges Counted at both edges Table 25.
RX23W Group 25.2.2 25. 16-Bit Timer Pulse Unit (TPUa) Timer Mode Register (TMDR) Address(es): TPU0.TMDR 0008 8111h, TPU1.TMDR 0008 8121h, TPU2.TMDR 0008 8131h, TPU3.TMDR 0008 8141h, TPU4.TMDR 0008 8151h, TPU5.TMDR 0008 8161h b7 b6 ICSEL ICSELB D Value after reset: 0 0 b5 b4 BFB BFA 0 0 b3 b2 b1 b0 MD[3:0] 0 0 0 0 Bit Symbol Bit Name Description R/W b3 to b0 MD[3:0] Mode Select b3 R/W b4 BFA Buffer Operation A*2 0: TPUm.TGRA operates normally 1: TPUm.TGRA and TPUm.
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) ICSELD Bit (TGRD Input Capture Input Select) Selects the input capture input for TPUm.TGRD (m = 3). This function allows measurement of high-level width and period of the input pulse on a TIOCCn input pin. 25.2.3 Timer I/O Control Register (TIORH, TIORL, TIOR) • TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIOR, TPU5.TIOR Address(es): TPU0.TIORH 0008 8112h, TPU1.TIOR 0008 8122h, TPU2.TIOR 0008 8132h, TPU3.TIORH 0008 8142h, TPU4.TIOR 0008 8152h, TPU5.
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) TPU has two TIORH registers, one for TPU0 and TPU3, and one TIORL register for TPU3, and also has four TIOR registers, one for TPU1, TPU2, TPU4, and TPU5. Thus the TPU has seven timer I/O control registers in total. TIORH, TIORL, and TIOR control registers TGRA, TGRB, TGRC, and TGRD. Note that TIORH, TIORL, and TIOR are affected by the TMDR setting. For details, see Table 25.13 to Table 25.19.
RX23W Group Table 25.13 25. 16-Bit Timer Pulse Unit (TPUa) TPU0.TIOR Bits IOB[3:0] Description b7 b6 b5 b4 TPU0.
RX23W Group Table 25.15 25. 16-Bit Timer Pulse Unit (TPUa) TPU2.TIOR Bits IOB[3:0] Description b7 b6 b5 b4 TPU2.
RX23W Group Table 25.16 25. 16-Bit Timer Pulse Unit (TPUa) TPU3.TIORH Bits IOA[3:0] Description b3 b2 b1 b0 TPU3.
RX23W Group Table 25.17 25. 16-Bit Timer Pulse Unit (TPUa) TPU4.TIOR Bits IOA[3:0] Description b3 b2 b1 b0 TPU4.
RX23W Group Table 25.18 25. 16-Bit Timer Pulse Unit (TPUa) TPU5.TIOR Bits IOB[3:0] Description b7 b6 b5 b4 TPU5.
RX23W Group Table 25.19 25. 16-Bit Timer Pulse Unit (TPUa) TPU3.TIORL Bits IOC[3:0] Description b3 b2 b1 b0 TPU3.
RX23W Group 25.2.4 25. 16-Bit Timer Pulse Unit (TPUa) Timer Interrupt Enable Register (TIER) Address(es): TPU0.TIER 0008 8114h, TPU1.TIER 0008 8124h, TPU2.TIER 0008 8134h, TPU3.TIER 0008 8144h, TPU4.TIER 0008 8154h, TPU5.
RX23W Group 25.2.5 25. 16-Bit Timer Pulse Unit (TPUa) Timer Status Register (TSR) Address(es): TPU0.TSR 0008 8115h, TPU1.TSR 0008 8125h, TPU2.TSR 0008 8135h, TPU3.TSR 0008 8145h, TPU4.TSR 0008 8155h, TPU5.TSR 0008 8165h b7 b6 b5 b4 b3 b2 b1 b0 TCFD — TCFU TCFV TGFD TGFC TGFB TGFA 1 1 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b0 TGFA Input Capture/Output Compare Flag A 0: Input capture to TPUm.TGRA or compare match with TPUm.TGRA has not occurred.
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) TGFA Flag (Input Capture/Output Compare Flag A) This status flag indicates that input capture to TPUm.TGRA or compare match with TPUm.TGRA (m = 0 to 5) has occurred. [Setting conditions] • When TPUm.TGRA holds the value for comparison in output-compare operations, TPUm.TCNT matches TPUm.TGRA. • When TPUm.TGRA is serving as an input-capture register, the input-capture signal has caused transfer of the value in TPUm.TCNT to TPUm.TGRA.
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) TCFV Flag (Overflow Flag) This status flag indicates an overflow of TPUm.TCNT (m = 0 to 5). [Setting condition] • Overflow of the value in TPUm.TCNT (TCNT counted from FFFFh to 0000h). [Clearing condition] • Writing 0 to TCFV after reading its value as 1. TCFU Flag (Underflow Flag) This status flag indicates an underflow of TPUm.TCNT (m = 1, 2, 4, 5). [Setting condition] • Underflow of the value in TPUm.TCNT (TCNT counted from 0000h to FFFFh).
RX23W Group 25.2.6 25. 16-Bit Timer Pulse Unit (TPUa) Timer Counter (TCNT) Address(es): TPU0.TCNT 0008 8116h, TPU1.TCNT 0008 8126h, TPU2.TCNT 0008 8136h, TPU3.TCNT 0008 8146h, TPU4.TCNT 0008 8156h, TPU5.TCNT 0008 8166h Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPUm.TCNT is a readable/writable counter that counts the internal clock or external events. 25.2.
RX23W Group 25.2.8 25. 16-Bit Timer Pulse Unit (TPUa) Timer Start Register (TSTR) Address(es): TPU.
RX23W Group 25.2.9 25. 16-Bit Timer Pulse Unit (TPUa) Timer Synchronous Register (TSYR) Address(es): TPU.
RX23W Group 25.2.10 25. 16-Bit Timer Pulse Unit (TPUa) Noise Filter Control Register (NFCR) Address(es): TPU0.NFCR 0008 8108h, TPU1.NFCR 0008 8109h, TPU2.NFCR 0008 810Ah, TPU3.NFCR 0008 810Bh, TPU4.NFCR 0008 810Ch, TPU5.NFCR 0008 810Dh Value after reset: Bit b7 b6 b5 — — NFCS[1:0] 0 0 0 Symbol b4 0 b3 b2 b1 b0 NFDEN NFCEN NFBEN NFAEN 0 Bit Name Enable A*2 0 0 0 Description R/W 0: The noise filter for TIOCAm is disabled. 1: The noise filter for TIOCAm is enabled.
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) NFDEN Bit (Noise Filter Enable D) This bit disables or enables the noise filter for the TIOCDm pin (m = 3). Since unexpected edges may be internally generated when the value of NFDEN is changed, select the output compare function in the timer I/O control register before changing the NFDEN value. NFCS[1:0] Bits (Noise Filter Clock Select) These bits select the sampling clock for the noise filter.
RX23W Group 25.3 25. 16-Bit Timer Pulse Unit (TPUa) Operation 25.3.1 Basic Functions Each channel has a TPUm.TCNT and a TPUm.TGRy register (y = A to D). TCNT is a 16-bit up-counter, which can function as a free-running counter, periodic counter, or event counter. TGRy can be used as an input capture register or output compare register. (1) Counter Operation When the CSTj bit (j = 0 to 5) in TPU.TSTR is set to 1, the TCNT for the corresponding channel starts counting.
RX23W Group (b) 25. 16-Bit Timer Pulse Unit (TPUa) Free-running count operation and periodic count operation Immediately after a reset, TPUm.TCNT are all set as free-running counters. When the relevant bit in TPU.TSTR is set to 1, the corresponding TCNT starts up-count operation as a free-running counter. When TCNT overflows (changes from FFFFh to 0000h), the TPU requests an interrupt. After an overflow, TCNT restarts counting up from 0000h. Figure 25.3 shows free-running counter operation.
RX23W Group (2) 25. 16-Bit Timer Pulse Unit (TPUa) Waveform Output by Compare Match The TPU can perform low, high, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 25.5 shows an example of the setting procedure for waveform output by a compare match.
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Figure 25.7 shows an example of toggle output. In this example, TPUm.TCNT has been set as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match FFFFn TGRB TGRA Time 0000h Toggle output TIOCBn Toggle output TIOCAn Figure 25.
RX23W Group (a) 25. 16-Bit Timer Pulse Unit (TPUa) Example of setting procedure for input capture operation Figure 25.8 shows an example of the setting procedure for input capture operation.
RX23W Group (b) 25. 16-Bit Timer Pulse Unit (TPUa) Example of input capture operation Figure 25.9 shows an example of input capture operation when the noise filter is stopped. In this example, both rising and falling edges have been selected as the TIOCAn pin input capture input edge, the falling edge has been selected as the TIOCBn pin input capture input edge, and counter clearing by TPUm.TGRB input capture has been set for TPUm.TCNT.
RX23W Group 25.3.2 25. 16-Bit Timer Pulse Unit (TPUa) Synchronous Operation In synchronous operation, the values in multiple TPUm.TCNT can be rewritten simultaneously (synchronous setting). Also, multiple TCNT can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TPUm.TCR. Synchronous operation enables TPUm.TGRy to be incremented with respect to a single time base. TPU0 to TPU5 can all be set for synchronous operation.
RX23W Group (2) 25. 16-Bit Timer Pulse Unit (TPUa) Example of Synchronous Operation Figure 25.11 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been set for TPU0 to TPU2, TPU0.TGRA compare match has been set as the TPU0 counter clearing source, and synchronous clearing has been set for the TPU1 and TPU2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCB0, TIOCB1, and TIOCB2.
RX23W Group 25.3.3 25. 16-Bit Timer Pulse Unit (TPUa) Buffer Operation Buffer operation, provided for TPU0 and TPU3, enables TPUm.TGRC and TPUm.TGRD to be used as buffer registers. Buffer operation differs depending on whether TPUm.TGRy has been set as an input capture register or a compare match register. Table 25.20 lists the register combinations used in buffer operation. Table 25.20 Register Combinations Channel Timer General Register Buffer Register TPU0 TPU0.TGRA TPU0.TGRC TPU0.TGRB TPU0.
RX23W Group (1) 25. 16-Bit Timer Pulse Unit (TPUa) Example of Buffer Operation Setting Procedure Figure 25.14 shows an example of the buffer operation setting procedure. Buffer operation Select TGRy function [1] [1] Set TGRy as an input capture register or output compare register by TIOR (y = A to D). [2] Set TGRy for buffer operation with bits BFA and BFB in TMDR. Set buffer operation [2] Start count [3] [3] Set the TPU.TSTR.CSTj bit (j = 0 to 5) to 1 to start the counter operation.
RX23W Group (b) 25. 16-Bit Timer Pulse Unit (TPUa) When TPUm.TGRy is an input capture register Figure 25.16 shows an operation example in which TPUm.TGRA has been set as an input capture register, and buffer operation has been set for the TGRA register and TPUm.TGRC. Counter clearing by TGRA input capture has been set for TPUm.TCNT, and both rising and falling edges have been selected as the TIOCAn pin input capture input edge.
RX23W Group 25.3.4 25. 16-Bit Timer Pulse Unit (TPUa) Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the TPU1 (TPU4) count clock at overflow/underflow of TPU2.TCNT (TPU5.TCNT) as set by the TPSC[2:0] bits in TPU1.TCR (TPSC[2:0] bits in TPU4.TCR). Underflow occurs only when the lower 16-bit TPUm.TCNT is in phase counting mode. Table 25.21 lists the register combinations used in cascaded operation.
RX23W Group (2) 25. 16-Bit Timer Pulse Unit (TPUa) Examples of Cascaded Operation Figure 25.18 shows the operation when counting upon TPU2.TCNT overflow/underflow has been set for TPU1.TCNT, TPU1.TGRB and TPU2.TGRB have been set as input capture registers, and the rising edge of the TIOCB1 and TIOCB2 pins has been selected. When a rising edge is input to the TIOCB1 and TIOCB2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TPU1.TGRB, and the lower 16 bits to TPU2.TGRB.
RX23W Group 25.3.5 25. 16-Bit Timer Pulse Unit (TPUa) PWM Modes In PWM mode, PWM waveforms are output from the output pins. low, high, or toggle output can be selected as the output level in response to compare match of each TPUm.TGRy. Settings of TGRy registers can output a PWM waveform in the range of 0% to 100% duty cycle. Specifying TGRy compare match as the counter clearing source enables the cycle to be set in that register. All channels can be set for PWM mode independently.
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) The correspondence between PWM output pins and registers is listed in Table 25.22. Table 25.22 PWM Output Registers and Output Pins Output Pin Channel TPU0 Register PWM Mode 1 TPU0.TGRA No pin is assigned for this output. TPU0.TGRB TPU0.TGRC TPU1.TGRA No pin is assigned for this output. TPU2.TGRA No pin is assigned for this output. TPU3.TGRA TIOCA3 TPU4.TGRA TIOCC3 TPU5.TGRA TPU5.TGRB Note: TIOCC3 TIOCD3 TIOCA4 TPU4.
RX23W Group (1) 25. 16-Bit Timer Pulse Unit (TPUa) Example of PWM Mode Setting Procedure Figure 25.20 shows an example of the PWM mode setting procedure. PWM mode Select count clock [1] [1] Select the count clock with the TPSC[2:0] bits in TCR. At the same time, select the input clock edge with the CKEG[1:0] bits in TCR. Select counter clearing source [2] [2] Select the TGRy register to be used as the TCNT clearing source with the CCLR[2:0] bits in TCR (y = A to D).
RX23W Group (2) 25. 16-Bit Timer Pulse Unit (TPUa) Examples of PWM Mode Operation Figure 25.21 shows an example of PWM mode 1 operation. In this example, TPUm.TGRA compare match is set as the TPUm.TCNT clearing source, low is set for the TGRA initial output value and output value, and high is set as the TPUm.TGRB output value. In this case, the value set in TGRA is used as the cycle, and the value set in TGRB is used as the duty cycle.
RX23W Group 25. 16-Bit Timer Pulse Unit (TPUa) Figure 25.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB changed TGRB TGRB changed 0000h Time 0% duty cycle TIOCAn Output does not change when compare matches in cycle register and duty register occur simultaneously.
RX23W Group 25.3.6 25. 16-Bit Timer Pulse Unit (TPUa) Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected by the settings for channels 1, 2, 4, and 5, and TPUm.TCNT is incremented/decremented accordingly. When phase counting mode is set, an external clock is selected as the count clock and TCNT operates as an up-/downcounter regardless of the setting of the TPSC[2:0] bits and CKEG[1:0] bits in TPUm.TCR.
RX23W Group (2) 25. 16-Bit Timer Pulse Unit (TPUa) Examples of Phase Counting Mode Operation In phase counting mode, TPUm.TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase counting mode 1 Figure 25.25 shows an example of phase counting mode 1 operation, and Table 25.24 lists the TPUm.TCNT up-/ down-count conditions.
RX23W Group (b) 25. 16-Bit Timer Pulse Unit (TPUa) Phase counting mode 2 Figure 25.26 shows an example of phase counting mode 2 operation, and Table 25.25 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Up-count Down-count Time Figure 25.26 Table 25.
RX23W Group (c) 25. 16-Bit Timer Pulse Unit (TPUa) Phase counting mode 3 Figure 25.27 shows an example of phase counting mode 3 operation, and Table 25.26 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Up-count Down-count Time Figure 25.27 Table 25.
RX23W Group (d) 25. 16-Bit Timer Pulse Unit (TPUa) Phase counting mode 4 Figure 25.28 shows an example of phase counting mode 4 operation, and Table 25.27 lists the TPUm.TCNT up-/ down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Up-count Down-count Time Figure 25.28 Table 25.
RX23W Group 25.3.6.1 25. 16-Bit Timer Pulse Unit (TPUa) Phase Counting Mode Application Example Figure 25.29 shows an example in which phase counting mode is set for TPU4, and TPU4 is coupled with TPU3 to input servo motor 2-phase encoder pulses in order to detect the position or speed. TPU4 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to the TCLKA and TCLKB pins. TPU3 operates with TPU3.TCNT clearing by TPU3.TGRC compare match; TPU3.TGRA and TPU3.
RX23W Group 25.3.7 25. 16-Bit Timer Pulse Unit (TPUa) Noise Filters Each pin for use in input capture by TPU is equipped with a noise filter. The noise filter samples the level on the pin three times at the selected sampling interval, conveys the level to the internal circuits if the samples match, and continues to convey that level until the other level is sampled from the pins three times in a row. The noise filter function can be enabled or disabled for each pin.
RX23W Group 25.4 25. 16-Bit Timer Pulse Unit (TPUa) Interrupt Sources There are three kinds of TPU interrupt sources: TPUm.TGRy input capture/compare match, TPUm.TCNT overflow, and TPUm.TCNT underflow. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 15, Interrupt Controller (ICUb). Table 25.28 lists the TPU interrupt sources. Table 25.
RX23W Group (1) 25. 16-Bit Timer Pulse Unit (TPUa) Input Capture/Compare Match Interrupt An interrupt is requested when the TGIEy bit (y = A, B, C, D) in TPUm.TIER is set to 1 by the occurrence of a TPUm.TGRy input capture/compare match on a channel. The TPU has 16 input capture/compare match interrupts, four each for TPU0 and TPU3, and two each for TPU1, TPU2, TPU4, and TPU5. (2) Overflow Interrupt An interrupt is requested when the TCIEV bit in TPUm.TIER is set to 1 by the occurrence of a TPUm.
RX23W Group 25.8 Operation Timing 25.8.1 (1) 25. 16-Bit Timer Pulse Unit (TPUa) Input/Output Timing TPUm.TCNT Count Timing Figure 25.31 shows TPUm.TCNT count timing in internal clock operation, and Figure 25.32 shows TCNT count timing in external clock operation. PCLK Falling edge Internal clock Rising edge Falling edge TCNT input clock N–1 TCNT Figure 25.
RX23W Group (2) 25. 16-Bit Timer Pulse Unit (TPUa) Output Compare Output Timing A compare match signal is generated in the final state in which TPUm.TCNT and TPUm.TGRy match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TPUm.TIORH, TPUm.TIORL, or TPUm.TIOR is output to the output compare output pin TIOCyn (y = A to D; n = 0 to 5).
RX23W Group (4) 25. 16-Bit Timer Pulse Unit (TPUa) Timing for Counter Clearing by Compare Match/Input Capture Figure 25.35 shows the timing when counter clearing by compare match occurrence is specified, and Figure 25.36 shows the timing when counter clearing by input capture occurrence is specified. PCLK Compare match signal Counter clear signal Figure 25.35 TPUm.TCNT N TPUm.TGRy N 0000h Counter Clear Timing (Compare Match) PCLK Input capture signal Counter clear signal TPUm.
RX23W Group (5) 25. 16-Bit Timer Pulse Unit (TPUa) Buffer Operation Timing Figure 25.37 and Figure 25.38 show the timings in buffer operation. PCLK n TCNT N+1 Compare match signal TGRA, TGRB n TGRC, TGRD Figure 25.37 N N Buffer Operation Timing (Compare Match) PCLK Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD Figure 25.38 N+1 N N+1 n N Buffer Operation Timing (Input Capture) R01UH0823EJ0110 Rev.1.
RX23W Group 25.8.2 (1) 25. 16-Bit Timer Pulse Unit (TPUa) Interrupt Signal Timing Timing of Interrupt Signal Setting on Compare Match Figure 25.39 shows the timing for setting the interrupt signal by compare match occurrence. PCLK TCNT input clock N TCNT N+1 N TGRy Compare match signal Interrupt signal Figure 25.39 (2) TGImy Interrupt Timing (Compare Match) Timing of Interrupt Signal Setting on Input Capture Figure 25.
RX23W Group (3) 25. 16-Bit Timer Pulse Unit (TPUa) Timing of TCImV/TCImU Interrupt Signal Setting Figure 25.41 shows the timing for generating the TCImV interrupt signal by overflow occurrence. Figure 25.42 shows the timing for generating the TCImU interrupt signal by underflow occurrence. PCLK TCNT input clock TCNT (overflow) FFFFh 0000h Overflow signal Interrupt signal Figure 25.
RX23W Group 25.9 25. 16-Bit Timer Pulse Unit (TPUa) Usage Notes 25.9.1 Module Stop Function Setting Operation of the TPU can be disabled or enabled using the module stop control register. The TPU does not operate with the initial setting. Register access is enabled by releasing the module stop state. For details, see section 11, Low Power Consumption. 25.9.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 PCLK cycles in the case of single-edge detection, and at least 2.
RX23W Group 25.9.4 25. 16-Bit Timer Pulse Unit (TPUa) Conflict between TPUm.TCNT Write and Clear Operations If the counter clearing signal is generated in a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 25.44 shows the timing in this case. TCNT write by CPU PCLK Counter clear signal TCNT Figure 25.44 25.9.5 N 0000h Conflict between TPUm.TCNT Write and Clear Operations Conflict between TPUm.
RX23W Group 25.9.6 25. 16-Bit Timer Pulse Unit (TPUa) Conflict between TPUm.TGRy Write and Compare Match If a compare match occurs in a TGRy write cycle, the TGRy write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 25.46 shows the timing in this case. TGR write by CPU PCLK Disabled Compare match signal TCNT N N+1 TGRy N M TGRy write data Figure 25.46 25.9.7 Conflict between TPUm.
RX23W Group 25.9.8 25. 16-Bit Timer Pulse Unit (TPUa) Conflict between TPUm.TGRy Read and Input Capture If the input capture signal is generated in a TGRy read cycle, the data that is read will be the data before input capture transfer. Figure 25.48 shows the timing in this case. Buffer register read by CPU PCLK Input capture signal TGRy Internal data bus Figure 25.48 25.9.9 N M N Conflict between TPUm.TGRy Read and Input Capture Conflict between TPUm.
RX23W Group 25.9.10 25. 16-Bit Timer Pulse Unit (TPUa) Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 25.50 shows the timing in this case. Buffer register write by CPU PCLK Input capture signal N TCNT TGRy M Buffer register Figure 25.50 25.9.
RX23W Group 25.9.12 25. 16-Bit Timer Pulse Unit (TPUa) Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, TPUm.TCNT is cleared with the generation of the compare match interrupt and an overflow interrupt is generated. Figure 25.51 shows the operation timing when a TPUm.TGRy compare match is specified as the clearing source and FFFFh is set in TGRy.
RX23W Group 25.9.13 25. 16-Bit Timer Pulse Unit (TPUa) Conflict between TPUm.TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in a TCNT write cycle, the TCNT write takes precedence. Figure 25.52 shows the operation timing when there is conflict between TCNT write and overflow. TCNT write by CPU PCLK TCNT write data TCNT FFFFh M Interrupt signal Figure 25.52 25.9.14 Conflict between TPUm.
RX23W Group 25.9.15 25. 16-Bit Timer Pulse Unit (TPUa) Continuous Output of Compare-Match Pulse Interrupt Signal When TGR is set to 0000h, PCLK/1 is set as the count clock, and compare match is set as the counter clear source, the TCNT remains 0000h and is not updated, and a compare-match pulse interrupt signal is output continuously to form a flat signal level. When a pulse interrupt signal is used, the interrupt controller cannot detect the second and subsequent interrupts. Figure 25.
RX23W Group 25.9.16 25. 16-Bit Timer Pulse Unit (TPUa) Continuous Output of Input-Capture Pulse Interrupt Signal When input-capture signal is set on both edges and when the pulse width of the input-capture input equals to one PCLK cycle detected by internal sampling, input capture is generated continuously on the rising and falling edges. Therefore, an input-capture pulse interrupt signal is output continuously to form a flat signal level.
RX23W Group 25.9.17 25. 16-Bit Timer Pulse Unit (TPUa) Continuous Output of Underflow Pulse Interrupt Signal If two external clock signals' same direction edges to be phase counted are generated within two PCLK cycles in phase counting mode 1, with TGR being 0000h, and compare match set as the counter clear source, the TCNT remains 0000h and is not updated, and a compare-match pulse interrupt signal and an underflow interrupt signal are output continuously to form a flat signal level.
RX23W Group 26. 26. 8-Bit Timer (TMR) 8-Bit Timer (TMR) This MCU has two units (unit 0, unit 1) of an on-chip 8-bit timer (TMR) module that comprise two 8-bit counter channels, totaling four channels. The 8-bit timer module can be used to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset signal, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers.
RX23W Group Table 26.2 26. 8-Bit Timer (TMR) TMR Functions Item Unit 0 Counter mode 8 Bits Unit 1 Channel TMR0 Count clock PCLK/1 PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 TMCI0 Counter clear TMR0.TCORA TMR1.TCORA TMR0.TCORA + TMR2.TCORA TMR3.TCORA TMR2.TCORA + TMR1.TCORA TMR3.TCORA TMR0.TCORB TMR1.TCORB TMR0.TCORB + TMR2.TCORB TMR3.TCORB TMR2.TCORB + TMR1.TCORB TMR3.
RX23W Group 26.
RX23W Group 26.
RX23W Group 26. 8-Bit Timer (TMR) Table 26.3 lists the I/O pins of the TMR. Table 26.
RX23W Group 26.2 26. 8-Bit Timer (TMR) Register Descriptions Table 26.4 Register Allocation for 16-Bit Access Address Register Upper 8 Bits Lower 8 Bits 0008 8208h TMR01.TCNT TMR0.TCNT TMR1.TCNT 0008 8204h TMR01.TCORA TMR0.TCORA TMR1.TCORA 0008 8206h TMR01.TCORB TMR0.TCORB TMR1.TCORB 0008 820Ah TMR01.TCCR TMR0.TCCR TMR1.TCCR 0008 8218h TMR23.TCNT TMR2.TCNT TMR3.TCNT 0008 8214h TMR23.TCORA TMR2.TCORA TMR3.TCORA 0008 8216h TMR23.TCORB TMR2.TCORB TMR3.
RX23W Group 26.2.2 26. 8-Bit Timer (TMR) Time Constant Register A (TCORA) Address(es): TMR0.TCORA 0008 8204h, TMR1.TCORA 0008 8205h, TMR2.TCORA 0008 8214h, TMR3.TCORA 0008 8215h, TMR01.TCORA 0008 8204h, TMR23.TCORA 0008 8214h TMR01.TCORA (TMR23.TCORA) TMR0.TCORA (TMR2.TCORA) Value after reset: TMR1.TCORA (TMR3.TCORA) b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 TCORA is an 8-bit readable/writable register. TMR0.TCORA and TMR1.
RX23W Group 26.2.4 26. 8-Bit Timer (TMR) Timer Control Register (TCR) Address(es): TMR0.TCR 0008 8200h, TMR1.TCR 0008 8201h, TMR2.TCR 0008 8210h, TMR3.TCR 0008 8211h b7 b6 b5 CMIEB CMIEA Value after reset: 0 0 b4 OVIE 0 b3 b2 b1 b0 CCLR[1:0] — — — 0 0 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 26.2.5 26. 8-Bit Timer (TMR) Timer Counter Control Register (TCCR) Address(es): TMR0.TCCR 0008 820Ah, TMR1.TCCR 0008 820Bh, TMR2.TCCR 0008 821Ah, TMR3.TCCR 0008 821Bh, TMR01.TCCR 0008 820Ah, TMR23.TCCR 0008 821Ah b7 b6 b5 TMRIS — — CSS[1:0] 0 0 0 0 Value after reset: Bit Symbol b4 b3 0 b2 b1 CKS[2:0] 0 Bit Name Select*1 b0 0 0 Description R/W b2 to b0 CKS[2:0] Clock See Table 26.5. R/W b4, b3 CSS[1:0] Clock Source Select See Table 26.5.
RX23W Group Table 26.5 26. 8-Bit Timer (TMR) Clock Input to TCNT and Count Condition TCCR Register CSS[1:0] CKS[2:0] Channel b4 b3 b2 b1 b0 Description TMR0 (TMR2) 0 0 — 0 0 Clock input prohibited 1 Uses external count clock. Counts at rising edge*1. 0 Uses external count clock. Counts at falling edge*1. 1 Uses external count clock. Counts at both rising and falling edges*1. 0 Uses internal clock. Counts at PCLK. 1 Uses internal clock. Counts at PCLK/2. 0 Uses internal clock.
RX23W Group 26.2.6 26. 8-Bit Timer (TMR) Timer Control/Status Register (TCSR) • TMR0.TCSR, TMR2.TCSR Address(es): TMR0.TCSR 0008 8202h, TMR2.TCSR 0008 8212h Value after reset: b7 b6 b5 b4 b3 b2 — — — — OSB[1:0] OSA[1:0] x x x 0 0 0 0 b1 b0 0 x: Undefined Bit Symbol Bit Name Description R/W b1, b0 OSA[1:0] Output Select A*1 b1 b0 R/W b3, b2 OSB[1:0] Output Select B*1 b3 b2 b4 — Reserved This bit is read as 0. The write value should be 0.
RX23W Group 26. 8-Bit Timer (TMR) • TMR1.TCSR Address(es): TMR1.TCSR 0008 8203h Value after reset: b7 b6 b5 b4 b3 b2 — — — — OSB[1:0] OSA[1:0] x x x 1 0 0 0 b1 b0 0 x: Undefined Bit Symbol Bit Name Description R/W b1, b0 OSA[1:0] Output Select A*1 b1 b0 R/W b3, b2 OSB[1:0] Output Select B*1 b3 b2 b4 — Reserved This bit is read as 1. The write value should be 1. R/W b7 to b5 — Reserved These bits are read as an undefined value. The write value should be 1.
RX23W Group 26.2.7 26. 8-Bit Timer (TMR) Timer Counter Start Register (TCSTR) Address(es): TMR0.TCSTR 0008 820Ch, TMR2.TCSTR 0008 821Ch Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — TCS x x x x x x x 0 x: Undefined Bit Symbol Bit Name Description R/W b0 TCS Timer Counter Status 0: Count stopped state in response to ELC. 1: Count start state in response to ELC. R/W b7 to b1 — Reserved These bits are read as an undefined value.
RX23W Group 26.3 26. 8-Bit Timer (TMR) Operation 26.3.1 Pulse Output Figure 26.3 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. 1. Set the TCR.CCLR[1:0] bits to 01b (cleared by compare match A) so that TCNT is cleared at a compare match of TCORA. 2. Set the TCSR.OSA[1:0] bits to 10b (high is output) and TCSR.OSB[1:0] bits to 01b (low is output), causing the output to change to high at a compare match of TCORA and to low at a compare match of TCORB.
RX23W Group 26.3.2 26. 8-Bit Timer (TMR) External Counter Reset Input Figure 26.4 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRIn input. 1. Set the TCR.CCLR[1:0] bits to 11b (cleared by external counter reset signal) and set the TMRIS bit in TCCR to 1 (cleared when the external counter reset signal is high) so that TCNT is cleared at the high level input of the TMRIn signal. 2. Set the TCSR.
RX23W Group 26.4 26. 8-Bit Timer (TMR) Operation Timing 26.4.1 TCNT Count Timing Figure 26.5 shows the count timing of TCNT for internal clock. Figure 26.6 shows the count timing of TCNT for external clock. Note that the external clock pulse width must be at least 1.5 PCLK cycles for increment at a single edge, and at least 2.5 PCLK cycles for increment at both edges. The counter will not increment correctly if the pulse width is less than these values.
RX23W Group 26.4.2 26. 8-Bit Timer (TMR) Timing of Interrupt Signal Output on a Compare Match A compare match refers to a match between the value of the TCORA or TCORB register and the TCNT, and a compare match interrupt signal is output at this time if the interrupt request is enabled. The compare match is generated in the last cycle in which the values match (at the time at which the value counted by TCNT to produce the match is updated).
RX23W Group 26.4.4 26. 8-Bit Timer (TMR) Timing of Counter Clear by Compare Match TCNT is cleared when compare match A or B occurs, depending on the settings of the TCR.CCLR[1:0] bits. Figure 26.9 shows the timing of this operation. PCLK Compare match signal TCNT Figure 26.9 26.4.5 N 00h Timing of Counter Clear by Compare Match Timing of the External Reset for TCNT TCNT is cleared at the rising edge or high level of an external counter reset signal, depending on the settings of the TCR.
RX23W Group 26.4.6 26. 8-Bit Timer (TMR) Timing of Interrupt Signal Output on an Overflow When TCNT overflows (changes from FFh to 00h), an overflow interrupt signal is output if this interrupt request is enabled. Figure 26.12 shows the timing of output of the interrupt signal. For the corresponding interrupt vector number, refer to section 15, Interrupt Controller (ICUb) and Table 26.6. PCLK TCNT FFh 00h Internal overflow signal OVIn Figure 26.
RX23W Group 26.5 26. 8-Bit Timer (TMR) Operation with Cascaded Connection If the CSS[1:0] bits in either TMR0.TCCR or TMR1.TCCR are set to 11b, the TMR of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of TMR0 could be counted by TMR1 (compare match count mode). This section describes unit 0. When the two units are cascade-connected, the operation of unit 1 differs in some respects from that of unit 0. 26.5.
RX23W Group 26.6 26. 8-Bit Timer (TMR) Interrupt Sources 26.6.1 Interrupt Sources and DTC Activation There are three interrupt sources for TMRn: CMIAn, CMIBn, and OVIn. Their interrupt sources and priorities are listed in Table 26.6. It is also possible to activate the DTC by means of CMIAn and CMIBn interrupts. Table 26.6 TMR Interrupt Sources Name Interrupt Sources DTC Activation CMIA0 TMR0.TCORA compare match Possible CMIB0 TMR0.TCORB compare match Possible OVI0 TMR0.
RX23W Group 26.7 26. 8-Bit Timer (TMR) Link Operation by ELC 26.7.1 Event Signal Output to ELC The TMR uses the event link controller (ELC) to perform link operation to the previously specified module using the interrupt request signal as the event signal. The TMR outputs compare match A, compare match B, and overflow signals as event signals. Channels that can be used in this way are TMR0 and TMR2.
RX23W Group 26.7.3 26. 8-Bit Timer (TMR) Notes on Operating TMR According to an Event Signal from ELC The following describes the notes on operating the TMR using the event link feature. (1) Count Start When the event specified by ELSRn occurs during the write cycle to the TCSTR.TCS bit, the cycle is not completed; setting 1 according to the event occurrence takes priority.
RX23W Group 26.8 26. 8-Bit Timer (TMR) Usage Notes 26.8.1 Module Stop State Setting Operation of the TMR can be disabled or enabled by using the module stop control registers. The initial setting is for halting of TMR operation. Register access becomes possible after release from the module stop state. For details, refer to section 11, Low Power Consumption. 26.8.
RX23W Group 26.8.4 26. 8-Bit Timer (TMR) Conflict between TCNT Write and Increment Even if a counting-up signal is generated concurrently with CPU write to TCNT, the counting-up is not performed and the write takes priority as shown in Figure 26.14. TCNT write by CPU PCLK TCNT count clock TCNT N M TCNT write data Figure 26.14 26.8.
RX23W Group 26.8.6 26. 8-Bit Timer (TMR) Conflict between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output methods high for compare match A and compare match B, as listed in Table 26.7. Table 26.7 Timer Output Priorities Output Setting Priority Toggle output High High output Low output Low No change 26.8.
RX23W Group Table 26.8 No. 3 26. 8-Bit Timer (TMR) Switching of Internal Clocks and TCNT Operation (2/2) Timing to Change the TCCR.CKS[2:0] Bits Switching from high to low*4 TCNT Counter Operation Clock before switching Clock after switching TCNT count clock TCNT N N+1 N+2 N+3 TCCR.CKS[2:0] bits changed 4 Switching from high to high Clock before switching Clock after switching TCNT count clock TCNT N N+1 N+2 TCCR.CKS[2:0] bits changed Note 1. Note 2. Note 3. Note 4.
RX23W Group 26.8.8 26. 8-Bit Timer (TMR) Clock Source Setting with Cascaded Connection If 16-bit counter mode and compare match count mode are specified at the same time, count clocks for TMR0.TCNT and TMR1.TCNT (TMR2.TCNT and TMR3.TCNT) are not generated, and the counter stops. Do not specify 16-bit counter mode and compare match count mode simultaneously. 26.8.
RX23W Group 27. 27. Compare Match Timer (CMT) Compare Match Timer (CMT) This MCU has two on-chip compare match timer (CMT) units (unit 0 and unit 1), each consisting of a two-channel 16-bit timer (i.e., a total of four channels). The CMT has a 16-bit counter, and can generate interrupts at set intervals. In this section, “PCLK” is used to refer to PCLKB. 27.1 Overview Table 27.1 lists the specifications for the CMT. Figure 27.1 shows a block diagram of the CMT (unit 0).
RX23W Group 27.2 27. Compare Match Timer (CMT) Register Descriptions 27.2.1 Compare Match Timer Start Register 0 (CMSTR0) Address(es): 0008 8000h Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — — — — — — — STR1 STR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 STR0 Count Start 0 0: CMT0.CMCNT count is stopped. 1: CMT0.CMCNT count is started.
RX23W Group 27.2.3 27. Compare Match Timer (CMT) Compare Match Timer Control Register (CMCR) Address(es): CMT0.CMCR 0008 8002h, CMT1.CMCR 0008 8008h, CMT2.CMCR 0008 8012h, CMT3.
RX23W Group 27.2.4 27. Compare Match Timer (CMT) Compare Match Counter (CMCNT) Address(es): CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah, CMT2.CMCNT 0008 8014h, CMT3.CMCNT 0008 801Ah Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The CMCNT counter is a readable/writable up-counter. When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTRm.
RX23W Group 27.3 27. Compare Match Timer (CMT) Operation 27.3.1 Periodic Count Operation When an frequency dividing clock is selected by the CMCR.CKS[1:0] bits and the CMSTRm.STRn (m = 0, 1; n = 0 to 3) bit is set to 1, the CMCNT counter starts counting up using the selected clock. When the value in the counter and the value in the register match, a compare match interrupt (CMIn) (n = 0 to 3) is generated. The CMCNT counter then starts counting up again from 0000h. Figure 27.
RX23W Group 27.4 27. Compare Match Timer (CMT) Interrupts 27.4.1 Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt (CMIn) (n = 0 to 3). When a compare match interrupt occurs, the corresponding interrupt request is output. When the interrupt request is used to generate a CPU interrupt, the priority of channels can be changed by the interrupt controller settings. For details, see section 15, Interrupt Controller (ICUb).
RX23W Group 27.5 27. Compare Match Timer (CMT) Link Operations by ELC 27.5.1 Event Signal Output to ELC The CMT uses the event link controller (ELC) to perform link operation to a preset module using the interrupt request signal as the event signal. The CMT outputs the event signal upon a CMT1 compare match. The event signal can be output regardless of the setting of the corresponding interrupt request enable bit (CMTn.CMCR.CMIE). 27.5.
RX23W Group 27.6 27. Compare Match Timer (CMT) Usage Notes 27.6.1 Setting the Module Stop Function The CMT can be enabled or disabled using the module stop control register. After a reset, the CMT is in the module stop state. The registers can be accessed by releasing the module stop state. For details, refer to section 11, Low Power Consumption. 27.6.
RX23W Group 28. 28. Realtime Clock (RTCe) Realtime Clock (RTCe) In this section, “PCLK” is used to refer to PCLKB. 28.1 Overview The RTC has two types of counting modes: calendar count mode and binary count mode. They are used by switching the register settings. For calendar count mode, the RTC has a 100 year calendar from 2000 to 2099 and automatically adjusts dates for leap years.
RX23W Group 28. Realtime Clock (RTCe) Internal peripheral bus Realtime clock (RTC) Bus interface To each function Prescaler RCR2 XCIN Sub-clock oscillator XCOUT 32.
RX23W Group 28.2 28. Realtime Clock (RTCe) Register Descriptions When writing to or reading from RTC registers, do so in accordance with section 28.6.5, Notes on Writing to and Reading from Registers. If the value in an RTC register after a reset is given as x (undefined bits) in the list, it is not initialized by a reset. When RTC enters the reset state or a low power consumption state during counting operations (i.e. while the RCR2.
RX23W Group 28.2.2 (1) 28. Realtime Clock (RTCe) Second Counter (RSECCNT)/Binary Counter 0 (BCNT0) In calendar count mode: Address(es): RTC.RSECCNT 0008 C402h b7 b6 — b4 b3 SEC10[2:0] x Value after reset: b5 x x b2 b1 b0 SEC1[3:0] x x x x x x: Undefined Bit Symbol Bit Name Description R/W b3 to b0 SEC1[3:0] 1-Second Count Counts from 0 to 9 every second. When a carry is generated, 1 is added to the tens place.
RX23W Group 28.2.3 (1) 28. Realtime Clock (RTCe) Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1) In calendar count mode: Address(es): RTC.RMINCNT 0008 C404h b7 b6 — x Value after reset: b5 b4 b3 MIN10[2:0] x x b2 b1 b0 MIN1[3:0] x x x x x x: Undefined Bit Symbol Bit Name Description R/W b3 to b0 MIN1[3:0] 1-Minute Count Counts from 0 to 9 every minute. When a carry is generated, 1 is added to the tens place.
RX23W Group 28.2.4 (1) 28. Realtime Clock (RTCe) Hour Counter (RHRCNT)/Binary Counter 2 (BCNT2) In calendar count mode: Address(es): RTC.RHRCNT 0008 C406h Value after reset: b7 b6 b5 b4 — PM HR10[1:0] x x x x b3 b2 b1 b0 HR1[3:0] x x x x x: Undefined Bit Symbol Bit Name Description R/W b3 to b0 HR1[3:0] 1-Hour Count Counts from 0 to 9 once per hour. When a carry is generated, 1 is added to the tens place.
RX23W Group 28.2.5 (1) 28. Realtime Clock (RTCe) Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3) In calendar count mode: Address(es): RTC.RWKCNT 0008 C408h Value after reset: b7 b6 b5 b4 b3 — — — — — x x x x x b2 b1 b0 DAYW[2:0] x x x x: Undefined Bit Symbol Bit Name Description R/W b2 to b0 DAYW[2:0] Day-of-Week Counting b2 R/W b7 to b3 — Reserved Set these bits to 0. They are read as the set value.
RX23W Group 28.2.6 28. Realtime Clock (RTCe) Date Counter (RDAYCNT) Address(es): RTC.RDAYCNT 0008 C40Ah Value after reset: b7 b6 — — 0 0 b5 b4 b3 DATE10[1:0] x x b2 b1 b0 DATE1[3:0] x x x x x: Undefined Bit Symbol Bit Name Description R/W b3 to b0 DATE1[3:0] 1-Day Count Counts from 0 to 9 once per day. When a carry is generated, 1 is added to the tens place. R/W b5, b4 DATE10[1:0] 10-Day Count Counts from 0 to 3 once per carry from the ones place.
RX23W Group 28.2.7 28. Realtime Clock (RTCe) Month Counter (RMONCNT) Address(es): RTC.RMONCNT 0008 C40Ch Value after reset: b7 b6 b5 b4 — — — MON10 0 0 0 x b3 b2 b1 b0 MON1[3:0] x x x x x: Undefined Bit Symbol Bit Name Description R/W b3 to b0 MON1[3:0] 1-Month Count Counts from 0 to 9 once per month. When a carry is generated, 1 is added to the tens place. R/W b4 MON10 10-Month Count Counts from 0 to 1 once per carry from the ones place.
RX23W Group 28.2.8 28. Realtime Clock (RTCe) Year Counter (RYRCNT) Address(es): RTC.RYRCNT 0008 C40Eh Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 — — — — — — — — 0 0 0 0 0 0 0 0 b7 b6 b5 b4 b3 YR10[3:0] x x x b2 b1 b0 YR1[3:0] x x x x x x: Undefined Bit Symbol Bit Name Description R/W b3 to b0 YR1[3:0] 1-Year Count Counts from 0 to 9 once per year. When a carry is generated, 1 is added to the tens place.
RX23W Group 28.2.9 (1) 28. Realtime Clock (RTCe) Second Alarm Register (RSECAR)/Binary Counter 0 Alarm Register (BCNT0AR) In calendar count mode: Address(es): RTC.
RX23W Group 28.2.10 (1) 28. Realtime Clock (RTCe) Minute Alarm Register (RMINAR)/Binary Counter 1 Alarm Register (BCNT1AR) In calendar count mode: Address(es): RTC.
RX23W Group 28.2.11 (1) 28. Realtime Clock (RTCe) Hour Alarm Register (RHRAR)/Binary Counter 2 Alarm Register (BCNT2AR) In calendar count mode: Address(es): RTC.
RX23W Group 28.2.12 (1) 28. Realtime Clock (RTCe) Day-of-Week Alarm Register (RWKAR)/Binary Counter 3 Alarm Register (BCNT3AR) In calendar count mode: Address(es): RTC.
RX23W Group 28.2.13 (1) 28. Realtime Clock (RTCe) Date Alarm Register (RDAYAR)/Binary Counter 0 Alarm Enable Register (BCNT0AER) In calendar count mode: Address(es): RTC.
RX23W Group 28.2.14 (1) 28. Realtime Clock (RTCe) Month Alarm Register (RMONAR)/Binary Counter 1 Alarm Enable Register (BCNT1AER) In calendar count mode: Address(es): RTC.
RX23W Group 28.2.15 (1) 28. Realtime Clock (RTCe) Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register (BCNT2AER) In calendar count mode: Address(es): RTC.
RX23W Group 28.2.16 (1) 28. Realtime Clock (RTCe) Year Alarm Enable Register (RYRAREN)/Binary Counter 3 Alarm Enable Register (BCNT3AER) In calendar count mode: Address(es): RTC.RYRAREN 0008 C41Eh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ENB — — — — — — — x x x x x x x x x: Undefined Bit Symbol Bit Name Description R/W b6 to b0 — Reserved Set these bits to 0. They are read as the set value.
RX23W Group 28.2.17 28. Realtime Clock (RTCe) RTC Control Register 1 (RCR1) Address(es): RTC.RCR1 0008 C422h b7 b6 b5 b4 PES[3:0] x Value after reset: x x b3 b2 b1 b0 RTCOS PIE CIE AIE 0 x 0 x x x: Undefined Bit Symbol Bit Name Description R/W b0 AIE Alarm Interrupt Enable 0: An alarm interrupt request is disabled. 1: An alarm interrupt request is enabled. R/W b1 CIE Carry Interrupt Enable 0: A carry interrupt request is disabled.
RX23W Group 28.2.18 28. Realtime Clock (RTCe) RTC Control Register 2 (RCR2) Address(es): RTC.RCR2 0008 C424h b7 CNTM D Value after reset: x b6 b5 b4 b3 b2 b1 b0 HR24 AADJP AADJE RTCOE ADJ30 RESET START x x x 0 0 0 x x: Undefined Bit Symbol Bit Name Description R/W b0 START Start*3 0: Prescaler and counter are stopped. 1: Prescaler and counter operate normally. R/W b1 RESET RTC Software Reset • In writing 0: Writing is invalid.
RX23W Group 28. Realtime Clock (RTCe) RESET Bit (RTC Software Reset) This bit initializes the prescaler and registers to be reset by RTC software reset. When 1 is written to the RESET bit, the initialization starts in synchronization with the count source. When the initialization is completed, the RESET bit is automatically set to 0. When 1 is written to the RESET bit, check that the bit is set to 0, and then make next settings. ADJ30 Bit (30-Second Adjustment) This bit is for 30-second adjustment.
RX23W Group 28.2.19 28. Realtime Clock (RTCe) RTC Control Register 3 (RCR3) Address(es): RTC.RCR3 0008 C426h Value after reset: b7 b6 b5 b4 — — — — 0 0 0 0 b3 b2 b1 b0 RTCDV[2:0] x x RTCEN x x x: Undefined Bit Symbol Bit Name Description R/W b0 RTCEN Sub-Clock Oscillator Control 0: Sub-clock oscillator is stopped. 1: Sub-clock oscillator is operating.
RX23W Group 28.2.20 28. Realtime Clock (RTCe) Time Error Adjustment Register (RADJ) Address(es): RTC.RADJ 0008 C42Eh b7 b6 b5 b4 PMADJ[1:0] Value after reset: x x b3 b2 b1 b0 x x ADJ[5:0] x x x x x: Undefined Bit Symbol Bit Name Description R/W b5 to b0 ADJ[5:0] Adjustment Value These bits specify the adjustment value from the prescaler. R/W b7, b6 PMADJ[1:0] Plus–Minus b7 b6 R/W 0 0 1 1 0: Adjustment is not performed.
RX23W Group 28.2.21 28. Realtime Clock (RTCe) Time Capture Control Register n (RTCCRn) (n = 0, 1) Address(es): RTC.RTCCR0 0008 C440h, RTC.RTCCR1 0008 C442h b7 b6 b5 b4 b3 b2 TCEN — TCNF[1:0] — TCST x x x x x Value after reset: x b1 b0 TCCT[1:0] x x x: Undefined Bit Symbol Bit Name Description R/W b1, b0 TCCT[1:0] Time Capture Control b1 b0 R/W b2 TCST Time Capture Status 0: No event is detected. 1: An event is detected.*1 R/W b3 — Reserved This bit is read as 0.
RX23W Group 28. Realtime Clock (RTCe) TCNF[1:0] Bits (Time Capture Noise Filter Control) These bits control the noise filter of the time capture event input pins (RTCIC0 and RTCIC1). When the noise filter is on, the count source divided by 1 or divided by 32 is selectable. In this case, when the input level on the time capture event input pin matches three consecutive times at the set sampling period, the input level is determined.
RX23W Group 28.2.22 (1) 28. Realtime Clock (RTCe) Second Capture Register n (RSECCPn) (n = 0, 1)/BCNT0 Capture Register n (BCNT0CPn) (n = 0, 1) In calendar count mode: Address(es): RTC.RSECCP0 0008 C452h, RTC.
RX23W Group 28.2.23 (1) 28. Realtime Clock (RTCe) Minute Capture Register n (RMINCPn) (n = 0, 1)/BCNT1 Capture Register n (BCNT1CPn) (n = 0, 1) In calendar count mode: Address(es): RTC.RMINCP0 0008 C454h, RTC.
RX23W Group 28.2.24 (1) 28. Realtime Clock (RTCe) Hour Capture Register n (RHRCPn) (n = 0, 1)/BCNT2 Capture Register n (BCNT2CPn) (n = 0, 1) In calendar count mode: Address(es): RTC.RHRCP0 0008 C456h, RTC.
RX23W Group 28.2.25 (1) 28. Realtime Clock (RTCe) Date Capture Register n (RDAYCPn) (n = 0, 1)/BCNT3 Capture Register n (BCNT3CPn) (n = 0, 1) In calendar count mode: Address(es): RTC.RDAYCP0 0008 C45Ah, RTC.
RX23W Group 28.2.26 28. Realtime Clock (RTCe) Month Capture Register n (RMONCPn) (n = 0, 1) Address(es): RTC.RMONCP0 0008 C45Ch, RTC.
