RX23W Group 36. CAN Module (RSCAN) Internal peripheral bus CAN-related registers CRXD0 Protocol controller CTXD0 Receive rule table RAM Acceptance filter FIFO RAM ID priority transmit controller fCANTQ Timer Buffer RAM Baud rate prescaler (BRP[9:0]) Peripheral module clock (PCLK) DCS fCAN Global receive FIFO interrupt 1/2 Main clock (CANMCLK) Global error interrupt Interrupt generator Channel transmit interrupt Transmit/receive FIFO receive interrupt BRP[9:0]: DCS: fCANTQ: fCAN: Figure 36.
RX23W Group 36.2 36. CAN Module (RSCAN) Register Descriptions 36.2.1 Bit Configuration Register L (CFGL) Address(es): RSCAN0.CFGL 000A 8300h b15 b14 b13 b12 b11 b10 — — — — — — 0 0 0 0 0 0 Value after reset: b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 BRP[9:0] 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b9 to b0 BRP[9:0] Prescaler Division Ratio Set When these bits are set to P (0 to 1023), the baud rate prescaler divides fCAN by P + 1.
RX23W Group 36.2.2 36. CAN Module (RSCAN) Bit Configuration Register H (CFGH) Address(es): RSCAN0.
RX23W Group 36. CAN Module (RSCAN) SJW[1:0] Bits (Resynchronization Jump Width Control) These bits are used to specify a Tq value for the resynchronization jump width. A value of 1 Tq to 4 Tq can be set. Set a value equal to or smaller than the value of the TSEG2[3:0] bits. 36.2.3 Control Register L (CTRL) Address(es): RSCAN0.
RX23W Group 36. CAN Module (RSCAN) RTBO Bit (Forcible Return from Bus-off) Setting this bit to 1 (forcible return from the bus off state) in the bus off state forcibly returns the state from the bus off state to the error active state. This bit is automatically set to 0. Setting this bit to 1 sets the STSH.TEC[7:0] and STSH.REC[7:0] flags to 00h and also sets the STSL.BOSTS flag to 0 (not in bus off state).The other registers remain unchanged.
RX23W Group 36.2.4 36. CAN Module (RSCAN) Control Register H (CTRH) Address(es): RSCAN0.CTRH 000A 8306h b15 b14 b13 b12 b11 — — — — — CTMS[1:0] 0 0 0 0 0 0 Value after reset: b10 b9 b8 b7 CTME ERRD 0 0 0 b6 b5 b4 b3 b2 b1 b0 BOM[1:0] — — — — TAIE 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 TAIE Transmit Abort Interrupt Enable 0: Transmit abort interrupt is disabled. 1: Transmit abort interrupt is enabled.
RX23W Group 36. CAN Module (RSCAN) bus off state before the CTRL.CHMDC[1:0] bits are set to 10b, a bus off recovery interrupt request is generated. If the CPU requests transition to channel reset mode at the same time when the CAN module transitions to channel halt mode (at bus off entry when the BOM[1:0] bits are 01b or at bus off end when the BOM[1:0] bits are 10b), the CPU’s request takes precedence. Modify these bits only in channel reset mode.
RX23W Group 36.2.5 36. CAN Module (RSCAN) Status Register L (STSL) Address(es): RSCAN0.
RX23W Group 36. CAN Module (RSCAN) TRMSTS Flag (Transmit Status Flag) This flag becomes 1 when transmission has started, and becomes 0 when the bus has become idle or reception has started. This flag remains 1 in the bus off state. RECSTS Flag (Receive Status Flag) This flag becomes 1 when reception has started, and becomes 0 when the bus has become idle or transmission has started. COMSTS Flag (Communication Status Flag) This flag indicates that communication is ready.
RX23W Group 36.2.7 36. CAN Module (RSCAN) Error Flag Register L (ERFLL) Address(es): RSCAN0.ERFLL 000A 830Ch b15 — b14 b12 b11 ADERR B0ERR B1ERR CERR 0 Value after reset: b13 0 0 0 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 AERR FERR SERR ALF BLF OVLF BORF BOEF EPF EWF BEF 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 BEF Bus Error Flag 0: No channel bus error is detected. 1: Channel bus error is detected.
RX23W Group 36. CAN Module (RSCAN) EWF Flag (Error Warning Flag) This flag becomes 1 only when the STSH.REC[7:0] or STSH.TEC[7:0] value exceeds 95 for the first time. Therefore, if the program writes 0 to this flag with the STSH.REC[7:0] or STSH.TEC [7:0] value remaining over 95, this bit is not set to 1 until both STSH.REC[7:0] and STSH.TEC[7:0] values become 95 or less and then the STSH.REC[7:0] or STSH.TEC[7:0] value exceeds 95 again.
RX23W Group 36. CAN Module (RSCAN) AERR Flag (ACK Error Flag) This flag becomes 1 when an ACK error has been detected. CERR Flag (CRC Error Flag) This flag becomes 1 when a CRC error has been detected. B1ERR Flag (Recessive Bit Error Flag) This flag becomes 1 when a dominant bit has been detected though a recessive bit was transmitted. B0ERR Flag (Dominant Bit Error Flag) This flag becomes 1 when a recessive bit has been detected though a dominant bit was transmitted.
RX23W Group 36.2.9 36. CAN Module (RSCAN) Global Configuration Register L (GCFGL) Address(es): RSCAN.GCFGL 000A 8322h b15 b14 b13 b12 — — — TSSS 0 0 0 0 Value after reset: b11 b10 b9 b8 TSP[3:0] 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — — DCS MME DRE DCE TPRI 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 TPRI Transmit Priority Select 0: ID priority 1: Transmit buffer number priority R/W b1 DCE DLC Check Enable 0: DLC check is disabled.
RX23W Group 36. CAN Module (RSCAN) DRE Bit (DLC Replacement Enable) When the DRE bit is set to 1, the DLC value of the receive rule is stored in the buffer instead of the DLC value of the received message after the DLC value has passed through the DLC filter. In this case, a value of 00h is stored in the data byte that exceeds the DLC value of the receive rule. When the DCE bit is set to 1 (DLC check is enabled), the DLC replacement function is available.
RX23W Group 36.2.11 36. CAN Module (RSCAN) Global Control Register L (GCTRL) Address(es): RSCAN.
RX23W Group 36.2.12 36. CAN Module (RSCAN) Global Control Register H (GCTRH) Address(es): RSCAN.GCTRH 000A 8328h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — — — — — — — — TSRST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b0 TSRST Timestamp Counter Reset Setting the TSRST bit to 1 resets the timestamp counter. This bit is read as 0.
RX23W Group 36. CAN Module (RSCAN) has returned from global stop mode. GRAMINIT Flag (CAN RAM Initialization Status Flag) This flag indicates the initialization status of the CAN RAM. This flag becomes 1 after the CAN module is enabled, and becomes 0 when CAN RAM initialization is completed. 36.2.14 Global Error Flag Register (GERFLL) Address(es): RSCAN.
RX23W Group 36.2.15 36. CAN Module (RSCAN) Global Transmit Interrupt Status Register (GTINTSTS) Address(es): RSCAN.GTINTSTS 000A 8388h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 — — — — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: b3 b2 b1 THIF0 CFTIF0 TAIF0 0 0 b0 TSIF0 0 0 Bit Symbol Bit Name Description R/W b0 TSIF0 RSCAN0 Transmit Buffer Interrupt Status Flag 0: No transmit buffer transmit complete interrupt request is present.
RX23W Group 36.2.16 36. CAN Module (RSCAN) Timestamp Register (GTSC) Address(es): RSCAN.GTSC 000A 832Eh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 TS[15:0] 0 Value after reset: 0 0 0 0 0 0 0 0 Bit Symbol Description Counter Value R/W b15 to b0 TS[15:0] The timestamp counter value can be read. 0000h to FFFFh R When the TS[15:0] bits are read, the read value shows the timestamp counter (16-bit free-running counter) value at that time.
RX23W Group 36.2.18 36. CAN Module (RSCAN) Receive Rule Entry Register jAL (GAFLIDLj) (j = 0 to 15) Address(es): RSCAN.GAFLIDL0 000A 83A0h, RSCAN.GAFLIDL1 000A 83ACh, RSCAN.GAFLIDL2 000A 83B8h, RSCAN.GAFLIDL3 000A 83C4h, RSCAN.GAFLIDL4 000A 83D0h, RSCAN.GAFLIDL5 000A 83DCh, RSCAN.GAFLIDL6 000A 83E8h, RSCAN.GAFLIDL7 000A 83F4h, RSCAN.GAFLIDL8 000A 8400h, RSCAN.GAFLIDL9 000A 840Ch, RSCAN.GAFLIDL10 000A 8418h, RSCAN.GAFLIDL11 000A 8424h, RSCAN.GAFLIDL12 000A 8430h, RSCAN.GAFLIDL13 000A 843Ch, RSCAN.
RX23W Group 36.2.19 36. CAN Module (RSCAN) Receive Rule Entry Register jAH (GAFLIDHj) (j = 0 to 15) Address(es): RSCAN.GAFLIDH0 000A 83A2h, RSCAN.GAFLIDH1 000A 83AEh, RSCAN.GAFLIDH2 000A 83BAh, RSCAN.GAFLIDH3 000A 83C6h, RSCAN.GAFLIDH4 000A 83D2h, RSCAN.GAFLIDH5 000A 83DEh, RSCAN.GAFLIDH6 000A 83EAh, RSCAN.GAFLIDH7 000A 83F6h, RSCAN.GAFLIDH8 000A 8402h, RSCAN.GAFLIDH9 000A 840Eh, RSCAN.GAFLIDH10 000A 841Ah, RSCAN.GAFLIDH11 000A 8426h, RSCAN.GAFLIDH12 000A 8432h, RSCAN.GAFLIDH13 000A 843Eh, RSCAN.
RX23W Group 36.2.20 36. CAN Module (RSCAN) Receive Rule Entry Register jBL (GAFLMLj) (j = 0 to 15) Address(es): RSCAN.GAFLML0 000A 83A4h, RSCAN.GAFLML1 000A 83B0h, RSCAN.GAFLML2 000A 83BCh, RSCAN.GAFLML3 000A 83C8h, RSCAN.GAFLML4 000A 83D4h, RSCAN.GAFLML5 000A 83E0h, RSCAN.GAFLML6 000A 83ECh, RSCAN.GAFLML7 000A 83F8h, RSCAN.GAFLML8 000A 8404h, RSCAN.GAFLML9 000A 8410h, RSCAN.GAFLML10 000A 841Ch, RSCAN.GAFLML11 000A 8428h, RSCAN.GAFLML12 000A 8434h, RSCAN.GAFLML13 000A 8440h, RSCAN.
RX23W Group 36.2.21 36. CAN Module (RSCAN) Receive Rule Entry Register jBH (GAFLMHj) (j = 0 to 15) Address(es): RSCAN.GAFLMH0 000A 83A6h, RSCAN.GAFLMH1 000A 83B2h, RSCAN.GAFLMH2 000A 83BEh, RSCAN.GAFLMH3 000A 83CAh, RSCAN.GAFLMH4 000A 83D6h, RSCAN.GAFLMH5 000A 83E2h, RSCAN.GAFLMH6 000A 83EEh, RSCAN.GAFLMH7 000A 83FAh, RSCAN.GAFLMH8 000A 8406h, RSCAN.GAFLMH9 000A 8412h, RSCAN.GAFLMH10 000A 841Eh, RSCAN.GAFLMH11 000A 842Ah, RSCAN.GAFLMH12 000A 8436h, RSCAN.GAFLMH13 000A 8442h, RSCAN.
RX23W Group 36.2.22 36. CAN Module (RSCAN) Receive Rule Entry Register jCL (GAFLPLj) (j = 0 to 15) Address(es): RSCAN.GAFLPL0 000A 83A8h, RSCAN.GAFLPL1 000A 83B4h, RSCAN.GAFLPL2 000A 83C0h, RSCAN.GAFLPL3 000A 83CCh, RSCAN.GAFLPL4 000A 83D8h, RSCAN.GAFLPL5 000A 83E4h, RSCAN.GAFLPL6 000A 83F0h, RSCAN.GAFLPL7 000A 83FCh, RSCAN.GAFLPL8 000A 8408h, RSCAN.GAFLPL9 000A 8414h, RSCAN.GAFLPL10 000A 8420h, RSCAN.GAFLPL11 000A 842Ch, RSCAN.GAFLPL12 000A 8438h, RSCAN.GAFLPL13 000A 8444h, RSCAN.
RX23W Group 36.2.23 36. CAN Module (RSCAN) Receive Rule Entry Register jCH (GAFLPHj) (j = 0 to 15) Address(es): RSCAN.GAFLPH0 000A 83AAh, RSCAN.GAFLPH1 000A 83B6h, RSCAN.GAFLPH2 000A 83C2h, RSCAN.GAFLPH3 000A 83CEh, RSCAN.GAFLPH4 000A 83DAh, RSCAN.GAFLPH5 000A 83E6h, RSCAN.GAFLPH6 000A 83F2h, RSCAN.GAFLPH7 000A 83FEh, RSCAN.GAFLPH8 000A 840Ah, RSCAN.GAFLPH9 000A 8416h, RSCAN.GAFLPH10 000A 8422h, RSCAN.GAFLPH11 000A 842Eh, RSCAN.GAFLPH12 000A 843Ah, RSCAN.GAFLPH13 000A 8446h, RSCAN.
RX23W Group 36.2.24 36. CAN Module (RSCAN) Receive Buffer Number Configuration Register (RMNB) Address(es): RSCAN.RMNB 000A 8332h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 — — — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 Value after reset: b4 b3 b2 b1 b0 0 0 NRXMB[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 NRXMB[4:0] Receive Buffer Number Configuration Set the number of receive buffers. Set a value of 0 to 16.
RX23W Group 36.2.26 36. CAN Module (RSCAN) Receive Buffer Register nAL (RMIDLn) (n = 0 to 15) Address(es): RSCAN.RMIDL0 000A 83A0h, RSCAN.RMIDL1 000A 83B0h, RSCAN.RMIDL2 000A 83C0h, RSCAN.RMIDL3 000A 83D0h, RSCAN.RMIDL4 000A 83E0h, RSCAN.RMIDL5 000A 83F0h, RSCAN.RMIDL6 000A 8400h, RSCAN.RMIDL7 000A 8410h, RSCAN.RMIDL8 000A 8420h, RSCAN.RMIDL9 000A 8430h, RSCAN.RMIDL10 000A 8440h, RSCAN.RMIDL11 000A 8450h, RSCAN.RMIDL12 000A 8460h, RSCAN.RMIDL13 000A 8470h, RSCAN.RMIDL14 000A 8480h, RSCAN.
RX23W Group 36.2.27 36. CAN Module (RSCAN) Receive Buffer Register nAH (RMIDHn) (n = 0 to 15) Address(es): RSCAN.RMIDH0 000A 83A2h, RSCAN.RMIDH1 000A 83B2h, RSCAN.RMIDH2 000A 83C2h, RSCAN.RMIDH3 000A 83D2h, RSCAN.RMIDH4 000A 83E2h, RSCAN.RMIDH5 000A 83F2h, RSCAN.RMIDH6 000A 8402h, RSCAN.RMIDH7 000A 8412h, RSCAN.RMIDH8 000A 8422h, RSCAN.RMIDH9 000A 8432h, RSCAN.RMIDH10 000A 8442h, RSCAN.RMIDH11 000A 8452h, RSCAN.RMIDH12 000A 8462h, RSCAN.RMIDH13 000A 8472h, RSCAN.RMIDH14 000A 8482h, RSCAN.
RX23W Group 36.2.28 36. CAN Module (RSCAN) Receive Buffer Register nBL (RMTSn) (n = 0 to 15) Address(es): RSCAN.RMTS0 000A 83A4h, RSCAN.RMTS1 000A 83B4h, RSCAN.RMTS2 000A 83C4h, RSCAN.RMTS3 000A 83D4h, RSCAN.RMTS4 000A 83E4h, RSCAN.RMTS5 000A 83F4h, RSCAN.RMTS6 000A 8404h, RSCAN.RMTS7 000A 8414h, RSCAN.RMTS8 000A 8424h, RSCAN.RMTS9 000A 8434h, RSCAN.RMTS10 000A 8444h, RSCAN.RMTS11 000A 8454h, RSCAN.RMTS12 000A 8464h, RSCAN.RMTS13 000A 8474h, RSCAN.RMTS14 000A 8484h, RSCAN.
RX23W Group 36.2.29 36. CAN Module (RSCAN) Receive Buffer Register nBH (RMPTRn) (n = 0 to 15) Address(es): RSCAN.RMPTR0 000A 83A6h, RSCAN.RMPTR1 000A 83B6h, RSCAN.RMPTR2 000A 83C6h, RSCAN.RMPTR3 000A 83D6h, RSCAN.RMPTR4 000A 83E6h, RSCAN.RMPTR5 000A 83F6h, RSCAN.RMPTR6 000A 8406h, RSCAN.RMPTR7 000A 8416h, RSCAN.RMPTR8 000A 8426h, RSCAN.RMPTR9 000A 8436h, RSCAN.RMPTR10 000A 8446h, RSCAN.RMPTR11 000A 8456h, RSCAN.RMPTR12 000A 8466h, RSCAN.RMPTR13 000A 8476h, RSCAN.RMPTR14 000A 8486h, RSCAN.
RX23W Group 36.2.30 36. CAN Module (RSCAN) Receive Buffer Register nCL (RMDF0n) (n = 0 to 15) Address(es): RSCAN.RMDF00 000A 83A8h, RSCAN.RMDF01 000A 83B8h, RSCAN.RMDF02 000A 83C8h, RSCAN.RMDF03 000A 83D8h, RSCAN.RMDF04 000A 83E8h, RSCAN.RMDF05 000A 83F8h, RSCAN.RMDF06 000A 8408h, RSCAN.RMDF07 000A 8418h, RSCAN.RMDF08 000A 8428h, RSCAN.RMDF09 000A 8438h, RSCAN.RMDF010 000A 8448h, RSCAN.RMDF011 000A 8458h, RSCAN.RMDF012 000A 8468h, RSCAN.RMDF013 000A 8478h, RSCAN.RMDF014 000A 8488h, RSCAN.
RX23W Group 36.2.32 36. CAN Module (RSCAN) Receive Buffer Register nDL (RMDF2n) (n = 0 to 15) Address(es): RSCAN.RMDF20 000A 83ACh, RSCAN.RMDF21 000A 83BCh, RSCAN.RMDF22 000A 83CCh, RSCAN.RMDF23 000A 83DCh, RSCAN.RMDF24 000A 83ECh, RSCAN.RMDF25 000A 83FCh, RSCAN.RMDF26 000A 840Ch, RSCAN.RMDF27 000A 841Ch, RSCAN.RMDF28 000A 842Ch, RSCAN.RMDF29 000A 843Ch, RSCAN.RMDF210 000A 844Ch, RSCAN.RMDF211 000A 845Ch, RSCAN.RMDF212 000A 846Ch, RSCAN.RMDF213 000A 847Ch, RSCAN.RMDF214 000A 848Ch, RSCAN.
RX23W Group 36.2.34 36. CAN Module (RSCAN) Receive FIFO Control Register m (RFCCm) (m = 0, 1) Address(es): RSCAN.RFCC0 000A 8338h, RSCAN.RFCC1 000A 833Ah b15 b14 b13 RFIGCV[2:0] 0 Value after reset: 0 0 b12 b11 RFIM — 0 0 b10 b9 b8 RFDC[2:0] 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — RFIE RFE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 RFE Receive FIFO Buffer Enable 0: No receive FIFO buffer is used. 1: Receive FIFO buffers are used.
RX23W Group 36. CAN Module (RSCAN) RFIGCV[2:0] Bits (Receive FIFO Interrupt Request Timing Select) These bits are used to specify the fraction of the transmit/receive FIFO buffer (the number of messages is selected by the setting of the RFDC[2:0] bits) that must be filled for the FIFO buffer to generate a receive interrupt request when the RFIM bit is set to 0. When the RFDC[2:0] bits are set to 001b (4 messages), set the RFIGCV[2:0] bits to 001b, 011b, 101b, or 111b.
RX23W Group 36. CAN Module (RSCAN) RFIF Flag (Receive FIFO Interrupt Request Flag) This flag becomes 1 when the receive FIFO interrupt request generation conditions set by the RFCCm.RFIGCV[2:0] bits (m = 0, 1) and the RFCCm.RFIM bit are met. This flag becomes 0 in global reset mode or by writing 0 to this flag. Modify this bit only in global operating mode or global test mode.
RX23W Group 36.2.37 36. CAN Module (RSCAN) Receive FIFO Access Register mAL (RFIDLm) (m = 0, 1) Address(es): RSCAN.RFIDL0 000A 85A0h, RSCAN.RFIDL1 000A 85B0h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 RFID[15:0] 0 Value after reset: 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b15 to b0 RFID[15:0] Receive FIFO Buffer ID Data L The standard ID or extended ID of received message can be read. Read bits 10 to 0 for standard ID.
RX23W Group 36.2.39 36. CAN Module (RSCAN) Receive FIFO Access Register mBL (RFTSm) (m = 0, 1) Address(es): RSCAN.RFTS0 000A 85A4h, RSCAN.RFTS1 000A 85B4h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 RFTS[15:0] Value after reset: 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b15 to b0 RFTS[15:0] Receive FIFO Buffer Timestamp Data Timestamp value of the received message can be read. R This register can be read when the GRWCR.
RX23W Group 36.2.41 36. CAN Module (RSCAN) Receive FIFO Access Register mCL (RFDF0m) (m = 0, 1) Address(es): RSCAN.RFDF00 000A 85A8h, RSCAN.
RX23W Group 36.2.43 36. CAN Module (RSCAN) Receive FIFO Access Register mDL (RFDF2m) (m = 0, 1) Address(es): RSCAN.RFDF20 000A 85ACh, RSCAN.
RX23W Group 36.2.45 36. CAN Module (RSCAN) Transmit/Receive FIFO Control Register 0L (CFCCL0) Address(es): RSCAN0.CFCCL0 000A 8350h b15 b14 b13 CFIGCV[2:0] 0 Value after reset: 0 0 b12 b11 CFIM — 0 0 b10 b9 b8 CFDC[2:0] 0 0 0 b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 CFTXIE CFRXI E 0 0 b0 CFE 0 Bit Symbol Bit Name Description R/W b0 CFE Transmit/Receive FIFO Buffer Enable 0: No transmit/receive FIFO buffer is used. 1: Transmit/receive FIFO buffers are used.
RX23W Group 36. CAN Module (RSCAN) This bit is set to 0 when the following conditions are met. • Receive mode: Global reset mode • Transmit mode: Channel reset mode Modify this bit only in the following mode. • Receive mode: Global operating mode or global test mode • Transmit mode: Channel communication mode or channel halt mode CFRXIE Bit (Transmit/Receive FIFO Receive Interrupt Enable) When the CFSTS0.
RX23W Group 36.2.46 36. CAN Module (RSCAN) Transmit/Receive FIFO Control Register 0H (CFCCH0) Address(es): RSCAN0.
RX23W Group 36.2.47 36. CAN Module (RSCAN) Transmit/Receive FIFO Status Register 0 (CFSTS0) Address(es): RSCAN0.CFSTS0 000A 8358h b15 b14 — — 0 0 Value after reset: b13 b12 b11 b10 b9 b8 CFMC[5:0] 0 0 0 0 0 0 b7 b6 b5 — — — 0 0 0 b4 b3 b2 b1 b0 CFTXIF CFRXI CFMLT CFFLL CFEMP F 0 0 0 0 1 Bit Symbol Bit Name Description R/W b0 CFEMP Transmit/Receive FIFO Buffer Empty Status Flag 0: The transmit/receive FIFO buffer contains messages.
RX23W Group 36. CAN Module (RSCAN) • When the CFCCL0.CFE value is 0 (no transmit/receive FIFO buffer is used). Note that this flag becomes 0 after transmission completion, CAN bus error detection, or arbitration lost when the message in the transmit/receive FIFO buffer is being transmitted or to be transmitted next. • When CFCCH0.CFM[1:0] value is 00b: In global reset mode • When CFCCH0.
RX23W Group 36.2.48 36. CAN Module (RSCAN) Transmit/Receive FIFO Pointer Control Register 0 (CFPCTR0) Address(es): RSCAN0.
RX23W Group 36.2.49 36. CAN Module (RSCAN) Transmit/Receive FIFO Access Register 0AL (CFIDL0) Address(es): RSCAN0.CFIDL0 000A 85E0h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 CFID[15:0] Value after reset: 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b15 to b0 CFID[15:0] Transmit/Receive FIFO Buffer ID Data L When CFCCH0.CFM[1:0] value is 01b (transmit mode): Set standard ID or extended ID.
RX23W Group 36.2.50 36. CAN Module (RSCAN) Transmit/Receive FIFO Access Register 0AH (CFIDH0) Address(es): RSCAN0.CFIDH0 000A 85E2h b15 b14 b13 b12 b11 b10 b9 b8 b7 CFIDE CFRTR THLEN Value after reset: 0 0 0 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 CFID[28:16] 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b12 to b0 CFID[28:16] Transmit/Receive FIFO Buffer ID Data H When CFCCH0.CFM[1:0] value is 01b (transmit mode): Set standard ID or extended ID.
RX23W Group 36.2.51 36. CAN Module (RSCAN) Transmit/Receive FIFO Access Register 0BL (CFTS0) Address(es): RSCAN0.CFTS0 000A 85E4h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 CFTS[15:0] Value after reset: 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b15 to b0 CFTS[15:0] Transmit/Receive FIFO Buffer Timestamp Data These bits are valid only when the CFCCH0.CFM[1:0] value is 00b (receive mode).
RX23W Group 36.2.52 36. CAN Module (RSCAN) Transmit/Receive FIFO Access Register 0BH (CFPTR0) Address(es): RSCAN0.CFPTR0 000A 85E6h b15 b14 b13 b12 b11 b10 b9 b8 b7 CFDLC[3:0] Value after reset: 0 0 0 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 CFPTR[11:0] 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b11 to b0 CFPTR[11:0] Transmit/Receive FIFO Buffer Label Data When CFCCH0.
RX23W Group 36.2.53 36. CAN Module (RSCAN) Transmit/Receive FIFO Access Register 0CL (CFDF00) Address(es): RSCAN0.CFDF00 000A 85E8h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 CFDB1[7:0] Value after reset: 0 0 0 0 0 b4 b3 b2 b1 b0 0 0 0 CFDB0[7:0] 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 CFDB0[7:0] Transmit/Receive FIFO Buffer Data Byte 0 R/W b15 to b8 CFDB1[7:0] Transmit/Receive FIFO Buffer Data Byte 1 When CFCCH0.
RX23W Group 36.2.55 36. CAN Module (RSCAN) Transmit/Receive FIFO Access Register 0DL (CFDF20) Address(es): RSCAN0.CFDF20 000A 85ECh b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 CFDB5[7:0] Value after reset: 0 0 0 0 0 b4 b3 b2 b1 b0 0 0 0 CFDB4[7:0] 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 CFDB4[7:0] Transmit/Receive FIFO Buffer Data Byte 4 R/W b15 to b8 CFDB5[7:0] Transmit/Receive FIFO Buffer Data Byte 5 When CFCCH0.
RX23W Group 36.2.57 36. CAN Module (RSCAN) Receive FIFO Message Lost Status Register (RFMSTS) Address(es): RSCAN.RFMSTS 000A 8360h b7 b6 b5 b4 b3 b2 — — — — — — 0 0 0 0 0 0 Value after reset: b1 b0 RF1ML RF0ML T T 0 0 Bit Symbol Bit Name Description R/W b0 RF0MLT Receive FIFO Buffer 0 Message Lost Status Flag 0: No receive FIFO buffer m message is lost (m = 0, 1). 1: A receive FIFO buffer m message is lost.
RX23W Group 36.2.59 36. CAN Module (RSCAN) Receive FIFO Interrupt Status Register (RFISTS) Address(es): RSCAN.RFISTS 000A 8362h b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — RF1IF RF0IF 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W b0 RF0IF Receive FIFO Buffer 0 Interrupt Request Status Flag R b1 RF1IF Receive FIFO Buffer 1 Interrupt Request Status Flag 0: No receive FIFO buffer m interrupt request is present (m = 0, 1).
RX23W Group 36.2.61 36. CAN Module (RSCAN) Transmit Buffer Control Register p (TMCp) (p = 0 to 3) Address(es): RSCAN0.TMC0 000A 8364h, RSCAN0.TMC1 000A 8365h, RSCAN0.TMC2 000A 8366h, RSCAN0.TMC3 000A 8367h b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 Value after reset: b2 b1 b0 TMOM TMTAR TMTR 0 0 0 Bit Symbol Bit Name Description R/W b0 TMTR Transmit Request 0: Transmission is not requested. 1: Transmission is requested.
RX23W Group 36. CAN Module (RSCAN) Modify the TMOM bit when the TMSTSp.TMTRM flag is 0. To set the TMOM bit to 1, also set the TMTR bit together. 36.2.62 Transmit Buffer Status Register p (TMSTSp) (p = 0 to 3) Address(es): RSCAN0.TMSTS0 000A 836Ch, RSCAN0.TMSTS1 000A 836Dh, RSCAN0.TMSTS2 000A 836Eh, RSCAN0.
RX23W Group 36.2.63 36. CAN Module (RSCAN) Transmit Buffer Transmit Request Status Register (TMTRSTS) Address(es): RSCAN0.TMTRSTS 000A 8374h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 — — — — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: b3 b2 b1 b0 TMTRS TMTRS TMTRS TMTRS TS3 TS2 TS1 TS0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 TMTRSTS0 RSCAN0 Transmit Buffer 0 Transmit Request Status Flag 0: No transmit request is present.
RX23W Group 36.2.64 36. CAN Module (RSCAN) Transmit Buffer Transmit Complete Status Register (TMTCSTS) Address(es): RSCAN0.TMTCSTS 000A 8376h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 — — — — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: b3 b2 b1 b0 TMTCS TMTCS TMTCS TMTCS TS3 TS2 TS1 TS0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 TMTCSTS0 RSCAN0 Transmit Buffer 0 Transmit Complete Status Flag 0: Transmission has not been completed.
RX23W Group 36.2.65 36. CAN Module (RSCAN) Transmit Buffer Transmit Abort Status Register (TMTASTS) Address(es): RSCAN0.TMTASTS 000A 8378h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 — — — — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: b3 b2 b1 b0 TMTAS TMTAS TMTAS TMTAS TS3 TS2 TS1 TS0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 TMTASTS0 RSCAN0 Transmit Buffer 0 Transmit Abort Status Flag 0: Transmission is not aborted.
RX23W Group 36.2.66 36. CAN Module (RSCAN) Transmit Buffer Interrupt Enable Register (TMIEC) Address(es): RSCAN0.TMIEC 000A 837Ah b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 — — — — — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 Value after reset: b3 b2 b1 b0 TMIE3 TMIE2 TMIE1 TMIE0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 TMIE0 RSCAN0 Transmit Buffer 0 Interrupt Enable 0: Transmit buffer interrupt is disabled. 1: Transmit buffer interrupt is enabled.
RX23W Group 36.2.68 36. CAN Module (RSCAN) Transmit Buffer Register pAH (TMIDHp) (p = 0 to 3) Address(es): RSCAN0.TMIDH0 000A 8602h, RSCAN0.TMIDH1 000A 8612h, RSCAN0.TMIDH2 000A 8622h, RSCAN0.TMIDH3 000A 8632h b15 b14 b13 b12 b11 b10 b9 b8 b7 TMIDE TMRTR THLEN Value after reset: 0 0 0 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 TMID[28:16] 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b12 to b0 TMID[28:16] Transmit Buffer ID Data H Set standard ID or extended ID.
RX23W Group 36.2.69 36. CAN Module (RSCAN) Transmit Buffer Register pBH (TMPTRp) (p = 0 to 3) Address(es): RSCAN0.TMPTR0 000A 8606h, RSCAN0.TMPTR1 000A 8616h, RSCAN0.TMPTR2 000A 8626h, RSCAN0.
RX23W Group 36.2.70 36. CAN Module (RSCAN) Transmit Buffer Register pCL (TMDF0p) (p = 0 to 3) Address(es): RSCAN0.TMDF00 000A 8608h, RSCAN0.TMDF01 000A 8618h, RSCAN0.TMDF02 000A 8628h, RSCAN0.TMDF03 000A 8638h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 TMDB1[7:0] Value after reset: 0 0 0 0 0 b4 b3 b2 b1 b0 0 0 0 TMDB0[7:0] 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 TMDB0[7:0] Transmit Buffer Data Byte 0 Set transmit buffer data.
RX23W Group 36.2.72 36. CAN Module (RSCAN) Transmit Buffer Register pDL (TMDF2p) (p = 0 to 3) Address(es): RSCAN0.TMDF20 000A 860Ch, RSCAN0.TMDF21 000A 861Ch, RSCAN0.TMDF22 000A 862Ch, RSCAN0.TMDF23 000A 863Ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 TMDB5[7:0] Value after reset: 0 0 0 0 0 b4 b3 b2 b1 b0 0 0 0 TMDB4[7:0] 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 TMDB4[7:0] Transmit Buffer Data Byte 4 Set transmit buffer data.
RX23W Group 36.2.74 36. CAN Module (RSCAN) Transmit History Buffer Control Register (THLCC0) Address(es): RSCAN0.THLCC0 000A 837Ch b15 b14 b13 b12 b11 — — — — — 0 0 0 0 0 Value after reset: b10 b9 b8 THLDT THLIM THLIE E 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — THLE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 THLE Transmit History Buffer Enable 0: Transmit history buffer is not used. 1: Transmit history buffer is used.
RX23W Group 36.2.75 36. CAN Module (RSCAN) Transmit History Buffer Status Register (THLSTS0) Address(es): RSCAN0.THLSTS0 000A 8380h b15 b14 b13 b12 — — — — 0 0 0 0 Value after reset: b11 b10 b9 b8 THLMC[3:0] 0 0 0 0 b7 b6 b5 b4 — — — — 0 0 0 0 b3 b2 b1 b0 THLIF THLEL THLFL THLEM T L P 0 0 0 1 Bit Symbol Bit Name Description R/W b0 THLEMP Transmit History Buffer Empty Status Flag 0: Transmit history buffer contains unread data.
RX23W Group 36.2.76 36. CAN Module (RSCAN) Transmit History Buffer Access Register (THLACC0) Address(es): RSCAN0.THLACC0 000A 8680h b15 b14 b13 b12 b11 b10 b9 b8 TID[7:0] 0 Value after reset: 0 0 0 0 0 0 0 b7 b6 b5 — — — 0 0 0 b4 b3 BN[1:0] 0 0 b2 b1 — 0 b0 BT[1:0] 0 Description 0 Bit Symbol Bit Name R/W b1, b0 BT[1:0] Buffer Type Data b2 — Reserved This bit is read as 0.
RX23W Group 36.2.77 36. CAN Module (RSCAN) Transmit History Buffer Pointer Control Register (THLPCTR0) Address(es): RSCAN0.
RX23W Group 36.2.78 36. CAN Module (RSCAN) Global RAM Window Control Register (GRWCR) Address(es): RSCAN.
RX23W Group 36.2.79 36. CAN Module (RSCAN) Global Test Configuration Register (GTSTCFG) Address(es): RSCAN.GTSTCFG 000A 838Ch b15 b14 b13 b12 b11 — — — — — 0 0 0 0 0 Value after reset: b10 b9 b8 RTMPS[2:0] 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 36.2.81 36. CAN Module (RSCAN) Global Test Protection Unlock Register (GLOCKK) Address(es): RSCAN.GLOCKK 000A 8394h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 LOCK[15:0] Value after reset: 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b15 to b0 LOCK[15:0] Protection Unlock Data Write protection unlock data to use test functions. These bits are read as 0000h. W Modify the GLOCKK register only in global test mode.
RX23W Group 36.3 36. CAN Module (RSCAN) CAN Modes The CAN module has four global modes to control entire CAN module status and four channel modes to control individual channel status. Details of global modes are described in section 36.3.1, Global Modes, and details of channel modes are described in section 36.3.2, Channel Modes. • Global stop mode: Stops clocks of entire module to achieve low power consumption. • Global reset mode: Performs initial settings for entire module.
RX23W Group 36. CAN Module (RSCAN) Table 36.5 shows the global mode transition time. Table 36.
RX23W Group 36.3.2 36. CAN Module (RSCAN) Channel Modes Figure 36.3 shows a channel mode state transition chart. Table 36.6 shows the channel mode transition time.
RX23W Group (1) 36. CAN Module (RSCAN) Channel Stop Mode In channel stop mode, clocks are not supplied to channels and therefore power consumption is reduced. CAN registers can be read, but writing data to them is prohibited. Register values are retained. Each channel enters channel stop mode after the operation of the CAN module is enabled. The channel transitions to channel stop mode when the CTRL.CSLPR bit is set to 1 (channel stop mode) in channel reset mode.
RX23W Group 36. CAN Module (RSCAN) • Bus off: Isolated from CAN communication. When the CTRL.CHMDC[1:0] bits are set to 00b, the channel transitions to channel communication mode. After that, when 11 consecutive recessive bits have been detected, the STSL.COMSTS flag becomes 1 (communication is ready) and transmission and reception are enabled on the CAN network as an active node. At this time, transmission and reception of messages can be started.
RX23W Group Table 36.8 36.
RX23W Group 36.4 36. CAN Module (RSCAN) Reception Function There are two reception types. • Reception by receive buffers: Zero to 16 receive buffers can be shared by all channels. Since messages stored in receive buffers are overwritten at each reception, the latest receive data can always be read.
RX23W Group 36. CAN Module (RSCAN) ID value in received message GAFLIDHj, GAFLIDLj (receive rule entry register jAH/AL) GAFL GAFL IDE RTR GAFLID GAFLMHj, GAFLMLj (receive rule entry register jBH/BL) GAFL GAFL IDEM RTRM Mask bit value 0: Bits are not compared. 1: Bits are compared.
RX23W Group 36.4.2 36. CAN Module (RSCAN) Timestamp The timestamp counter is a 16-bit free-running counter used for recording message receive time. The timestamp counter value is fetched at the start-of-frame (SOF) timing of a message and is then stored in a receive buffer or a FIFO buffer together with the message ID and data. PCLK or the CAN bit time clock is selectable as a timestamp counter clock source from the GCFGL.TSSS bit. The clock obtained by dividing the selected clock source by the GCFGL.
RX23W Group 36.5 36. CAN Module (RSCAN) Transmission Functions There are two types of transmission. • Transmission using transmit buffers: Each channel has 4 buffers. • Transmission using transmit/receive FIFO buffers (transmit mode): Each channel has one FIFO buffer. Up to 16 messages can be contained in a single FIFO buffer. Each FIFO buffer is used with a link to a transmit buffer. Only the message to be transmitted next in a FIFO buffer becomes the target of transmit priority determination.
RX23W Group 36.5.2 36. CAN Module (RSCAN) Transmission Using Transmit Buffers Setting the transmit request bit (TMCp.TMTR bit) in a transmit buffer to 1 (transmission is requested) allows transmission of data frames or remote frames. Transmit result is shown by the corresponding TMSTSp.TMTRF[1:0] flags. When transmit completes successfully, the TMSTSp.
RX23W Group 36. CAN Module (RSCAN) CFCCH0.CFITT[7:0] bits to 00h. Select an interval timer count source by the CFCCH0.CFITR and CFITSS bits. When the CFCCH0.CFITR and CFITSS bits are set to 00b, the clock obtained by frequency-dividing PCLK by the GCFGH.ITRCP[15:0] value is used as a count source. When the CFCCH0.CFITR and CFITSS bits are set to 10b, the clock obtained by frequency-dividing PCLK by the GCFGH.ITRCP[15:0] value × 10 is used as a count source. When the CFCCH0.
RX23W Group 36. CAN Module (RSCAN) Figure 36.9 shows the interval timer timing chart.
RX23W Group 36.5.4 36. CAN Module (RSCAN) Transmit History Function Information of transmitted messages can be stored in the transmit history buffer. Each channel has a single transmit history buffer that can contain 8 sets of transmit history data. A message transmit source buffer type can be selected by the THLCC0.THLDTE bit. Whether to store transmit history data for each message can be set by the CFIDH0.THLEN bit.
RX23W Group 36.6 36. CAN Module (RSCAN) Test Function The test function is classified into communication tests and global tests. Communication tests: Performed for each channel. • Standard test mode • Listen-only mode • Self-test mode 0 (external loopback mode) • Self-test mode 1 (internal loopback mode) Global tests: Performed in entire module • RAM test (read/write test) 36.6.1 Standard Test Mode Standard test mode allows CRC test. 36.6.
RX23W Group 36.6.3 36. CAN Module (RSCAN) Self-Test Mode (Loopback Mode) In self-test mode, transmitted messages are compared with the receive rule of the own channel and the messages are stored in a buffer if they have passed through the filter processing. Messages transmitted from other CAN nodes are compared only with the receive rule for which the GAFLIDHj.GAFLLB bit is set to 0 (when a message transmitted from another CAN node is received).
RX23W Group 36.7 36. CAN Module (RSCAN) Interrupt The CAN module has 5 interrupts that are grouped into global interrupts and channel interrupts.
RX23W Group Table 36.11 36. CAN Module (RSCAN) List of CAN Interrupt Sources Item Interrupt Source Global interrupts Global receive FIFO Corresponding Interrupt Request Flag*1 Corresponding Interrupt Enable Bit *1 Receive FIFO 0 RFSTS0.RFIF RFCC0.RFIE Receive FIFO 1 RFSTS1.RFIF RFCC1.RFIE GERFLL.DEF GCTRL.DEIE Global error Channel interrupts Channel transmit GERFLL.MES GCTRL.MEIE GERFLL.THLES GCTRL.THLEIE Transmit complete TMSTSp.TMTRF[1:0] TMIEC.TMIEp Transmit abort TMSTSp.
RX23W Group 36. CAN Module (RSCAN) CFSTS0.CFRXIF Transmit/receive FIFO receive interrupt CFCCL0.CFRXIE TMIEC.TMIEp Channel transmit interrupt TMSTSp.TMTRF0 TMSTSp.TMTRF1 CTRH.TAIE CFSTS0.CFTXIF CFCCL0.CFTXIE THLSTS0.THLIF THLCC0.THLIE ERFLL.BEF CTRL.BEIE ERFLL.EWF Channel error interrupt CTRL.EWIE ERFLL.EPF CTRL.EPIE ERFLL.BOEF CTRL.BOEIE ERFLL.BORF CTRL.BORIE ERFLL.OVLF CTRL.OLIE ERFLL.BLF CTRL.BLIE ERFLL.ALF CTRL.ALIE Figure 36.14 CAN Channel Interrupt Block Diagram R01UH0823EJ0110 Rev.1.
RX23W Group 36.8 36. CAN Module (RSCAN) RAM Window The CAN area from 000A 83A0h to 000A 8681h consists of two windows. The GRWCR.RPAGE bit is used to switch the allocation of registers. • Registers allocated when the GRWCR.RPAGE bit is set to 0 (window 0 selected) Receive rule entry registers: GAFLIDLj, GAFLIDHj, GAFLMLj, GAFLMHj, GAFLPLj, GAFLPHj RAM test registers: RPGACCr • Registers allocated when the GRWCR.
RX23W Group 36.9 36. CAN Module (RSCAN) Initial Settings The CAN module initializes the CAN RAM after the operation of the CAN module is enabled. The RAM initialization time is 276 cycles of PCLK. The GSTS.GRAMINIT flag becomes 1 (CAN RAM initialization is ongoing) during the RAM initialization and becomes 0 (CAN RAM initialization is finished) when the initialization is completed. Make CAN settings after the GSTS.GRAMINIT flag becomes 0. Figure 36.
RX23W Group 36.9.1 36. CAN Module (RSCAN) Clock Setting Set the CAN clock source (fCAN) as a clock source of the CAN module. Select PCLK or CANMCLK with the GCFGL.DCS bit. 36.9.2 Bit Timing Setting In the CAN protocol, one bit of a communication frame consists of three segments, SS, TSEG1, and TSEG2. Two of the segments, TSEG1 and TSEG2, can be set by the CFGH register for each channel. Sample point timing can be determined by setting two segments.
RX23W Group 36.9.3 36. CAN Module (RSCAN) Communication Speed Setting Set the CAN communication speed for each channel using the fCAN, baud rate prescaler division value (CFGL.BRP[9:0] bits), and Tq count per bit time. Figure 36.18 shows the CAN clock control block diagram, and Table 36.13 shows an example of the communication speed setting.
RX23W Group 36.9.4 36. CAN Module (RSCAN) Receive Rule Setting Receive rules can be set using receive rule-related registers. Up to 16 receive rules can be registered. Figure 36.19 shows the receive rule setting procedure. Start Set the number of receive rules by the GAFLCFG.RNC0[4:0] bits. Switch to window 0 for access to receive rules (Set the GRWCR.RPAGE bit to 0.) Set receive rules by the GAFLIDLj, GAFLIDHj, GAFLMLj, GAFLMHj, GAFLPLj, and GAFLPHj registers.
RX23W Group 36.9.5 36. CAN Module (RSCAN) Buffer Setting Set sizes and interrupt sources of buffers. For transmit/receive FIFO buffers that are set to transmit mode, set transmit buffers to be linked. Figure 36.20 shows the buffer configuration. Figure 36.21 shows the buffer setting procedure.
RX23W Group 36. CAN Module (RSCAN) 36.10 Reception Procedure 36.10.1 Receive Buffer Reading Procedure When the processing to store received messages in a receive buffer starts, the RMND0.RMNSn flag becomes 1 (receive buffer n contains a new message). Messages can be read from the RMIDLn, RMIDHn, RMTSn, RMPTRn, and RMDF0n to RMDF3n registers. If the next message has been received before the current message is read from the receive buffer, the message is overwritten. Figure 36.
RX23W Group 36. CAN Module (RSCAN) ID Control High CRC delimiter EOF ID INT Control EOF INT CAN bus Low SOF ACK Acceptance filter processing SOF Routing and storage processing ACK Acceptance filter processing Routing and storage processing 1 RMNSn flag 0 (1) (2) (3) (4) (5) (6) Cleared by the program RMNSn: Flag in the RMND0 register Figure 36.23 Receive Buffer Reception Timing Chart (1) When the ID field in a message has been received, the acceptance filter processing starts.
RX23W Group 36.10.2 36. CAN Module (RSCAN) FIFO Buffer Reading Procedure When received messages have been stored in one or more receive FIFO buffers or a transmit/receive FIFO buffer that is set to receive mode, the corresponding message count display counter (RFSTSm.RFMC[5:0] flags or CFSTS0.CFMC[5:0] flags) is incremented. At this time, when the RFCCm.RFIE bit (receive FIFO interrupt is enabled) or the CFCCL0.
RX23W Group 36.
RX23W Group 36. CAN Module (RSCAN) CFCCL0.CFDC[2:0] bits are set to 001b or more. The CFSTS0.CFMC[5:0] value is incremented to 01h. When the CFCCL0.CFIM bit is set to 1 (an interrupt occurs each time a message has been received), the CFSTS0.CFRXIF flag becomes 1 (a transmit/receive FIFO receive interrupt request is present). The message is stored in the receive FIFO buffer, if the RFCCm.RFE bit is set to 1 (receive FIFO buffers are used) and RFCCm.RFDC[2:0] bits are set to 001b or more. The RFSTSm.
RX23W Group 36.
RX23W Group 36.
RX23W Group 36. CAN Module (RSCAN) To clear the interrupt request, set the TMSTSa.TMTRF[1:0] flags to 00b (transmission is in progress or no transmit request is present). (5) While another CAN node is transmitting data on the CAN bus (TMSTSa.TMTSTS flag = 0), if the TMCa.TMTAR bit is set to 1 while the corresponding channel is determining transmit priority, the TMCa.TMTR bit cannot be set to 0. (6) After the internal processing time has passed, the transmission is terminated and the TMSTSa.
RX23W Group 36.
RX23W Group 36.
RX23W Group 36.11.3 36. CAN Module (RSCAN) Transmit History Buffer Reading Procedure Transmit history data can be read from the THLACC0 register. The next data can be accessed by writing FFh to the corresponding THLPCTR0 register after reading a set of data. Figure 36.32 shows the transmit history buffer reading procedure. Start Is transmit history buffer empty? (Is the THLSTS0.THLEMP flag 1?) Yes No Read transmit history data form the THLACC0 register. Read data when the GRWCR.RPAGE bit is 1.
RX23W Group 36. CAN Module (RSCAN) 36.12 Test Settings 36.12.1 Self-Test Mode Setting Procedure Self-test mode allows communication test on a channel basis by receiving messages transmitted from the own node. Figure 36.33 shows the self-test mode setting procedure. Start Set the CTRL.CHMDC[1:0] bit to 10b. Is the STSL.CHLTSTS flag 1 (in channel halt mode)? Channel halt mode No Yes Set the CTRH.CTME bit to 1. Set the CTMS[1:0] bits to 10b or 11b. Set the CTRL.CHMDC[1:0] bits to 00b. Are all STSL.
RX23W Group 36.12.2 36. CAN Module (RSCAN) Protection Unlock Procedure Since the global test functions shown in Table 36.14 are protected, write unlock data 1 and unlock data 2 in succession to the GLOCKK.LOCK[15:0] bits, and then set each test function bit to 1. Table 36.14 Protection Unlock Data for Test Functions Test Function Protection Unlock Data 1 Protection Unlock Data 2 Target Bit RAM test 7575h 8A8Ah GTSTCTRL.RTME bit If an incorrect value has been written to the GLOCKK.
RX23W Group 36.12.3 36. CAN Module (RSCAN) RAM Test Setting Procedure RAM tests include CAN RAM read/write test. The read/write test verifies that data written to the RAM is read correctly. Before closing the RAM test, write 0000h to all pages of the CAN RAM. Figure 36.35 shows the RAM test setting procedure. Start Set the GCTRL.GMDC[1:0] bits to 10b. Global test mode Transition to global test mode Is the GSTS.GHLTSTS flag 1 (in global test mode)? No Yes Set the GLOCKK.LOCK[15:0] bits to 7575h.
RX23W Group 36. CAN Module (RSCAN) 36.13 Notes on the CAN Module • When changing a global mode, check the GSTS.GSLPSTS, GHLTSTS, and GRSTSTS flags for transitions. When changing a channel mode, check the STSL.CSLPSTS, CHLTSTS, and CRSTSTS flags for transitions. • The acceptance filter processing checks receive rules sequentially in ascending order from the minimum rule number.
RX23W Group 37. 37. Serial Sound Interface (SSI) Serial Sound Interface (SSI) This MCU integrates one channel of the serial sound interface (SSI) compliant with the I2S bus specification. The SSI supports I2S data format and MSB-first and left-justified/right-justified formats, so it can be used to send or receive audio data with various devices. 37.1 Overview Table 37.
RX23W Group 37. Serial Sound Interface (SSI) Figure 37.1 shows a block diagram of SSI (SSI0).
RX23W Group 37.2 37. Serial Sound Interface (SSI) Register Descriptions 37.2.1 Control Register (SSICR) Address(es): SSI0.
RX23W Group 37. Serial Sound Interface (SSI) Bit Symbol Bit Name Description R/W b12 SWSP Word Select Polarity 0: SSIWS0 is low for the 1st system word, high for the 2nd system word. 1: SSIWS0 is high for the 1st system word, low for the 2nd system word. R/W b13 SCKP Serial Bit Clock Polarity*3 0: SSIWS0 and SSITXD0 change at the SSISCK0 falling edge (SSIWS0 and SSIRXD0 are sampled at the SSISCK0 rising edge).
RX23W Group 37. Serial Sound Interface (SSI) REN Bit (Receive Enable) This bit enables or disables receive operation. Setting this bit to 1 starts receive operation. TEN Bit (Transmit Enable) This bit enables or disables transmit operation. Setting this bit to 1 starts transmit operation. SSITXD0 pin of SSI0 is set as output while SSITXD0 is selected by the multi-function pin controller (MPC), regardless of the TEN bit setting. Table 37.
RX23W Group 37.
RX23W Group 37.2.2 37. Serial Sound Interface (SSI) Status Register (SSISR) Address(es): SSI0.
RX23W Group 37. Serial Sound Interface (SSI) TSWNO Flag (Transmit System Word Number Flag) This status flag indicates the current word number. The initial value of this is 1, and its value is inverted when the data is transferred from the SSIFTDR register to the transmit shift register. This flag is initialized to 1 when the SSICR.TEN bit value is changed from 0 to 1. When the data word length specified by the SSICR.
RX23W Group 37. Serial Sound Interface (SSI) confirming it to be 1. If TUIRQ flag = 1 and SSICR.TUIEN bit = 1, an interrupt occurs. If TUIRQ flag = 1, the SSIFTDR register did not have data written to it before it was required for transmission. This may lead to the same data being transmitted once more. Note: When a transmit underflow occurs, the last data input to the SSIFTDR register is transmitted until this module is in the idle state after transmission is stopped. 37.2.
RX23W Group 37. Serial Sound Interface (SSI) RFRST Bit (Receive FIFO Data Register Reset) This bit invalidates the data in the SSIFRDR register to reset the FIFO to an empty state. TFRST Bit (Transmit FIFO Data Register Reset) This bit invalidates the data in the SSIFTDR register to reset the FIFO to an empty state. RIE Bit (Receive Data Full Interrupt Enable) This bit enables or disables generation of receive data full interrupt (RXI) requests when the SSIFSR.RDF flag is set to 1 during reception.
RX23W Group 37.2.4 37. Serial Sound Interface (SSI) FIFO Status Register (SSIFSR) Address(es): SSI0.
RX23W Group Note: 37. Serial Sound Interface (SSI) Since the SSIFRDR register is a 32-byte FIFO register, the maximum number of data bytes that can be read from it while the RDF flag is 1 is indicated in the RDC[3:0] flags. If reading data from the SSIFRDR register is continued after all the data is read, undefined values will be read. RDC[3:0] Flags (Receive Data Indicate Flag) These flags indicate the number of data bytes stored in the SSIFRDR register. RDC[3:0] flags = 0h indicates no received data.
RX23W Group 37.2.5 37. Serial Sound Interface (SSI) Transmit FIFO Data Register (SSIFTDR) Address(es): SSI0.
RX23W Group 37.2.7 37. Serial Sound Interface (SSI) TDM Mode Register (SSITDMR) Address(es): SSI0.
RX23W Group 37.3 37. Serial Sound Interface (SSI) Operation 37.3.1 Bus Format This module can operate as a transmitter or a receiver and can be configured into many serial bus formats in either mode. The bus format can be selected from one of the six modes shown in Table 37.5. 1 Non-compression master transmitter 1 0 1 1 Non-compression master transceiver 1 1 1 1 37.3.
RX23W Group (6) 37. Serial Sound Interface (SSI) Master Transceiver This mode allows serial data transmission and reception between this module and another device. The clock and word select signals are internally derived from the master clock. The format of these signals is defined in the configuration fields of this module. (7) Operating Settings Related to Word Length All bits related to the SSICR register's word length are valid in non-compressed modes.
RX23W Group 37. Serial Sound Interface (SSI) • MSB-First and Left-Justified Format Figure 37.4 shows the MSB-first and left-justified format with padding. SSICR.SCKP bit = 0, SSICR.SWSP bit = 1, SSICR.DEL bit = 1, SSICR.CHNL[1:0] bits = 00b, SSICR.SPDP bit = 0, SSICR.SDTA bit = 0 System word length > data word length SSISCK SSIWS SSIDATA LSB MSB MSB Data word 1 Padding Data word 2 System word 1 Figure 37.
RX23W Group (8) 37. Serial Sound Interface (SSI) Operating Settings Other than Word Length Related Settings Several more configuration bits in non-compressed mode are shown below. These bits are not mutually exclusive, but some combinations may not be useful. These configuration bits are described below with reference to the basic format sample in Figure 37.6. In Figure 37.6 to Figure 37.14, a system word length of 6 bits and a data word length of 4 bits are used for simplification of these figures.
RX23W Group 37. Serial Sound Interface (SSI) • Inverted Word Select Same as basic format sample configuration except SSICR.SWSP bit = 1 SSISCK System word 1 SSIWS SSIDATA Figure 37.8 TD28 0 0 TD31 TD30 TD29 TD28 System word 2 0 0 TD31 TD30 TD29 TD28 0 0 TD31 1 1 TD31 Inverted Word Select • Inverted Padding Polarity Same as basic format sample configuration except SSICR.SPDP bit = 1 SSISCK System word 1 SSIWS SSIDATA Figure 37.
RX23W Group 37. Serial Sound Interface (SSI) • Transmitting and Receiving in the Order of Serial Data and Padding Bits; without Delay Same as basic format sample configuration except SSICR.DEL bit = 1 SSISCK System word 1 SSIWS SSIDATA Figure 37.
RX23W Group 37.3.3 37. Serial Sound Interface (SSI) WS Continue Mode In WS continue mode, the SSIWS0 signal continues to be toggled irrespective whether data transmission is enabled or disabled. This mode can be set using the SSITDMR.CONT bit. With this mode enabled, the SSIWS0 signal does not stop but continues toggling even if the SSICR.TEN and REN bits are both set to 0 (transmission disabled). With this mode disabled, the SSIWS0 signal stops if the SSICR.TEN and REN bits are both set to 0.
RX23W Group 37.3.4 37. Serial Sound Interface (SSI) Operating States There are three states of operation: idle, communication, and waiting for idle. Figure 37.17 shows the operating state transitions. Reset Idle (after reset) SSICR.TEN bit = 0 and SSICR.REN bit = 0 (SSISR.IDST flag = 1) SSICR.TEN bit = 1 or SSICR.REN bit = 1 (SSISR.IDST flag = 0) Waiting for idle Communication SSICR.TEN bit = 0 and SSICR.REN bit = 0 (SSISR.IDST flag = 0) Figure 37.
RX23W Group 37.3.5 37. Serial Sound Interface (SSI) Transmit Operation Transmission can be controlled either by DMA/DTC transfer or interrupt. DMAC/DTC control is preferred to reduce the processor load. In transmission using the DMAC/DTC, the processor will only receive interrupts if there is an underflow or overflow of data or if DMA/DTC transfer has been completed.
RX23W Group (1) 37. Serial Sound Interface (SSI) Transmission Using the DMAC/DTC Start Set the SSIFCR.AUCKE bit to 1 in master mode. Set the SSICR register configuration bits. Enable an error interrupt, setup and enable the DMAC/DTC, enable transmit operation. Enable a transmit interrupt, enable the DMAC/DTC. Wait for an interrupt.
RX23W Group (2) 37. Serial Sound Interface (SSI) Transmission Using Interrupts Start Set the SSIFCR.AUCKE bit to 1 in master mode. Set the SSICR register configuration bits. Setup the interrupt controller. Enable an error interrupt, enable a transmit interrupt, enable transmit operation. Wait for an interrupt. Error interrupt? Yes No Write transmit data*2, clear the SSIFSR.
RX23W Group 37.3.6 37. Serial Sound Interface (SSI) Receive Operation Like transmission, reception can be controlled either by DMA/DTC transfer or interrupt. Figure 37.20 and Figure 37.21 show the flow of operation. When stopping reception, set the SSICR.REN bit to 0 and continue to supply the clock*1 until the SSISR.IIRQ flag becomes 1 (in idle state). Note 1. Input clock from the SSISCK0 pin when SSICR.SCKD bit = 0. Master clock when SSICR.SCKD bit = 1.
RX23W Group (2) 37. Serial Sound Interface (SSI) Reception Using Interrupts Start Set the SSIFCR.AUCKE bit to 1 in master mode. Set the SSICR register configuration bits. Setup the interrupt controller. Enable an error interrupt, enable a receive interrupt, enable receive operation. Wait for an interrupt. Error interrupt? Yes No Read receive data, clear the SSIFSR.RDF flag Yes Receive more data? No Disable receive operation, disable an error interrupt, enable an idle interrupt.
RX23W Group 37.3.7 37. Serial Sound Interface (SSI) Serial Bit Clock Control The SSI controls and selects the serial bit clock, according to the SSICR.SCKD and CKDV[3:0] bits setting. If the serial bit clock direction is set to input (SCKD bit = 0), this module is in slave mode and the shift register uses the clock that was input to the SSISCK0 pin as the bit clock.
RX23W Group 37.5 37.5.1 37. Serial Sound Interface (SSI) Usage Notes Setting the Module Stop Function Module stop state can be entered or released using the MSTPCRD register. The initial setting of the SSI is in the module stop state. SSI register access is enabled by releasing the module stop state. For details on the MSTPCRD register, refer to section 11, Low Power Consumption. 37.5.
RX23W Group 38. 38. Serial Peripheral Interface (RSPIa) Serial Peripheral Interface (RSPIa) In this section, “PCLK” is used to refer to PCLKB. 38.1 Overview This MCU includes one channel of Serial Peripheral Interface (RSPI). The RSPI channels are capable of high-speed, full-duplex synchronous serial communications with multiple processors and peripheral devices. Table 38.1 lists the specifications of the RSPI, and Figure 38.1 shows a block diagram of the RSPI.
RX23W Group Table 38.1 38. Serial Peripheral Interface (RSPIa) RSPI Specifications (2/2) Item Description Interrupt sources • Interrupt sources Receive buffer full interrupt Transmit buffer empty interrupt RSPI error interrupt (mode fault, overrun, or parity error) RSPI idle interrupt (RSPI idle) Event link function (output) • The following events can be output to the event link controller.
38.
RX23W Group 38. Serial Peripheral Interface (RSPIa) Table 38.2 lists the I/O pins used in the RSPI. The RSPI automatically switches the I/O direction of the SSLA0 pin. SSLA0 is set as an output when the RSPI is a single master and as an input when the RSPI is a multi-master or a slave. Pins RSPCKA, MOSIA, and MISOA are automatically set as inputs or outputs according to the setting of master or slave and the level input on the SSLA0 pin. Refer to section 38.3.2, Controlling RSPI Pins for details.
RX23W Group 38.2 38. Serial Peripheral Interface (RSPIa) Register Descriptions 38.2.1 RSPI Control Register (SPCR) Address(es): RSPI0.
RX23W Group 38. Serial Peripheral Interface (RSPIa) MODFEN Bit (Mode Fault Error Detection Enable) The MODFEN bit enables or disables the detection of mode fault error (refer to section 38.3.8, Error Detection). In addition, the RSPI determines the I/O direction of the SSLA0, SSLA1, and SSLA3 pins based on combinations of the MODFEN and MSTR bits (refer to section 38.3.2, Controlling RSPI Pins). MSTR Bit (RSPI Master/Slave Mode Select) The MSTR bit selects master/slave mode of the RSPI.
RX23W Group 38.2.2 38. Serial Peripheral Interface (RSPIa) RSPI Slave Select Polarity Register (SSLP) Address(es): RSPI0.
RX23W Group 38.2.3 38. Serial Peripheral Interface (RSPIa) RSPI Pin Control Register (SPPCR) Address(es): RSPI0.
RX23W Group 38.2.4 38. Serial Peripheral Interface (RSPIa) RSPI Status Register (SPSR) Address(es): RSPI0.
RX23W Group 38. Serial Peripheral Interface (RSPIa) 4. The RSPI internal sequencer has entered the idle state (status in which operations up to the next-access delay have finished) Slave mode • The SPCR.SPE bit is 0 (disables the RSPI function) MODF Flag (Mode Fault Error Flag) Indicates the occurrence of a mode fault error. [Setting condition] Multi-master mode • When the input level of the SSLAi pin changes to the active level while the SPCR.MSTR bit is 1 (master mode) and the SPCR.
RX23W Group 38. Serial Peripheral Interface (RSPIa) [Clearing condition] • When all of the received data are read from the SPDR register R01UH0823EJ0110 Rev.1.
RX23W Group 38.2.5 38. Serial Peripheral Interface (RSPIa) RSPI Data Register (SPDR) • When accessing in longword size Address(es): RSPI0.
RX23W Group 38. Serial Peripheral Interface (RSPIa) mapped to the single address of SPDR. Data written to SPDR are written to a transmit-buffer stage (SPTXn) (n = 0 to 3) and then transmitted from the buffer. The receive buffer holds received data on completion of reception. The receive buffer is not updated if an overrun is generated. Furthermore, if the data length is other than 32 bits, bits not referred to in SPTXn (n = 0 to 3) are stored in the corresponding bits in SPRXn.
RX23W Group 38. Serial Peripheral Interface (RSPIa) the RSPI data control register (SPDCR). Even if the number of frames is written to the transmit buffer (SPTXn), the value of the buffer is not updated after completion of the writing and before generation of the next transmit buffer empty interrupt (while the SPSR.SPTEF flag is 0). (b) Reading SPDR can be read to read the value of a receive buffer (SPRXn) or a transmit buffer (SPTXn).
RX23W Group 38.2.6 38. Serial Peripheral Interface (RSPIa) RSPI Sequence Control Register (SPSCR) Address(es): RSPI0.SPSCR 0008 8388h Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 SPSLN[2:0] 0 0 Bit Symbol Bit Name Description b2 to b0 SPSLN[2:0] RSPI Sequence Length Specification b2 b7 to b3 — Reserved 0 b0 Sequence Length R/W Referenced SPCMD0 to SPCMD7 (No.
RX23W Group 38.2.7 38. Serial Peripheral Interface (RSPIa) RSPI Sequence Status Register (SPSSR) Address(es): RSPI0.SPSSR 0008 8389h b7 b6 — Value after reset: 0 b5 b4 SPECM[2:0] 0 0 b3 b2 — 0 0 b1 b0 SPCP[2:0] 0 0 0 Bit Symbol Bit Name Description b2 to b0 SPCP[2:0] RSPI Command Pointer b3 — Reserved This bit is read as 0. R b6 to b4 SPECM[2:0] RSPI Error Command b6 R b7 — Reserved This bit is read as 0.
RX23W Group 38.2.8 38. Serial Peripheral Interface (RSPIa) RSPI Bit Rate Register (SPBR) Address(es): RSPI0.SPBR 0008 838Ah Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 1 1 1 1 1 SPBR sets the bit rate in master mode. Do not change the SPBR register while both the SPCR.MSTR and SPCR.SPE bits are 1.
RX23W Group 38.2.9 38. Serial Peripheral Interface (RSPIa) RSPI Data Control Register (SPDCR) Address(es): RSPI0.SPDCR 0008 838Bh Value after reset: b7 b6 — — 0 0 b5 b4 SPLW SPRDT D 0 0 b3 b2 b1 b0 — — SPFC[1:0] 0 0 0 0 Bit Symbol Bit Name Description R/W b1, b0 SPFC[1:0] Number of Frames Specification b1 b0 R/W b3, b2 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group Table 38.4 38.
RX23W Group 38.2.10 38. Serial Peripheral Interface (RSPIa) RSPI Clock Delay Register (SPCKD) Address(es): RSPI0.SPCKD 0008 838Ch Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 SCKDL[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 SCKDL[2:0] RSPCK Delay Setting b2 R/W b7 to b3 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 38.2.11 38. Serial Peripheral Interface (RSPIa) RSPI Slave Select Negation Delay Register (SSLND) Address(es): RSPI0.SSLND 0008 838Dh Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 SLNDL[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 SLNDL[2:0] SSL Negation Delay Setting b2 R/W b7 to b3 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 38.2.12 38. Serial Peripheral Interface (RSPIa) RSPI Next-Access Delay Register (SPND) Address(es): RSPI0.SPND 0008 838Eh Value after reset: b7 b6 b5 b4 b3 — — — — — 0 0 0 0 0 b2 b1 b0 SPNDL[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 SPNDL[2:0] RSPI Next-Access Delay Setting b2 R/W b7 to b3 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 38.2.13 38. Serial Peripheral Interface (RSPIa) RSPI Control Register 2 (SPCR2) Address(es): RSPI0.SPCR2 0008 838Fh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — SCKAS E PTE SPIIE SPOE SPPE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 SPPE Parity Enable 0: Does not add the parity bit to transmit data and does not check the parity bit of receive data 1: Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.
RX23W Group 38. Serial Peripheral Interface (RSPIa) SCKASE Bit (RSPCK Auto-Stop Function Enable) The SCKASE bit enables or disables the RSPCK auto-stop function. When this function is enabled, the RSPCK clock is stopped before an overrun error occurs when data is received in master mode. For details, refer to section 38.3.8.1, Overrun Error. R01UH0823EJ0110 Rev.1.
RX23W Group 38.2.14 38. Serial Peripheral Interface (RSPIa) RSPI Command Register m (SPCMDm) (m = 0 to 7) Address(es): RSPI0.SPCMD0 0008 8390h, RSPI0.SPCMD1 0008 8392h, RSPI0.SPCMD2 0008 8394h, RSPI0.SPCMD3 0008 8396h, RSPI0.SPCMD4 0008 8398h, RSPI0.SPCMD5 0008 839Ah, RSPI0.SPCMD6 0008 839Ch, RSPI0.
RX23W Group 38. Serial Peripheral Interface (RSPIa) SPCMDm register is used to set a transfer format for the RSPI in master mode. Each channel has eight RSPI command registers (SPCMD0 to SPCMD7). Some of the bits in SPCMD0 register is used to set a transfer mode for the RSPI in slave mode. The RSPI in master mode sequentially references SPCMDm register according to the settings in the SPSCR.SPSLN[2:0] bits, and executes the serial transfer that is set in the referenced SPCMDm register.
RX23W Group 38. Serial Peripheral Interface (RSPIa) SPNDEN Bit (RSPI Next-Access Delay Enable) The SPNDEN bit sets the period from the time the RSPI in master mode terminates a serial transfer and sets the SSLAi signal inactive until the RSPI enables the SSLAi signal assertion for the next access (next-access delay). If the SPNDEN bit is 0, the RSPI sets the next-access delay to 1 RSPCK + 2 PCLK. If the SPNDEN bit is 1, the RSPI inserts a nextaccess delay in compliance with the SPND setting.
RX23W Group 38.3 38. Serial Peripheral Interface (RSPIa) Operation In this section, the serial transfer period means a period from the beginning of driving valid data to the fetching of the final valid data. 38.3.1 Overview of RSPI Operations The RSPI is capable of synchronous serial transfers in slave mode (SPI operation), single-master mode (SPI operation), multi-master mode (SPI operation), slave mode (clock synchronous operation), and master mode (clock synchronous operation).
RX23W Group 38.3.2 38. Serial Peripheral Interface (RSPIa) Controlling RSPI Pins According to the MSTR, MODFEN, and SPMS bits in SPCR and the ODRn.Bi bit for I/O ports, the RSPI can switch pin states. Table 38.6 lists the relationship between pin states and bit settings. Setting the ODRn.Bi bit for an I/O port to 0 selects CMOS output; setting it to 1 selects open-drain output. The I/O port settings should follow this relationship. Table 38.
RX23W Group 38.3.3 38.3.3.1 38. Serial Peripheral Interface (RSPIa) RSPI System Configuration Examples Single Master/Single Slave (with This MCU Acting as Master) Figure 38.5 shows a single-master/single-slave RSPI system configuration example when this MCU is used as a master. In the single-master/single-slave configuration, the SSLA0, SSLA1, and SSLA3 output of this MCU (master) are not used. The SSL input of the SPI slave is fixed to the low level, and the SPI slave is maintained in a select state.
RX23W Group 38.3.3.2 38. Serial Peripheral Interface (RSPIa) Single Master/Single Slave (with This MCU Acting as Slave) Figure 38.6 shows a single-master/single-slave RSPI system configuration example when this MCU is used as a slave. When this MCU is to operate as a slave, the SSLA0 pin is used as SSL input. The SPI master drives the RSPCK and MOSI. This MCU (slave) drives the MISOA.*1 In the single-slave configuration in which the SPCMDm.
RX23W Group 38.3.3.3 38. Serial Peripheral Interface (RSPIa) Single Master/Multi-Slave (with This MCU Acting as Master) Figure 38.8 shows a single-master/multi-slave RSPI system configuration example when this MCU is used as a master. In the example of Figure 38.8, the RSPI system is comprised of this MCU (master) and three slaves (SPI slave 0 to SPI slave 2). The RSPCKA and MOSIA outputs of this MCU (master) are connected to the RSPCK and MOSI inputs of SPI slave 0 to SPI slave 2.
RX23W Group 38.3.3.4 38. Serial Peripheral Interface (RSPIa) Single Master/Multi-Slave (with This MCU Acting as Slave) Figure 38.9 shows a single-master/multi-slave RSPI system configuration example when this MCU is used as a slave. In the example of Figure 38.9, the RSPI system is comprised of an SPI master and two MCUs (slave X and slave Y). The SPCK and MOSI outputs of the SPI master are connected to the RSPCKA and MOSIA inputs of the MCUs (slave X and slave Y).
RX23W Group 38.3.3.5 38. Serial Peripheral Interface (RSPIa) Multi-Master/Multi-Slave (with This MCU Acting as Master) Figure 38.10 shows a multi-master/multi-slave RSPI system configuration example when this MCU is used as a master. In the example of Figure 38.10, the RSPI system is comprised of two MCUs (master X and master Y) and two SPI slaves (SPI slave 1 and SPI slave 2).
RX23W Group 38.3.3.6 38. Serial Peripheral Interface (RSPIa) Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with This MCU Acting as Master) Figure 38.11 shows a master (clock synchronous operation)/slave (clock synchronous operation) RSPI system configuration example when this MCU is used as a master. In the master (clock synchronous operation)/slave (clock synchronous operation) configuration, SSLA0, SSLA1, and SSLA3 of this MCU (master) are not used.
RX23W Group 38.3.4 38. Serial Peripheral Interface (RSPIa) Data Format The RSPI’s data format depends on the settings in RSPI command register m (SPCMDm) (m = 0 to 7) and the parity enable bit in RSPI control register 2 (SPCR2.SPPE). Regardless of whether the MSB or LSB is first, the RSPI treats the range from the LSB bit in the RSPI data register (SPDR) to the selected data length as transfer data. The format of one frame of data before or after transfer is shown below.
RX23W Group 38.3.4.1 38. Serial Peripheral Interface (RSPIa) When Parity is Disabled (SPCR2.SPPE = 0) When parity is disabled, data for transmission are copied to the shift register with no prior processing. A description of the connection between the RSPI data register (SPDR) and the shift register in terms of the combination of MSB or LSB first and data length is given below. (1) MSB First Transfer (32-Bit Data) Figure 38.
RX23W Group (2) 38. Serial Peripheral Interface (RSPIa) MSB First Transfer (24-Bit Data) Figure 38.15 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, 24 bits as the RSPI data length for an example that is not 32 bits, and MSB first selected. In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are copied to the shift register.
RX23W Group (3) 38. Serial Peripheral Interface (RSPIa) LSB First Transfer (32-Bit Data) Figure 38.16 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, an RSPI data length of 32 bits, and LSB first selected. In transmission, bits T31 to T00 from the current stage of the transmit buffer are reordered bit by bit to obtain the order T00 to T31 for copying to the shift register.
RX23W Group (4) 38. Serial Peripheral Interface (RSPIa) LSB First Transfer (24-Bit Data) Figure 38.17 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity disabled, 24 bits as the RSPI data length for an example that is not 32 bits, and LSB first selected. In transmission, the lower-order 24 bits (T23 to T00) from the current stage of the transmit buffer are reordered bit by bit to obtain the order T00 to T23 for copying to the shift register.
RX23W Group 38.3.4.2 38. Serial Peripheral Interface (RSPIa) When Parity is Enabled (SPCR2.SPPE = 1) When parity is enabled, the lowest-order bit of the data for transmission becomes a parity bit. Hardware calculates the value of the parity bit. (1) MSB First Transfer (32-Bit Data) Figure 38.18 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, an RSPI data length of 32 bits, and MSB first selected.
RX23W Group (2) 38. Serial Peripheral Interface (RSPIa) MSB First Transfer (24-Bit Data) Figure 38.19 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, 24 bits as the RSPI data length for an example that is not 32 bits, and MSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T23 to T01. This replaces the final bit, T00, and the whole is copied to the shift register.
RX23W Group (3) 38. Serial Peripheral Interface (RSPIa) LSB First Transfer (32-Bit Data) Figure 38.20 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, an RSPI data length of 32 bits, and LSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T30 to T00. This replaces the final bit, T31, and the whole is copied to the shift register. Data are transmitted in the order T00, T01, …, T30, and P.
RX23W Group (4) 38. Serial Peripheral Interface (RSPIa) LSB First Transfer (24-Bit Data) Figure 38.21 shows details of operations by the RSPI data register (SPDR) and the shift register in transfer with parity enabled, 24 bits as the RSPI data length for an example that is not 32 bits, and LSB first selected. In transmission, the value of the parity bit (P) is calculated from bits T22 to T00. This replaces the final bit, T23, and the whole is copied to the shift register.
RX23W Group 38.3.5 38. Serial Peripheral Interface (RSPIa) Transfer Format 38.3.5.1 CPHA = 0 Figure 38.22 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 0. Note that clock synchronous operation (the SPCR.SPMS bit is 1) should not performed when the RSPI operates in slave mode (SPCR.MSTR = 0) and the CPHA bit is 0. In Figure 38.22, RSPCKA (CPOL = 0) indicates the RSPCKA signal waveform when the SPCMDm.
RX23W Group 38.3.5.2 38. Serial Peripheral Interface (RSPIa) CPHA = 1 Figure 38.23 shows a sample transfer format for the serial transfer of 8-bit data when the SPCMDm.CPHA bit is 1. However, when the SPCR.SPMS bit is 1, the SSLAi signals are not used, and only the three signals RSPCKA, MOSIA, and MISOA handle communications. In Figure 38.23, RSPCK (CPOL = 0) indicates the RSPCKA signal waveform when the SPCMDm.CPOL bit is 0; RSPCKA (CPOL = 1) indicates the RSPCKA signal waveform when the CPOL bit is 1.
RX23W Group 38.3.6 38. Serial Peripheral Interface (RSPIa) Communications Operating Mode Full-duplex synchronous serial communications or transmit operations only can be selected by the communications operating mode select bit (SPCR.TXMD). The SPDR access shown in Figure 38.24 and Figure 38.25 indicate the condition of access to the SPDR register, where W denotes a write cycle. 38.3.6.1 Full-Duplex Synchronous Serial Communications (SPCR.TXMD = 0) Figure 38.
RX23W Group 38.3.6.2 38. Serial Peripheral Interface (RSPIa) Transmit Operations Only (SPCR.TXMD = 1) Figure 38.25 shows an example of operation when the communications operating mode select bit (SPCR.TXMD) is set to 1. In the example in Figure 38.25, the RSPI performs an 8-bit serial transfer in which the SPDCR.SPFC[1:0] bits are 00b, the SPCMDm.CPHA bit is 1, and the SPCMDm.CPOL bit is 0. The numbers given under the RSPCKA waveform represent the number of RSPCK cycles (i.e.
RX23W Group 38.3.7 38. Serial Peripheral Interface (RSPIa) Transmit Buffer Empty/Receive Buffer Full Interrupts Figure 38.26 shows an example of operation of the transmit buffer empty interrupt (SPTI) and the receive buffer full interrupt (SPRI). The SPDR register access shown in Figure 38.26 indicates the condition of access to the SPDR register, where W denotes a write cycle, and R a read cycle. In the example in Figure 38.26, the RSPI performs an 8-bit serial transfer in which the SPCR.
RX23W Group 38. Serial Peripheral Interface (RSPIa) (5) When SPDR is read in the receive buffer full interrupt routine or in the receive buffer full detecting process by polling the SPRF flag, the receive data can be read. When the receive data is read, the SPRF flag becomes 0. If transmit data is written to SPDR while the transmit buffer holds data that has not yet been transmitted (the SPTEF flag is 0), the RSPI does not update the data in the transmit buffer.
RX23W Group 38.3.8 38. Serial Peripheral Interface (RSPIa) Error Detection In the normal RSPI serial transfer, the data written to the transmit buffer of SPDR is transmitted, and the received data can be read from the receive buffer of SPDR. If access is made to SPDR, depending on the status of the transmit/receive buffer or the status of the RSPI at the beginning or end of serial transfer, in some cases non-normal transfers can be executed.
RX23W Group 38.3.8.1 38. Serial Peripheral Interface (RSPIa) Overrun Error If a serial transfer ends when the receive buffer of SPDR is full, the RSPI detects an overrun error, and sets the SPSR.OVRF flag to 1. When the OVRF flag is 1, the RSPI does not copy data from the shift register to the receive buffer so that the data prior to the occurrence of the error is retained in the receive buffer. To set the OVRF flag to 0, write 0 to the OVRF flag after the CPU has read SPSR with the OVRF flag set to 1.
RX23W Group 38. Serial Peripheral Interface (RSPIa) When the RSPCK auto-stop function is enabled in master mode, an overrun error does not occur. Figure 38.28 and Figure 38.29 show the clock stop waveform when a serial transfer continues while the receive buffer is full in master mode.
RX23W Group 38.3.8.2 38. Serial Peripheral Interface (RSPIa) Parity Error If full-duplex synchronous serial communications is performed with the SPCR.TXMD bit set to 0 and the SPCR2.SPPE bit set to 1, when serial transfer ends, the RSPI checks whether there are parity errors. Upon detecting a parity error in the received data, the RSPI sets the SPSR.PERF flag to 1. Since the RSPI does not copy the data in the shift register to the receive buffer when the SPSR.
RX23W Group 38.3.8.3 38. Serial Peripheral Interface (RSPIa) Mode Fault Error The RSPI operates in multi-master mode when the SPCR.MSTR bit is 1, the SPCR.SPMS bit is 0, and the SPCR.MODFEN bit is 1. If the active level is input with respect to the SSLA0 input signal of the RSPI in multi-master mode, the RSPI detects a mode fault error irrespective of the status of the serial transfer, and sets the SPSR.MODF flag to 1.
RX23W Group 38.3.9 38. Serial Peripheral Interface (RSPIa) Initializing RSPI If 0 is written to the SPCR.SPE bit or the RSPI sets the SPE bit to 0 because of the detection of a mode fault error, the RSPI disables the RSPI function, and initializes some of the module functions. When a system reset is generated, the RSPI initializes all of the module functions. The following describes initialization by the clearing of the SPCR.SPE bit and initialization by a system reset. 38.3.9.
RX23W Group 38.3.10 38.3.10.1 38. Serial Peripheral Interface (RSPIa) SPI Operation Master Mode Operation The only difference between single-master mode operation and multi-master mode operation lies in mode fault error detection (refer to section 38.3.8, Error Detection). When operating in single-master mode, the RSPI does not detect mode fault errors whereas the RSPI running in multi-master mode does detect mode fault errors.
RX23W Group (3) 38. Serial Peripheral Interface (RSPIa) Sequence Control The transfer format that is employed in master mode is determined by SPSCR, SPCMDm, SPBR, SPCKD, SSLND, and SPND registers. SPSCR is a register used to determine the sequence configuration for serial transfers that are executed by the RSPI in master mode.
RX23W Group 38. Serial Peripheral Interface (RSPIa) Figure 38.33 shows the relationship between the command and the transmit and receive buffers in the sequence of operations specified by the settings in Table 38.4.
RX23W Group (4) 38. Serial Peripheral Interface (RSPIa) Burst Transfer If the SPCMDm.SSLKP bit that the RSPI references during the current serial transfer is 1, the RSPI keeps the SSLAi signal level during the serial transfer until the beginning of the SSLAi signal assertion for the next serial transfer.
RX23W Group (5) 38. Serial Peripheral Interface (RSPIa) RSPCK Delay (t1) The RSPCK delay value of the RSPI in master mode depends on the SPCMDm.SCKDEN bit setting and the SPCKD register setting. The RSPI determines the SPCMDm register to be referenced during serial transfer by pointer control, and determines an RSPCK delay value during serial transfer by using the SPCMDm.SCKDEN bit and SPCKD, as listed in Table 38.9. For a definition of RSPCK delay, refer to section 38.3.5, Transfer Format. Table 38.
RX23W Group (7) 38. Serial Peripheral Interface (RSPIa) Next-Access Delay (t3) The next-access delay value of the RSPI in master mode depends on the SPCMDm.SPNDEN bit setting and the SPND setting. The RSPI determines the SPCMDm register to be referenced during serial transfer by pointer control, and determines a next-access delay value during serial transfer by using the SPCMDm.SPNDEN bit and SPND, as listed in Table 38.11. For a definition of next-access delay, refer to section 38.3.5, Transfer Format.
RX23W Group (8) 38. Serial Peripheral Interface (RSPIa) Initialization Flowchart Figure 38.35 is a flowchart illustrating an example of initialization in SPI operation when the RSPI is used in master mode. For a description of how to set up the interrupt controller, DMAC, and I/O ports, refer to the descriptions given in the individual blocks. Start of initialization in master mode Set RSPI slave select polarity register (SSLP) • Sets polarity of SSL signal.
RX23W Group (9) 38. Serial Peripheral Interface (RSPIa) Software Processing Flow Figure 38.36 to Figure 38.38 show examples of the flow of software processing. (a) Transmit Processing Flow When transmitting data, the CPU will be notified of the completion of data transmission by enabling the SPI interrupt after the last writing of data for transmission. The completion of data transmission can also be checked by polling to see if the SPSR.IDLNF flag has become 0, instead of using the SPII interrupt.
RX23W Group (b) 38. Serial Peripheral Interface (RSPIa) Receive Processing Flow The RSPI does not handle receive-only operation, so processing for transmission is required. Pre-transfer processing Processing for reception Start processing for reception End of initial settings Clear the SPSR.MODF, OVRF, and PERF flags [1] Clear error sources. No SPRI interrupt generated or SPSR.SPRF = 1? Yes Set SPCR2.SPIIE = 0 Set SPCR.SPE = 1 and set bits SPTIE, SPRIE, and SPEIE [2] Disable SPII interrupts.
RX23W Group (c) 38. Serial Peripheral Interface (RSPIa) Flow of Error Processing The RSPI has three types of error. When a mode fault error is generated, the SPCR.SPE bit is automatically cleared, stopping operations for transmission and reception. For errors from other sources, however, the SPCR.SPE bit is not cleared and operations for transmission and reception continue; accordingly, we recommend clearing of the SPCR.SPE bit to stop operations in the case of errors other than mode fault errors.
RX23W Group 38.3.10.2 (1) 38. Serial Peripheral Interface (RSPIa) Slave Mode Operation Starting a Serial Transfer If the SPCMD0.CPHA bit is 0, when detecting an SSLA0 input signal assertion, the RSPI needs to start driving valid data to the MISOA output signal. For this reason, when the CPHA bit is 0, the assertion of the SSLA0 input signal triggers the start of a serial transfer.
RX23W Group (4) 38. Serial Peripheral Interface (RSPIa) Burst Transfer If the SPCMD0.CPHA bit is 1, continuous serial transfer (burst transfer) can be executed while retaining the assertion state for the SSLA0 input signal. If the CPHA bit is 1, the period from the first RSPCKA edge to the sampling timing for the reception of the final bit in an SSLA0 signal active state corresponds to a serial transfer period.
RX23W Group (6) 38. Serial Peripheral Interface (RSPIa) Software Processing Flow Figure 38.40 to Figure 38.42 show examples of the flow of software processing. (a) Transmit Processing Flow Pre-transfer processing Processing for transmission Start processing for transmission End of initial settings Clear the SPSR.MODF, OVRF, and PERF flags No SPTI interrupt generated or SPSR.SPTEF = 1?*1 [1] Clear error sources. Yes Write data for transmission to SPDR [2] Disable SPII interrupts. Set SPCR2.
RX23W Group (c) 38. Serial Peripheral Interface (RSPIa) Flow of Error Processing In slave operation, even when a mode fault error is generated, the SPSR.MODF flag can be cleared regardless of the status of the SSLA0 pin. When interrupts are used and an error occurs, if the ICU.IRn.IR flag for the SPTI or SPRI interrupt request is set to 1, clear the ICU.IRn.IR flag in the error processing routine.
RX23W Group 38.3.11 38. Serial Peripheral Interface (RSPIa) Clock Synchronous Operation Setting the SPCR.SPMS bit to 1 selects clock synchronous operation of the RSPI. In clock synchronous operation, the SSLAi pin is not used, and the three pins of RSPCKA, MOSIA, and MISOA handle communications. The SSLAi pin is available as I/O port pins. Although clock synchronous operation does not require use of the SSLAi pin, operation of the module is the same as in SPI operation.
RX23W Group 38. Serial Peripheral Interface (RSPIa) Sequence length setting Determining reference command Loading transfer format settings SPSCR Command pointer control SPCMD0 SPCMD1 SPCMD2 SPCMD3 SPCMD4 SPCMD5 SPCMD6 SPCMD7 CPHA CPOL BRDV[1:0] SSLA[2:0] SSLKP SPB[3:0] LSBF SLNDEN SCKDEN SPCKD SSLND SPNDEN SPND Transfer format determiner Figure 38.
RX23W Group 38. Serial Peripheral Interface (RSPIa) Figure 38.45 shows the relationship between the command and the transmit and receive buffers in the sequence of operations specified by the settings in Table 38.4.
RX23W Group (4) 38. Serial Peripheral Interface (RSPIa) Initialization Flowchart Figure 38.46 is a flowchart illustrating an example of initialization in clock synchronous operation when the RSPI is used in master mode. For a description of how to set up the interrupt controller, DMAC, and I/O ports, refer to the descriptions given in the individual blocks.
RX23W Group (5) 38. Serial Peripheral Interface (RSPIa) Flow of Software Processing Software processing during clock-synchronous master operation is the same as that for SPI master operation. For details, refer to section 38.3.10.1, (9) Software Processing Flow. Note that mode fault errors will not occur. 38.3.11.2 (1) Slave Mode Operation Starting a Serial Transfer When the SPCR.SPMS bit is 1, the first RSPCKA edge triggers the start of a serial transfer in the RSPI.
RX23W Group (3) 38. Serial Peripheral Interface (RSPIa) Initialization Flowchart Figure 38.47 is a flowchart illustrating an example of initialization in clock synchronous operation when the RSPI is used in slave mode. For a description of how to set up the interrupt controller, DMAC, and I/O ports, refer to the descriptions given in the individual blocks.
RX23W Group 38.3.12 38. Serial Peripheral Interface (RSPIa) Loopback Mode When 1 is written to the SPPCR.SPLP2 bit or SPPCR.SPLP bit, the RSPI shuts off the path between the MISOA pin and the shift register if the SPCR.MSTR bit is 1, and between the MOSIA pin and the shift register if the SPCR.MSTR bit is 0, and connects the input path and output path of the shift register. The RSPI does not shut off the path between the MOSIA pin and the shift register if the SPCR.
RX23W Group 38.3.13 38. Serial Peripheral Interface (RSPIa) Self-Diagnosis of Parity Bit Function The parity circuit consists of a parity bit adding unit used for transmit data and an error detecting unit used for received data. In order to detect defects in the parity bit adding unit and error detecting unit of the parity circuit, self-diagnosis is executed for the parity circuit following the flowchart shown in Figure 38.49.
RX23W Group 38.3.14 38. Serial Peripheral Interface (RSPIa) Interrupt Sources The RSPI has interrupt sources of receive buffer full, transmit buffer empty, mode fault, overrun, parity error, and RSPI idle. In addition, the DTC or DMAC can be activated by the receive buffer full or transmit buffer empty interrupt to perform data transfer.
RX23W Group 38.4 38. Serial Peripheral Interface (RSPIa) Link Operation by Event Linking The RSPI0 supports the following event output for the event link controller (ELC). The event link output signal is output regardless of the interrupt enable bit setting. 38.4.1 Receive Buffer Full Event Output This event signal is output when received data have been transferred from the shift register to the SPDR on completion of serial transfer. 38.4.
RX23W Group 38.4.4 (1) 38. Serial Peripheral Interface (RSPIa) RSPI Idle Event Output In Master Mode In master mode, an event is output when the condition for setting the IDLNF flag (RSPI idle flag) to 0 is satisfied. (2) In Slave Mode In slave mode, an event is output when the SPCR.SPE bit is set to 0 (RSPI is initialized). 38.4.
RX23W Group 38.5 38.5.1 38. Serial Peripheral Interface (RSPIa) Usage Notes Setting Module Stop Function Module stop control register B (MSTPCRB) can be used to enable or disable the RSPI. Immediately after a reset, operation of the RSPI is disabled. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption. 38.5.
RX23W Group 39. 39. CRC Calculator (CRC) CRC Calculator (CRC) The CRC (Cyclic Redundancy Check) calculator generates CRC codes. 39.1 Overview Table 39.1 lists the specifications of the CRC calculator, and Figure 39.1 shows a block diagram of the CRC calculator. Table 39.
RX23W Group 39.2 39. CRC Calculator (CRC) Register Descriptions 39.2.1 CRC Control Register (CRCCR) Address(es): 0008 8280h b7 b6 b5 b4 b3 b2 DORCL R — — — — LMS 0 0 0 0 0 0 Value after reset: b1 b0 GPS[1:0] 0 0 Bit Symbol Bit Name Description R/W b1, b0 GPS[1:0] CRC Generating Polynomial Switching b1 b0 R/W b2 LMS CRC Calculation Switching 0: Generates CRC for LSB first communication. 1: Generates CRC for MSB first communication.
RX23W Group 39.2.3 39. CRC Calculator (CRC) CRC Data Output Register (CRCDOR) Address(es): 0008 8282h Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDOR is a readable and writable register. Since its initial value is 0000h, rewrite the CRCDOR register to perform calculation using a value other than the initial value.
RX23W Group 39.3 39. CRC Calculator (CRC) Operation The CRC calculator generates CRC codes for use in LSB first or MSB first transfer. The following shows examples of generating the CRC code for input data (F0h) using the 16-bit CRC generating polynomial (X16 + X12 + X5 + 1). In these examples, the value of the CRC data output register (CRCDOR) is cleared before CRC calculation.
RX23W Group 39. CRC Calculator (CRC) 1. 8-bit serial reception (LSB first) CRC code Data 0 7 7 1 1 1 1 0 1 F 1 1 1 7 0 7 0 0 0 1 1 8 1 1 1 0 1 F 1 1 0 0 F 0 Input 0 0 2. Write 83h to the CRC control register (CRCCR) CRCCR CRCDOR 7 0 1 0 0 0 0 0 1 15 1 0 0 0 0 0 0 0 8 7 0 0 8 7 1 1 0 0 0 0 0 0 0 0 Clear CRCDOR 3.
RX23W Group 39. CRC Calculator (CRC) 1. 8-bit serial reception (MSB first) CRC code Data 0 7 7 Input 1 1 1 1 0 0 F 0 0 1 07 1 0 1 0 1 1 E 1 1 0 0 0 F 0 1 1 1 1 1 1 F 2. Write 87h to the CRC control register (CRCCR) CRCCR CRCDOR 7 0 1 0 0 0 0 1 1 15 1 0 0 0 0 0 0 0 8 7 0 0 8 7 1 0 0 0 0 0 0 0 0 0 Clear CRCDOR 3.
RX23W Group 39.4 39. CRC Calculator (CRC) Usage Notes 39.4.1 Module Stop Function Setting Operation of the CRC calculator can be disabled or enabled using the module stop control register B (MSTPCRB). After a reset, the CRC is in the module stop state. Register access is enabled by releasing the module stop state. For details, refer to section 11, Low Power Consumption. 39.4.
RX23W Group 40. 40. SD Host Interface (SDHIa) SD Host Interface (SDHIa) This MCU incorporates an SD host interface (SDHI) which is compliant with the SD Specifications. When developing host devices that are compliant with the SD Specifications, the user must enter into the SD Host/Ancillary Product License Agreement (SD HALA). 40.1 Overview Table 40.1 lists the SDHI specifications. Table 40.
RX23W Group 40.2 40. SD Host Interface (SDHIa) Register Details 40.2.1 Command Register (SDCMD) SDCMD Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) Table 40.3 lists examples of SDCMD register settings. Table 40.
RX23W Group 40.2.2 40. SD Host Interface (SDHIa) Argument Register (SDARG) SDARG Address(es): SDHI.SDARG 0008 AC08h b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 Value after reset: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 The SDARG register is used for setting the argument field value. Set the SDARG register before setting the SDCMD register.
RX23W Group 40. SD Host Interface (SDHIa) the busy state, the SDSTS1.ACEND flag becomes 1. • Performing a multi-block transfer When the STP bit is set to 1, the SDHI issues CMD12, and the command sequence is stopped. The SD buffer can be accessed even after the STP bit is set to 1, but a buffer access error occurs and the SDSTS2.ILW flag or SDSTS2.ILR flag becomes 1. If the command sequence stops due to a communication error or a timeout, the SDHI does not issue CMD12.
RX23W Group 40.2.5 40. SD Host Interface (SDHIa) Response Register 10 (SDRSP10), Response Register 32 (SDRSP32), Response Register 54 (SDRSP54), Response Register 76 (SDRSP76) • SDRSP10, SDRSP32, SDRSP54 SDRSP10 SDRSP32 SDRSP54 Address(es): SDHI.SDRSP10 0008 AC18h, SDHI.SDRSP32 0008 AC20h, SDHI.
RX23W Group 40.2.6 40. SD Host Interface (SDHIa) SD Status Register 1 (SDSTS1) SDSTS1 Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) RSPEND Flag (Response End Detection Flag) — This flag becomes 1 under any of the following conditions: • A response is received. • A command that does not have a response is issued. • After the R1b response is received, the SDHI is released from the busy state. • During a multi-block transmission, after the SDIOMD.C52PUB bit is set to 1, the CMD52 response is received. • A communication error or timeout causes the command sequence to abort.
RX23W Group 40. SD Host Interface (SDHIa) SDD3RM Flag (SDHI_D3 Removal Flag) — This flag becomes 1 under the following condition: • The SDHI_D3 pin changes from high to low, and the low period is at least two PCLKB cycles. — This flag becomes 0 under the following condition: • The flag is set to 0. SDD3IN Flag (SDHI_D3 Insertion Flag) — This flag becomes 1 under the following condition: • The SDHI_D3 pin changes from low to high, and the high period is at least two PCLKB cycles.
RX23W Group 40.2.7 40. SD Host Interface (SDHIa) SD Status Register 2 (SDSTS2) SDSTS2 Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) The SDSTS2 register indicates the status of the SD buffer and the status of the SD card. Flags to be cleared should be set to 0; flags not being cleared should be set to 1. CMDE Flag (Command Error Detection Flag) The command sequence is stopped when a command error occurs. When the SDIOMD.C52PUB bit is set to 1 and CMD52 is automatically issued, if a communication error or response timeout occurs, the command sequence will not be completed.
RX23W Group 40. SD Host Interface (SDHIa) DTO Flag (Data Timeout Detection Flag) This flag indicates that the data expected to be received during the period specified (set in the SDOPT.TOP[3:0] bits) was not received. However, response timeouts are excluded. The command sequence stops when a data timeout occurs. — This flag becomes 1 under any of the following conditions: • After the R1b response is received, the SDHI is busy for the period specified or longer.
RX23W Group 40. SD Host Interface (SDHIa) BRE Flag (SDBUFR Read Enable Flag) — This flag becomes 1 under any of the following conditions: • During a single block transfer, the data size set in the SDSIZE.LEN[9:0] bits is stored in the SD buffer. • During a multi-block transfer, the data size set in the SDSIZE.LEN[9:0] bits is stored in one of the two SD buffers. — This flag becomes 0 under any of the following conditions: • The bit is set to 0.
RX23W Group 40.2.8 40. SD Host Interface (SDHIa) SD Interrupt Mask Register 1 (SDIMSK1) SDIMSK1 Address(es): SDHI.
RX23W Group 40.2.9 40. SD Host Interface (SDHIa) SD Interrupt Mask Register 2 (SDIMSK2) SDIMSK2 Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.10 SDHI Clock Control Register (SDCLKCR) SDCLKCR Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.11 Transfer Data Size Register (SDSIZE) SDSIZE Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.12 Card Access Option Register (SDOPT) SDOPT Address SDHI.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.13 SD Error Status Register 1 (SDERSTS1) SDERSTS1 Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.14 SD Error Status Register 2 (SDERSTS2) SDERSTS2 Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) Note 3. Set the SDOPT.TOP[3:0] bits to select the number of n cycles. The SDERSTS2 register indicates the timeout status. 40.2.15 SD Buffer Register (SDBUFR) SDBUFR Address(es): SDHI.SDBUFR 0008 AC60h b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Undefined Value after reset: The SDBUFR register is used when writing data to the SD card and when reading data from the SD card.
RX23W Group 40. SD Host Interface (SDHIa) RWREQ Bit (Read Wait Request) If the RWREQ bit is set to 1 during a multi-block read sequence triggered by issuing CMD53, when the current block is done being read, the SDHI enters the read wait state. The method for exiting the read wait state is as follows. • If the RWREQ bit is set to 0 while the SDHI is in the read wait state, the SDHI exits the read wait state.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.17 SDIO Status Register (SDIOSTS) SDIOSTS Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) EXWT Flag (EXWT Status Flag) — This flag becomes 1 under the following condition: • During a multi-block read sequence triggered by CMD53 being issued, the SDIOMD.RWREQ bit is set to 1 while the last block is being transferred. — This flag becomes 0 under the following condition: • The flag is set to 0. 40.2.18 SDIO Interrupt Mask Register (SDIOIMSK) SDIOIMSK Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.19 DMA Transfer Enable Register (SDDMAEN) SDDMAEN Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.20 SDHI Software Reset Register (SDRST) SDRST Address(es): SDHI.
RX23W Group 40. SD Host Interface (SDHIa) 40.2.21 Swap Control Register (SDSWAP) SDSWAP Address(es): SDHI.
RX23W Group 40.3 40. SD Host Interface (SDHIa) SDHI Operation 40.3.1 Data Block Format of the SD Card The SDHI has a default bus mode (1-bit width) that uses just the SDHI_D0 pin as a data line and a wide bus mode (4-bit width) that uses pins SDHI_D0 to SDHI_D3. Figure 40.2 shows the transfer format when the SDOPT.WIDTH bit is 1 (default bus mode), and Figure 40.3 shows the transfer format when the SDOPT.WIDTH bit is 0 (wide bus mode). SDHI_D0 S Start Figure 40.
RX23W Group 40.3.2 40. SD Host Interface (SDHIa) SD Buffer and the SDBUFR Register The SDHI transfers data to an SD card via its internal SD buffer. The SD buffer is comprised of a double buffer, and each buffer is 512 bytes. Figure 40.4 shows the data configuration of a single buffer of the SD buffer’s double buffer. Word 0 1 127 Figure 40.
RX23W Group 40.3.3 40. SD Host Interface (SDHIa) SD Card Detection The SDHI can detect an SD card using either the SDHI_CD pin or SDHI_D3 pin. 40.3.3.1 Using the SDHI_CD Pin to Detect an SD Card Figure 40.6 shows the timing chart for SD card detection using the SDHI_CD pin. The SDHI_CD pin is connected to the card detection switch of the SD card connector, and is pulled-up by the MCU. The pull-up resistance value is determined by the specifications of the host device.
RX23W Group 40.3.4 40. SD Host Interface (SDHIa) SD Card Write Protection The SDHI can disable writing to an SD card via the SDHI_WP pin or a command. 40.3.4.1 Using the SDHI_WP Pin to Enable Write Protection The SDHI_WP pin is connected to the WP detection switch of the SD card connector, and the SDHI_WP pin is pulleddown or pulled-up when an SD card is inserted. The resistance value and whether the SDHI_WP pin is pulled-up or pulled-down are determined by the specifications of the host device.
RX23W Group 40.3.5 40. SD Host Interface (SDHIa) Communication Errors and Timeouts When a communication error or timeout error occurs, depending on the type of error, the corresponding status flag in the SDSTS2 register becomes 1. Also, depending on the source of the error, the corresponding flag in the SDERSTS1 or SDERSTS2 register becomes 1. The status flags in registers SDERSTS1 and SDERSTS2 become 0 by writing to the SDCMD register, or by setting the SDRST.SDRST bit to 0. Table 40.
RX23W Group 40.3.6 40.3.6.1 40. SD Host Interface (SDHIa) Examples of Issuing a Command Command Absent of Response Reception and Data Transfer Figure 40.8 shows an example of no response being received and no data being transferred after the SDHI issues a command. 1. Set the flags in registers SDSTS1 and SDSTS2 to 0. 2. Set the SDHI clock in the SDCLKCR register, and set the interrupt requests to be masked in registers SDIMSK1 and SDIMSK2. Refer to section 40.5.
RX23W Group 40.3.6.2 40. SD Host Interface (SDHIa) Command Absent of Data Transfer Figure 40.9 shows an example of no data being transferred after the SDHI issues a command. 1. Set the flags in registers SDSTS1 and SDSTS2 to 0. 2. Set the SDHI clock in the SDCLKCR register, and set the interrupt requests to be masked in registers SDIMSK1 and SDIMSK2. Refer to section 40.5.5 for details on setting the SDCLKCR register. 3.
RX23W Group 40.3.6.3 40. SD Host Interface (SDHIa) Single Block Read Command (CMD17) Figure 40.10 shows an example of issuing the single block read command (CMD17). 1. Set the flags in registers SDSTS1 and SDSTS2 to 0. 2. Set the SDHI clock in the SDCLKCR register, and set the interrupt requests to be masked in registers SDIMSK1 and SDIMSK2. Refer to section 40.5.5 for details on setting the SDCLKCR register. 3.
RX23W Group 40. SD Host Interface (SDHIa) Start Clear the flag register Set the SDCLKCR register.
RX23W Group 40.3.6.4 40. SD Host Interface (SDHIa) Single Block Write Command (CMD24) Figure 40.11 shows an example of issuing the single block write command (CMD24). 1. Set the flags in registers SDSTS1 and SDSTS2 to 0. 2. Set the SDHI clock in the SDCLKCR register, and set the interrupt requests to be masked in registers SDIMSK1 and SDIMSK2. Refer to section 40.5.5 for details on setting the SDCLKCR register. 3.
RX23W Group 40. SD Host Interface (SDHIa) Start Clear the flag register Set the SDCLKCR register. SDSIZE = Transfer data size SDIMSK1 = 0000 FFFEh SDIMSK2 = 0000 7F80h SDARG = Argument field value SDCMD = 0000 0018h Error (communication error or timeout) Response end or error occurred? CMD24 (single block write) issued No Yes SDSTS1 = 0000 FFFEh Read the SDRSP10 register SDIMSK1 = 0000 FFFBh SDIMSK2 = 0000 7D80h Is the BWE flag 1 or did an error occur? Clear the flags. Check the response.
RX23W Group 40.3.6.5 40. SD Host Interface (SDHIa) Multi-Block Read Command (CMD18) Figure 40.12 shows an example of issuing the multi-block read command (CMD18). 1. Set the flags in registers SDSTS1 and SDSTS2 to 0. 2. Set the SDHI clock in the SDCLKCR register, and set the interrupt requests to be masked in registers SDIMSK1 and SDIMSK2. Refer to section 40.5.5 for details on setting the SDCLKCR register. Set the SDSTOP.
RX23W Group 40.
RX23W Group 40.3.6.6 40. SD Host Interface (SDHIa) Multi-Block Write Command (CMD25) Figure 40.13 shows an example of issuing the multi-block write command (CMD25). 1. Set the flags in registers SDSTS1 and SDSTS2 to 0. 2. Set the SDHI clock in the SDCLKCR register, and set the interrupt requests to be masked in registers SDIMSK1 and SDIMSK2. Refer to section 40.5.5 for details on setting the SDCLKCR register. Set the SDSTOP.
RX23W Group 40. SD Host Interface (SDHIa) Start Clear the flag register Set the SDCLKCR register.
RX23W Group 40.3.6.7 40. SD Host Interface (SDHIa) IO_RW_DIRECT Command (CMD52) Figure 40.14 shows an example of issuing the IO_RW_DIRECT command (CMD52). Start Clear the flag register Set the SDCLKCR register.
RX23W Group 40.3.6.8 40. SD Host Interface (SDHIa) IO_RW_EXTENDED Command (CMD53 (Multi-Block Read)) Figure 40.15 shows an example of issuing the IO_RW_EXTENDED command (CMD53/Multi-block read).
RX23W Group 40. SD Host Interface (SDHIa) Figure 40.16 shows an example of entering the read wait state and then issuing the SDIO none abort command (CMD52) during the IO_RW_EXTENDED command (CMD53/Multi-block read). Start SDIMSK1 = 0000 FFFEh SDIMSK2 = 0000 7F80h SDARG = Argument field value SDIOMD = 0000 0205h Error (communication error or timeout) Did a response end or error occur? No Yes SDSTS1 = 0000 FFFEh Read the SDRSP10 register Was CMD52 issued? Clear the flags. Check the response.
RX23W Group 40.3.6.9 40. SD Host Interface (SDHIa) IO_RW_EXTENDED (CMD53 Multi-Block Write) Figure 40.18 shows an example of issuing the IO_RW_EXTENDED command (CMD53/Multi-block write). Start Clear the flag register Set the SDCLKCR register.
RX23W Group 40. SD Host Interface (SDHIa) Figure 40.19 shows SDIO none abort (CMD52) issued during IO_RW_EXTENDED command (CMD53/Multi-block write) sequence. Start SDSTS1 = 0000 FFFEh SDSTS2 = 0000 7F80h SDARG = Argument field value SDIOMD = 0000 0201h Error (communication error or timeout) Did a response end or error occur? No Yes SDSTS1 = 0000 FFFEh Read the SDRSP10 register Was CMD52 issued? Clear the flags. Check the response.
RX23W Group 40. SD Host Interface (SDHIa) 40.3.6.10 DMA Transfer Figure 40.21 shows an example of data being transferred from the SDBUFR register after the CMD18 multi-block read command is issued.
RX23W Group 40. SD Host Interface (SDHIa) Figure 40.22 shows an example of data being DMA transferred to the SDBUFR register after the CMD25 multi-block write command is issued.
RX23W Group 40.4 40. SD Host Interface (SDHIa) Interrupts Table 40.8 lists the SDHI interrupt sources. When the status flags in registers SDSTS1, SDSTS2, and SDIOSTS become 1, if the corresponding bits in registers SDIMSK1, SDIMSK2, and SDIOIMSK are 0, the SDHI requests an interrupt. When clearing the status flags in registers SDSTS1, SDSTS2, and SDIOSTS, write 0 to the status flags to be cleared and write 1 to the states flags not being cleared. Table 40.
RX23W Group 40.4.1 40. SD Host Interface (SDHIa) DMA Transfer Triggered by Interrupt Requests When the SBFAI interrupt is requested, DMA/DTC transfer can be used to write to or read the SDBUFR register. When using the SBFAI interrupt, set the SDDMAEN.DMAEN bit to 1, the SDIMSK2.BWEM bit to 1, and SDIMSK2.BREM bit to 1. When the SDDMAEN.DMAEN bit is 1, if a write command is issued, the SDSTS2.BWE flag becomes 1; if a read command is issued, the SDSTS2.BRE flag becomes 1.
RX23W Group 40.5 40. SD Host Interface (SDHIa) Notes on Using the SDHI 40.5.1 Illegal Read Access During a Multi-Block Read and How To Avoid It When the multi-block read command (CMD18) is issued to read one or two blocks, if the response to CMD18 stored in the SDRSP10 register is read, the timing of the read access may cause the response to be read incorrectly. Figure 40.23 shows examples of a normal read and an illegal read when using CMD18 to read two blocks.
RX23W Group 40.5.3 40. SD Host Interface (SDHIa) Automatic Control of the SDHI Clock Output As per the SD card specifications, after MCU power-on, 74 cycles of the SDHI clock must be output from the host to the SD card before the card initialization command (CMD0) can be issued. Therefore, 74 cycles of the SDHI clock should be output from the SDHI to the SD card before enabling automatic control of the SDHI clock output.
RX23W Group 41. 41. Bluetooth Low Energy (BLE) Bluetooth Low Energy (BLE) This MCU has a Bluetooth Low Energy (BLE), which consists of an RF transceiver compliant with Bluetooth 5.0 Low Energy (single mode), a link layer, and an RF transceiver power-supply. The BLE is controlled by a Bluetooth middleware available from Renesas Electronics Corporation. 41.1 Overview Table 41.1 lists the Specifications of the BLE. Figure 41.1 is a BLE Block Diagram. Table 41.
VSS_RF VCC_RF DCLIN_D DCLOUT DCLIN_A 41. Bluetooth Low Energy (BLE) AVCC_RF RX23W Group Power amplifier PLL Link layer ANT Matching circuit Modem Low noise amplifier Frequency mixer Low-pass filter Internal peripheral bus RF transceiver power-supply A/D converter RF Transceiver Block Figure 41.1 BLE Block Diagram Table 41.2 lists the BLE I/O Pins. Table 41.
RX23W Group 41. Bluetooth Low Energy (BLE) Figure 41.2 shows an example of the external connection circuit for the 83-pin LGA version of this MCU. This MCU (83-pin LGA) INT_ANT ANT DCLOUT DCLIN_D DCLIN_A XTAL2_RF XTAL1_RF Figure 41.2 Example of the External Connection Circuit (83-Pin LGA) R01UH0823EJ0110 Rev.1.
RX23W Group 41. Bluetooth Low Energy (BLE) Table 41.3 lists the Bluetooth Low Energy functions that this MCU supports. The use of these functions requires the Bluetooth middleware. Table 41.3 List of Supported Bluetooth Low Energy Functions Function Bluetooth® core spec Low Energy Controller (PHY and LL) v4.0 Low Energy Host (L2CAP and Security Manager) Attribute Protocol and Generic Attribute Profile Appearance Data Type v4.
RX23W Group 41.2 41. Bluetooth Low Energy (BLE) Operation 41.2.1 State Transitions Figure 41.3 is the State Transition Diagram of the BLE. Reset RF powerdown mode RF sleep mode Waiting mode Transmit mode Figure 41.3 Receive mode State Transition Diagram of the BLE RF Power-Down Mode The RF power-down mode is the initial mode of the BLE after release from the reset state. Power is supplied to the MCU, but not to the RF transceiver.
RX23W Group 41.3 41. Bluetooth Low Energy (BLE) Interrupts Table 41.4 shows the interrupt sources. The Bluetooth middleware executes processing in response to these interrupts. Do not set the ICU.IERm.IENj bits for these interrupts to 0. Table 41.4 BLE Interrupt Sources Name DTC Activation DMAC Activation BLEIRQ Not possible Not possible ERI Not possible Not possible RXI Possible Possible TXI Possible Possible TEI Not possible Not possible R01UH0823EJ0110 Rev.1.
RX23W Group 41. Bluetooth Low Energy (BLE) Certificates of Compliance 41.4.1 Radio-Related Laws The 83-pin LGA version of this MCU complies with the radio laws listed below. ■ Japan: Certificate of construction type Model number certification number *1 R5F523W8CDLN 🅁🅁006-000937 R5F523W8DDLN 🅁🅁006-000940 ■ North America: FCC (FCC ID: 2AEMXRX23W8DLN), ISED (IC ID: 20194-RX23W8DLN)*1 Europe: CE (RE)*2 ■ Note 1.
RX23W Group 41. Bluetooth Low Energy (BLE) RF exposure considerations This equipment complies with FCC mobile radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 20cm between the radiator & your body. If the module is installed in a portable host, a separate SAR evaluation is required to confirm compliance with relevant FCC portable RF exposure rules. Antennas The antenna of this module is PCB type.
RX23W Group 41. Bluetooth Low Energy (BLE) Remarque concermant les utilisateurs au Canada Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
RX23W Group 41.5 41. Bluetooth Low Energy (BLE) Usage Notes 41.5.1 RF Transceiver Power-Supply In the case of the 85-pin BGA and 56-pin QFN products, the RF transceiver power supply is selectable as either the DCto-DC converter or linear regulator. Only the linear regulator is available for the 83-pin LGA product. Figure 41.4 shows an example of the externally connected circuit for BLE when the DC-to-DC converter is selected (only available for the 85-pin BGA and 56-pin QFN products). Figure 41.
RX23W Group 41. Bluetooth Low Energy (BLE) This MCU DCLIN_D DCLIN_A RF transceiver power-supply Linear regulator Figure 41.6 DCLOUT Example of the BLE Externally Connected Circuit (83-pin LGA) Do not connect other pins or external circuits to the I/O pins (DCLOUT, DCLIN_D, or DCLIN_A) of the RF transceiver power-supply whether the DC to DC converter or linear regulator is selected. 41.5.
RX23W Group 42. 42. Trusted Secure IP (TSIP-Lite) Trusted Secure IP (TSIP-Lite) This MCU incorporates a Trusted Secure IP Lite (TSIP-Lite) module to provide security functions. The module consists of an access management circuit, encryption engine, and random number generator. In combination with the TSIP-Lite library, the TSIP-Lite can prevent eavesdropping (confidentiality), falsification of information (integrity), and impersonation (authenticity).
RX23W Group 42. Trusted Secure IP (TSIP-Lite) TSIP-Lite Bus interface Internal peripheral bus Random number generator Encryption engine Access Management Circuit GHASH Supervisor mode signal Figure 42.1 AES (128 bits/256 bits) Unique ID TSIP-Lite Block Diagram R01UH0823EJ0110 Rev.1.
RX23W Group 42.2 42. Trusted Secure IP (TSIP-Lite) Operation 42.2.1 Operating Modes and State Transitions Figure 42.2 shows the state transitions of the TSIP-Lite. Use of the TSIP-Lite security functions is only possible through use of the TSIP-Lite library provided by Renesas Electronics, in accordance with the state transitions as shown in the figure below.
RX23W Group 42.2.2 42. Trusted Secure IP (TSIP-Lite) Encryption Engine Figure 42.3 shows processes of the encryption engine integrated in the TSIP-Lite. The encryption engine, using the key generation information, performs plaintext to ciphertext encryption and ciphertext to plaintext decryption by hardware. In no part of the encryption or decryption process, is key data or intermediate data ever exposed outside of the TSIP-Lite.
RX23W Group 42.2.3 42. Trusted Secure IP (TSIP-Lite) Key Installation The key installation is the operation that safely converts the user key to the key generation information and stores it in flash memory. The procedure for installing the key data are given below. (1) The user uses the key (Key-2) used for encrypting the user key to encrypt the user key (Key-1) producing eKey-1. (2) The user sends the encrypted user key (eKey-1) to the TSIP-Lite over the serial interface.
RX23W Group 42. Trusted Secure IP (TSIP-Lite) START in encryption engine active mode Input the encrypted user key Decrypt the user key Convert to user key generation information TSIP-Lite library uses the unique ID and a random number Output user key generation information END in TSIP-Lite enabled mode Figure 42.5 42.2.4 Key Installation Flow Chart Encryption and Decryption The procedures for encrypting and decrypting data are given below.
RX23W Group 42. Trusted Secure IP (TSIP-Lite) START in encryption engine active mode Input the key generation information Checking the integrity of the key generation information Setting the key Input of the initialization vector TSIP-Lite library uses the unique ID Only when input of an initialization vector is required Set the DMAC Set the ICU Input the plaintext Encryption of the data Output the encrypted data END in TSIP-Lite enabled mode Figure 42.
RX23W Group 42. Trusted Secure IP (TSIP-Lite) START in encryption engine active mode Input the key generation information Checking the integrity of the key generation information Setting the key Input of the initialization vector TSIP-Lite library uses the unique ID Only when input of an initialization vector is required Set the DMAC Set the ICU Input the ciphertext Decryption of the data Output the decrypted data END in TSIP-Lite enabled mode Figure 42.
RX23W Group 42.2.5 42. Trusted Secure IP (TSIP-Lite) Generating Key Generation Information (by Using Random Numbers) Figure 42.9 shows the generating flow for the key generation information by using random numbers. START in encryption engine active mode Generation of random number Generation of key generation information TSIP-Lite library uses the unique ID Output the key generation information END in TSIP-Lite enabled mode Figure 42.9 42.2.
RX23W Group 42.3 42. Trusted Secure IP (TSIP-Lite) Interrupt Table 42.2 lists the interrupt sources. TSIP-Lite library uses interrupts caused by these interrupt sources. Do not set the ICU.IERm.IENj bits corresponding to these interrupt sources to 0. Table 42.2 TSIP-Lite Interrupt Sources Name Interrupt Source DTC Triggerable DMAC Triggerable RD Data read ready Yes Yes WR Data write ready Yes Yes Error Illegal access detected No No 42.4 42.4.
RX23W Group 43. 43. Capacitive Touch Sensing Unit (CTSU) Capacitive Touch Sensing Unit (CTSU) The capacitive touch sensing unit (CTSU) measures the electrostatic capacitance of the touch sensor. Changes in the electrostatic capacitance are determined by software, which enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode surface of the touch sensor is usually enclosed with a dielectric so that a finger does not come into contact with the electrode.
RX23W Group 43.1 43. Capacitive Touch Sensing Unit (CTSU) Overview Table 43.1 lists the specifications of the CTSU, and Figure 43.3 shows a block diagram of the CTSU. Table 43.
RX23W Group 43.2 43. Capacitive Touch Sensing Unit (CTSU) Register Descriptions 43.2.1 CTSU Control Register 0 (CTSUCR0) Address(es): CTSU.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) CTSUCAP Bit (CTSU Measurement Operation Start Trigger Select) This bit specifies the measurement start condition. For details, see the description of the CTSUSTRT bit. CTSUSNZ Bit (CTSU Wait State Power-Saving Enable) This bit enables or disables power-saving operation during a wait state. This bit can also be used to suspend the CTSU power supply, which decreases power consumption during the wait state.
RX23W Group 43.2.2 43. Capacitive Touch Sensing Unit (CTSU) CTSU Control Register 1 (CTSUCR1) Address(es): CTSU.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) CTSUCLK[1:0] Bits (CTSU Operating Clock Select) These bits select the operating clock. CTSUMD[1:0] Bits (CTSU Measurement Mode Select) These bits set the measurement mode. For details, refer to section 43.3.2, Measurement Modes. 43.2.3 CTSU Synchronous Noise Reduction Setting Register (CTSUSDPRS) Address(es): CTSU.
RX23W Group 43.2.4 43. Capacitive Touch Sensing Unit (CTSU) CTSU Sensor Stabilization Wait Control Register (CTSUSST) Address(es): CTSU.CTSUSST 000A 0903h b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 CTSUSST[7:0] Value after reset: 0 0 0 0 0 Bit Symbol Bit Name Description R/W b7 to b0 CTSUSST[7:0] CTSU Sensor Stabilization Wait Control The value of these bits should be fixed to 00010000b. R/W The CTSUSST register should be set when the CTSUCR0.CTSUSTRT bit is 0.
RX23W Group 43.2.5 43. Capacitive Touch Sensing Unit (CTSU) CTSU Measurement Channel Register 0 (CTSUMCH0) Address(es): CTSU.
RX23W Group 43.2.6 43. Capacitive Touch Sensing Unit (CTSU) CTSU Measurement Channel Register 1 (CTSUMCH1) Address(es): CTSU.CTSUMCH1 000A 0905h Value after reset: b7 b6 — — 0 0 b5 b4 b3 b2 b1 b0 1 1 CTSUMCH1[5:0] 1 1 1 1 Bit Symbol Bit Name Description R/W b5 to b0 CTSUMCH1[5:0] CTSU Measurement Channel 1 b5 R b7, b6 — Reserved These bits are read as 0. Writing to these bits has no effect.
RX23W Group 43.2.7 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Enable Control Register 0 (CTSUCHAC0) Address(es): CTSU.CTSUCHAC0 000A 0906h b7 b6 b5 CTSUC HAC07 — — 0 0 0 Value after reset: b4 b3 b2 CTSUC CTSUC CTSUC HAC04 HAC03 HAC02 0 0 0 b1 b0 — — 0 0 Bit Symbol Bit Name Description R/W b1, b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.8 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Enable Control Register 1 (CTSUCHAC1) Address(es): CTSU.CTSUCHAC1 000A 0907h Value after reset: b7 b6 — — 0 0 b5 b4 CTSUC CTSUC HAC15 HAC14 0 0 b3 b2 b1 b0 — — — CTSUC HAC10 0 0 0 0 Bit Symbol Bit Name Description R/W b0 CTSUCHAC10 CTSU Channel 8 Enable Control 0: Not measurement target 1: Measurement target R/W b3 to b1 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.9 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Enable Control Register 2 (CTSUCHAC2) Address(es): CTSU.CTSUCHAC2 000A 0908h b7 b6 CTSUC CTSUC HAC27 HAC26 Value after reset: 0 0 b5 b4 b3 b2 b1 b0 — — — — — — 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b5 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.10 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Enable Control Register 3 (CTSUCHAC3) Address(es): CTSU.CTSUCHAC3 000A 0909h Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — CTSUC HAC36 — — CTSUC HAC33 — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.11 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Enable Control Register 4 (CTSUCHAC4) Address(es): CTSU.CTSUCHAC4 000A 090Ah Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — CTSUC HAC43 — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.12 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Transmit/Receive Control Register 0 (CTSUCHTRC0) Address(es): CTSU.CTSUCHTRC0 000A 090Bh b7 b6 b5 CTSUC HTRC07 — — 0 0 0 Value after reset: b4 b3 b2 CTSUC CTSUC CTSUC HTRC04 HTRC03 HTRC02 0 0 0 b1 b0 — — 0 0 Bit Symbol Bit Name Description b1, b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.13 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Transmit/Receive Control Register 1 (CTSUCHTRC1) Address(es): CTSU.CTSUCHTRC1 000A 090Ch b7 Value after reset: b6 — — 0 0 b5 b4 CTSUC CTSUC HTRC15 HTRC14 0 0 b3 b2 b1 b0 — — — CTSUC HTRC10 0 0 0 0 Bit Symbol Bit Name Description R/W b0 CTSUCHTRC10 CTSU Channel 8 Transmit/Receive Control 0: Reception 1: Transmission R/W b3 to b1 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.14 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Transmit/Receive Control Register 2 (CTSUCHTRC2) Address(es): CTSU.CTSUCHTRC2 000A 090Dh b7 b6 CTSUC CTSUC HTRC27 HTRC26 Value after reset: 0 0 b5 b4 b3 b2 b1 b0 — — — — — — 0 0 0 0 0 0 Bit Symbol Bit Name Description b5 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.15 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Transmit/Receive Control Register 3 (CTSUCHTRC3) Address(es): CTSU.CTSUCHTRC3 000A 090Eh Value after reset: b7 b6 — CTSUC HTRC36 0 0 b5 b4 b3 b2 b1 b0 — — CTSUC HTRC33 — — — 0 0 0 0 0 0 Bit Symbol Bit Name Description b2 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.16 43. Capacitive Touch Sensing Unit (CTSU) CTSU Channel Transmit/Receive Control Register 4 (CTSUCHTRC4) Address(es): CTSU.CTSUCHTRC4 000A 090Fh b7 Value after reset: b6 b5 b4 b3 b2 b1 b0 — — — 0 0 0 — — — — CTSUC HTRC43 0 0 0 0 0 Bit Symbol Bit Name Description b2 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.17 43. Capacitive Touch Sensing Unit (CTSU) CTSU High-Pass Noise Reduction Control Register (CTSUDCLKC) Address(es): CTSU.CTSUDCLKC 000A 0910h Value after reset: b7 b6 — — 0 0 b5 b4 CTSUSSCNT[1: 0] 0 0 b3 b2 — — 0 0 b1 b0 CTSUSSMOD[1 :0] 0 0 Bit Symbol Bit Name Description R/W b1, b0 CTSUSSMOD[1:0] CTSU Diffusion Clock Mode Select These bits should be set to 00b. R/W b3, b2 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.18 43. Capacitive Touch Sensing Unit (CTSU) CTSU Status Register (CTSUST) Address(es): CTSU.CTSUST 000A 0911h b7 b6 b5 b4 CTSUP CTSUR CTSUS CTSUD S OVF OVF TSR Value after reset: 0 0 0 0 b3 b2 — 0 b1 b0 CTSUSTC[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 CTSUSTC[2:0] CTSU Measurement Status Counter b2 R b3 — Reserved This bit is read as 0. The write value should be 0.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) No interrupt is generated even when an overflow occurs. To determine the channel on which the overflow has occurred, read the measurement result of each channel after measurement is completed (after a measurement end interrupt is generated). This flag is cleared when 0 is written after 1 is read by software. This flag is also cleared using the CTSUCR0.CTSUINIT bit.
RX23W Group 43.2.19 43. Capacitive Touch Sensing Unit (CTSU) CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register (CTSUSSC) Address(es): CTSU.CTSUSSC 000A 0912h b15 b14 b13 b12 — — — — 0 0 0 0 Value after reset: Bit Symbol b7 to b0 b11 to b8 b11 b10 b9 b8 CTSUSSDIV[3:0] 0 0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — — — 0 0 0 0 0 0 0 0 Bit Name Description — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 43.2.20 43. Capacitive Touch Sensing Unit (CTSU) CTSU Sensor Offset Register 0 (CTSUSO0) Address(es): CTSU.CTSUSO0 000A 0914h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 CTSUSNUM[5:0] Value after reset: 0 0 0 0 b5 b4 b3 b2 b1 b0 0 0 0 0 CTSUSO[9:0] 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description b9 to b0 CTSUSO[9:0] CTSU Sensor Offset Adjustment b9 CTSU Measurement Count Setting These bits set the number of measurements.
RX23W Group 43.2.21 43. Capacitive Touch Sensing Unit (CTSU) CTSU Sensor Offset Register 1 (CTSUSO1) Address(es): CTSU.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) CTSURICOA[7:0] Bits (CTSU Reference ICO Current Adjustment) These bits adjust the oscillation frequency using the input current of the reference ICO. CTSUSDPA[4:0] Bits (CTSU Base Clock Setting) These bits are used to generate a base clock used as the source for the sensor drive pulse by dividing the operating clock. For details on the setting procedure, refer to section 43.3.2.1, Initial Setting Flowchart.
RX23W Group 43.2.23 43. Capacitive Touch Sensing Unit (CTSU) CTSU Reference Counter (CTSURC) Address(es): CTSU.CTSURC 000A 091Ah b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 CTSURC[15:0] Value after reset: 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b15 to b0 CTSURC[15:0] CTSU Reference Counter These bits indicate FFFFh when an overflow occurs.
RX23W Group 43.2.24 43. Capacitive Touch Sensing Unit (CTSU) CTSU Error Status Register (CTSUERRS) Address(es): CTSU.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) This bit is cleared by writing 0 to the CTSUCR1.CTSUPON bit and turning off the power supply. R01UH0823EJ0110 Rev.1.
RX23W Group 43.3 43. Capacitive Touch Sensing Unit (CTSU) Operation 43.3.1 Principles of Measurement Operation Figure 43.4 shows the measurement circuit. Power supply LPF Reference electric potential VCC + Control current TSCAP Sensor (electrode) ICO Counter SW1 Sensor drive pulse TSm Switched capacitor filter R = 1/(fC) SW2 Figure 43.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) Reference electric Power potential supply LPF VCC + Control current TSCAP Sensor (electrode) ICO Counter SW1 Sensor drive pulse TSm Switched capacitor filter i = fCV SW2 Figure 43.6 Discharging Operation (m = 2, 3, 4, 7, 8, 12, 13, 22, 23, 27, 30, 35) Number of counts Touching Touch is determined based on the difference Not touching 0 Sensor drive pulse generated Time Figure 43.
RX23W Group 43.3.2 43. Capacitive Touch Sensing Unit (CTSU) Measurement Modes The CTSU supports self-capacitance and mutual capacitance methods. Figure 43.8 illustrates these methods. Receive pin Touch key TS0 Key 1 TS1 TS2 Key 2 Key 3 Key 4 Key 5 TS4 TS1 TS2 TS3 TS4 TS5 TS6 Transmit pin TS3 TS5 Touch key arrangement for self-capacitance method Touch sensor arrangement for mutual capacitance method Figure 43.
RX23W Group 43.3.2.1 43. Capacitive Touch Sensing Unit (CTSU) Initial Setting Flowchart Figure 43.9 shows the flowchart for CTSU initial setting. Discharge external LPF capacitor connected to TSCAP pin Set I/O port Enable CTSU input clock Set CTSU power supply Set CTSU base clock Power on CTSU Wait for stabilization Discharge the external LPF capacitor connected to the MCU by using the TSCAP pin as the I/O port function and driving it low for the specified time.
RX23W Group 43.3.2.2 43. Capacitive Touch Sensing Unit (CTSU) Status Counter The measurement status counter of the CTSU status register (CTSUST) indicates the current measurement status. The measurement status is common to all four modes. Figure 43.11 shows status operation transitions.
RX23W Group 43.3.2.3 43. Capacitive Touch Sensing Unit (CTSU) Self-Capacitance Single Scan Mode Operation In self-capacitance single scan mode, electrostatic capacitance on a channel is measured. Figure 43.12 shows the software flowchart and an operation example, and Figure 43.13 shows the timing chart.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) Sensor stabilization wait time (CTSUSST register) Measurement time Operating clock CTSUCR0.CTSUSTRT bit CTSUMCH0 register 63 CTSUST.CTSUSTC[2:0] flags (Status) 5 0 1 2 3 63 4 (During current/count value conversion) 5 1 0 Sensor ICO clock CTSUSC counter 0 Measurement result CTSUWR interrupt CTSURD interrupt CTSUFN interrupt Sensor drive pulse (1) Figure 43.
RX23W Group 43.3.2.4 43. Capacitive Touch Sensing Unit (CTSU) Self-Capacitance Multi-Scan Mode Operation In self-capacitance multi-scan mode, electrostatic capacitance on all channels that are specified as measurement targets by setting the CTSUCHACn registers (n = 0 to 4) are measured sequentially in ascending order. Figure 43.14 shows the software flowchart and an operation example, and Figure 43.15 shows the timing chart.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) Measurement of channel 2 Sensor stabilization wait time (CTSUSST register) Measurement of channel N Measurement time Operating clock CTSUCR0.CTSUSTRT bit CTSUMCH0 register 63 CTSUST.
RX23W Group 43.3.2.5 43. Capacitive Touch Sensing Unit (CTSU) Mutual Capacitance Full Scan Mode Operation In mutual capacitance full scan mode, measurement is performed during the high-level period of the sensor drive pulse on the receive channel by applying the edge to the target transmit channel to be measured. A single measurement target is measured twice, at the rising and falling edges.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) Measurement of rising edge Sensor stabilization wait time (CTSUSST register) Measurement of falling edge Measurement time Operating clock CTSUCR0.CTSUSTRT bit CTSUMCH0 register (Receive channel) 63 CTSUMCH1 register (Transmit channel) 63 CTSUST.CTSUSTC[2:0] flags (Status) 0 0 1 0 2 1 2 3 4 (During current/count value conversion) 5 1 3 4 (During current/count value conversion) 5 3 4 5 1 2 CTSUST.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) Table 43.8 lists the touch pin states in mutual capacitance full scan mode. Table 43.
RX23W Group 43.3.3 43. Capacitive Touch Sensing Unit (CTSU) Items Common to Multiple Modes 43.3.3.1 Sensor Stabilization Wait Time and Measurement Time Figure 43.18 shows the timing chart of the sensor stabilization wait time and measurement time. (1) Sensor stabilization wait time (CTSUSST register) (2) Measurement time Sensor drive pulse stop period (3) Operating clock CTSUCR0.CTSUSTRT bit (4) Sensor ICO clock CTSUST.
RX23W Group 43.3.3.2 43.
RX23W Group 43. Capacitive Touch Sensing Unit (CTSU) (2) Measurement data transfer request interrupt (CTSURD) Set DTC or ICU transfer corresponding to the CTSURD interrupt in advance. The CTSURD interrupt is output when Status 5 transitions to Status 1. Read the measurement result from the CTSUSC and CTSURC counters (Figure 43.20).
RX23W Group 43.4 43. Capacitive Touch Sensing Unit (CTSU) Usage Notes 43.4.1 Measurement Result Data (CTSUSC and CTSURC Counters) Read access during measurement is prohibited. If the measurement result data is accessed, an incorrect value may be read due to asynchronous operation. 43.4.2 Software Trigger When 10b (PCLK/4) is selected by the CTSUCR1.CTSUCLK[1:0] bits, to restart measurement by writing 1 to the CTSUCR0.
RX23W Group 43.4.4 43. Capacitive Touch Sensing Unit (CTSU) Notes on Forcibly Stopping Operation To forcibly stop the current operation, write 0 to the CTSUCR0.CTSUSTRT bit and 1 to the CTSUCR0.CTSUINIT bit at the same time. After this setting, the operation is stopped and the internal control registers are initialized. When the CTSUCR0.CTSUINIT bit is used for initialization, the following registers are initialized in addition to the initialization of the internal measurement state.
RX23W Group 44. 44. 12-Bit A/D Converter (S12ADE) 12-Bit A/D Converter (S12ADE) In this section, “PCLK” is used to refer to PCLKB. 44.1 Overview This MCU incorporates one unit of a 12-bit successive approximation A/D converter. Up to 14 channel analog inputs, temperature sensor output, and internal reference voltage are selectable for conversion.
RX23W Group Table 44.1 44. 12-Bit A/D Converter (S12ADE) Specifications of 12-Bit A/D Converter (1/2) Item Description Number of units One unit Input channels Up to 14 channels Extended analog function Temperature sensor output, internal reference voltage A/D conversion method Successive approximation method Resolution 12 bits Conversion time 0.
RX23W Group Table 44.1 44. 12-Bit A/D Converter (S12ADE) Specifications of 12-Bit A/D Converter (2/2) Item Description Interrupt sources • In the modes except double trigger mode and group scan mode, A/D scan end interrupt request (S12ADI0) can be generated on completion of single scan. • In double trigger mode, A/D scan end interrupt request (S12ADI0) can be generated on completion of double scan.
RX23W Group Table 44.2 44. 12-Bit A/D Converter (S12ADE) Functions of 12-Bit A/D Converter Pin Name, Abbreviation Item Analog input channels Conditions for A/D conversion start AN000 to AN007, AN016 to AN020, AN027, temperature sensor output, internal reference voltage Software Software trigger Enabled Asynchronous trigger ADTRG0# Enabled Synchronous trigger Compare match/input capture from MTU0.TGRA TRG0AN Compare match/input capture from MTU0.
RX23W Group 44.
RX23W Group 44.2 44. 12-Bit A/D Converter (S12ADE) Register Descriptions 44.2.1 A/D Data Registers y (ADDRy) (y = 0 to 7, 16 to 20, 27), A/D Data Duplication Register (ADDBLDR), A/D Temperature Sensor Data Register (ADTSDR), A/D Internal Reference Voltage Data Register (ADOCDR) Address(es): S12AD.ADDR0 0008 9020h, S12AD.ADDR1 0008 9022h, S12AD.ADDR2 0008 9024h, S12AD.ADDR3 0008 9026h, S12AD.ADDR4 0008 9028h, S12AD.ADDR5 0008 902Ah, S12AD.ADDR6 0008 902Ch, S12AD.ADDR7 0008 902Eh, S12AD.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) The value added by the A/D-converted value of the same channel is stored in bits 15 to 2. Bits 1 and 0 are read as 0. • Flush-left format (A/D-converted value addition mode and 16-time conversion selected) The value added by the A/D-converted value of the same channel is stored in bits 15 to 0. When A/D-converted addition mode is selected, the value added by the A/D-converted value of the same channel is indicated.
RX23W Group 44.2.2 44. 12-Bit A/D Converter (S12ADE) A/D Self-Diagnosis Data Register (ADRD) Address(es): S12AD.ADRD 0008 901Eh Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADRD is a 16-bit read-only register that stores the A/D conversion results based on the 12-bit A/D converter’s selfdiagnosis. In addition to the A/D-converted value, the self-diagnosis status is included in.
RX23W Group 44.2.3 44. 12-Bit A/D Converter (S12ADE) A/D Control Register (ADCSR) Address(es): S12AD.ADCSR 0008 9000h b15 ADST Value after reset: 0 b14 b13 ADCS[1:0] 0 0 b12 b11 ADIE — 0 0 b10 b9 b8 b7 ADHSC TRGE EXTRG DBLE 0 0 0 b6 b5 GBADI E — 0 0 0 b4 b3 b2 b1 b0 0 0 DBLANS[4:0] 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 DBLANS[4:0] Double Trigger Channel Select These bits select one analog input channel for double triggered operation.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) not be set simultaneously when 1 is written to the ADST bit. To enter A/D-converted value addition/average mode while double trigger mode is set, the channel selected by the DBLANS[4:0] bits should be selected in the ADANSA0 and ADANSA1 registers. Table 44.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) is set to 1 as long as the scan is started by the synchronous trigger selected by the ADSTRGR.TRSA[5:0] bits. ADCS[1:0] Bits (Scan Mode Select) The ADCS[1:0] bits select the scan mode.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) • Group A scan is completed in group scan mode. • Group B scan is completed in group scan mode. • With group-A priority control operation mode enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit = 1), a group A trigger is detected during group B A/D conversion and the scanning of group B is stopped. • With group-A priority control operation mode enabled (ADCSR.ADCS[1:0] bits = 01b and ADGSPCR.PGS bit = 1), the ADGSPCR.
RX23W Group 44.2.5 44. 12-Bit A/D Converter (S12ADE) A/D Channel Select Register A1 (ADANSA1) Address(es): S12AD.ADANSA1 0008 9006h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 — — — — ANSA1 11 — — — — — — 0 0 0 0 0 0 0 0 0 0 0 Value after reset: b4 b3 b2 b1 b0 ANSA1 ANSA1 ANSA1 ANSA1 ANSA1 04 03 02 01 00 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 ANSA100 A/D Conversion Channel Select R/W b1 ANSA101 0: AN016 to AN020 are not subjected to conversion.
RX23W Group 44.2.6 44. 12-Bit A/D Converter (S12ADE) A/D Channel Select Register B0 (ADANSB0) Address(es): S12AD.
RX23W Group 44.2.7 44. 12-Bit A/D Converter (S12ADE) A/D Channel Select Register B1 (ADANSB1) Address(es): S12AD.ADANSB1 0008 9016h b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 — — — — ANSB1 11 — — — — — — 0 0 0 0 0 0 0 0 0 0 0 Value after reset: b4 b3 b2 b1 b0 ANSB1 ANSB1 ANSB1 ANSB1 ANSB1 04 03 02 01 00 0 0 0 0 0 Bit Symbol Bit Name Description R/W b0 ANSB100 A/D Conversion Channel Select R/W b1 ANSB101 0: AN016 to AN020 are not subjected to conversion.
RX23W Group 44.2.8 44. 12-Bit A/D Converter (S12ADE) A/D-Converted Value Addition/Average Function Select Register 0 (ADADS0) Address(es): S12AD.
RX23W Group 44.2.9 44. 12-Bit A/D Converter (S12ADE) A/D-Converted Value Addition/Average Function Select Register 1 (ADADS1) Address(es): S12AD.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) Continuous conversion count 4 times 3 times 2 times 1 time AN002 AN006 AN002 AN002 AN006 AN002 AN002 AN006 AN002 AN000 AN001 AN002 AN003 AN004 AN005 AN006 AN007 AN000 AN001 AN002 • • • Conversion in progress Figure 44.2 Scan Conversion Sequence with ADADC.ADC[2:0] = 011b, ADS002 = 1, and ADS006 = 1 R01UH0823EJ0110 Rev.1.
RX23W Group 44.2.10 44. 12-Bit A/D Converter (S12ADE) A/D-Converted Value Addition/Average Count Select Register (ADADC) Address(es): S12AD.ADADC 0008 900Ch b7 b6 b5 b4 b3 AVEE — — — — 0 0 0 0 0 Value after reset: b2 b1 b0 ADC[2:0] 0 0 0 Bit Symbol Bit Name Description R/W b2 to b0 ADC[2:0] Addition Count Select b2 R/W b6 to b3 — Reserved These bits are read as 0. The write value should be 0. R/W b7 AVEE Average Mode Enable 0: Addition mode is selected.
RX23W Group 44.2.11 44. 12-Bit A/D Converter (S12ADE) A/D Control Extended Register (ADCER) Address(es): S12AD.ADCER 0008 900Eh b15 b14 b13 b12 ADRFM T — — — 0 0 0 0 Value after reset: b11 b10 DIAGM DIAGL D 0 0 b9 b8 DIAGVAL[1:0] 0 0 b7 b6 b5 b4 b3 b2 b1 b0 — — ACE — — — — — 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b4 to b0 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) DIAGM Bit (Self-Diagnosis Enable) The DIAGM bit enables or disables self-diagnosis. Self-diagnosis is used to detect a failure of the 12-bit A/D converter. Specifically, one of the internally generated voltage values 0, the reference voltage × 1/2, and the reference voltage is converted. When conversion is completed, information on the converted voltage and the conversion result is stored into the self-diagnosis data register (ADRD).
RX23W Group 44.2.12 44. 12-Bit A/D Converter (S12ADE) A/D Conversion Start Trigger Select Register (ADSTRGR) Address(es): S12AD.ADSTRGR 0008 9010h Value after reset: b15 b14 — — 0 0 b13 b12 b11 b10 b9 b8 TRSA[5:0] 0 0 0 0 0 0 b7 b6 — — 0 0 b5 b4 b3 b2 b1 b0 0 0 TRSB[5:0] 0 0 0 0 Bit Symbol Bit Name Description R/W b5 to b0 TRSB[5:0] A/D Conversion Start Trigger Select for Group B Select the A/D conversion start trigger for group B in group scan mode.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) Table 44.7 lists the selection of A/D conversion start sources selected by the TRSA[5:0] bits. Table 44.6 Module Selection of A/D Activation Sources by the TRSB[5:0] Bits Source Remarks Trigger source deselection state MTU TPU ELC Table 44.7 Module 1 MTU TPU ELC 1 1 1 1 1 TRG0AN Compare match/input capture from MTU0.TGRA 0 0 0 0 0 1 TRG0BN Compare match/input capture from MTU0.
RX23W Group 44.2.13 44. 12-Bit A/D Converter (S12ADE) A/D Conversion Extended Input Control Register (ADEXICR) Address(es): S12AD.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) Sampling starts after discharging is completed during A/D conversion of the temperature sensor output, an autodischarging period of 15 ADCLK cycles is inserted before sampling. OCSA Bit (Internal Reference Voltage A/D Conversion Select) This bit selects A/D conversion of the internal reference voltage in single scan mode.
RX23W Group 44.2.14 44. 12-Bit A/D Converter (S12ADE) A/D Sampling State Register n (ADSSTRn) (n = 0 to 7, L, T, O) Address(es): S12AD.ADSSTRL 0008 90DDh, S12AD.ADSSTRT 0008 90DEh, S12AD.ADSSTRO 0008 90DFh, S12AD.ADSSTR0 0008 90E0h, S12AD.ADSSTR1 0008 90E1h, S12AD.ADSSTR2 0008 90E2h, S12AD.ADSSTR3 0008 90E3h, S12AD.ADSSTR4 0008 90E4h, S12AD.ADSSTR5 0008 90E5h, S12AD.ADSSTR6 0008 90E6h, S12AD.
RX23W Group 44.2.15 44. 12-Bit A/D Converter (S12ADE) A/D Disconnection Detection Control Register (ADDISCR) Address(es): S12AD.
RX23W Group 44.2.16 44. 12-Bit A/D Converter (S12ADE) A/D Event Link Control Register (ADELCCR) Address(es): S12AD.ADELCCR 0008 907Dh Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — — — — — ELCC[1:0] 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W b1, b0 ELCC[1:0] Event Link Control b1 b0 R/W b7 to b2 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 44.2.17 44. 12-Bit A/D Converter (S12ADE) A/D Group Scan Priority Control Register (ADGSPCR) Address(es): S12AD.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) GBRSCN bit. The ADCSR.ADST bit must be 0 when the GBRP bit is to be set. The setting of the GBRP bit is enabled when the PGS bit is 1. 44.2.18 A/D Compare Function Control Register (ADCMPCR) Address(es): S12AD.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) • A/D channel select registers A0/A1/B0/B1 (ADANSA0, ADANSA1, ADANSB0, ADANSB1) • OCSA or TSSA in the A/D conversion extended input control register (ADEXICR.OCSA, TSSA) • CMPCHB[5:0] in the window B channel select register (ADCMPBNSR.CMPCHB[5:0]) CMPAE Bit (Compare Window A Operation Enable) This bit enables or disables the compare window A operation. The CMPAE bit should be set while the ADCSR.ADST bit is 0.
RX23W Group 44.2.19 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Channel Select Register 0 (ADCMPANSR0) Address(es): S12AD.
RX23W Group 44.2.20 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Channel Select Register 1 (ADCMPANSR1) Address(es): S12AD.
RX23W Group 44.2.21 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Extended Input Select Register (ADCMPANSER) Address(es): S12AD.ADCMPANSER 0008 9092h b7 Value after reset: b6 b5 b4 b3 b2 — — — — — — 0 0 0 0 0 0 b1 b0 CMPO CMPTS CA A 0 0 Bit Symbol Bit Name Description R/W b0 CMPTSA Temperature Sensor Output Compare Select 0: Temperature sensor output is not a target for compare window A. 1: Temperature sensor output is a target for compare window A.
RX23W Group 44.2.22 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Comparison Condition Setting Register 0 (ADCMPLR0) Address(es): S12AD.
RX23W Group 44.2.23 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Comparison Condition Setting Register 1 (ADCMPLR1) Address(es): S12AD.
RX23W Group 44.2.24 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Extended Input Comparison Condition Setting Register (ADCMPLER) Address(es): S12AD.ADCMPLER 0008 9093h b7 Value after reset: b6 b5 b4 b3 b2 — — — — — — 0 0 0 0 0 0 b1 b0 CMPLO CMPLT CA SA 0 0 Bit Symbol Bit Name Description R/W b0 CMPLTSA Compare Window A Temperature Sensor Output Comparison Condition Select When the window function is disabled (ADCMPCR.
RX23W Group 44.2.25 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Lower-Side Level Setting Register (ADCMPDR0) Address(es): S12AD.ADCMPDR0 0008 909Ch Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCMPDR0 is a readable/writable register that sets the reference data when the compare window A function is used. ADCMPDR0 sets the lower-side level of window A.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) Set bits 15 to 2 to the lower-side comparison level for comparison with the A/D-converted value of the same channel. Write 0 to bits 1 and 0. • Flush-left format (A/D-converted value addition mode and 16-time conversion selected) Set bits 15 to 0 to the lower-side comparison level for comparison with the A/D-converted value of the same channel. When A/D-converted addition mode is selected, set the value added by the A/D-converted value of the same channel.
RX23W Group 44.2.26 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Upper-Side Level Setting Register (ADCMPDR1) Address(es): S12AD.ADCMPDR1 0008 909Eh Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADCMPDR1 is a readable/writable register that sets the reference data when the compare window A function is used. ADCMPDR1 sets the upper-side level of window A.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) • Flush-left format (A/D-converted value addition mode and 1-time to 4-time conversion selected) • Set bits 15 to 2 to the upper-side comparison level for comparison with the A/D-converted value of the same channel. Write 0 to bits 1 and 0. • Flush-left format (A/D-converted value addition mode and 16-time conversion selected) Set bits 15 to 0 to the upper-side comparison level for comparison with the A/D-converted value of the same channel.
RX23W Group 44.2.28 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Channel Status Register 1 (ADCMPSR1) Address(es): S12AD.
RX23W Group 44.2.29 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A Extended Input Channel Status Register (ADCMPSER) Address(es): S12AD.ADCMPSER 0008 90A4h b7 Value after reset: b6 b5 b4 b3 b2 — — — — — — 0 0 0 0 0 0 b1 b0 CMPST CMPST OCA TSA 0 0 Bit Symbol Bit Name Description R/W b0 CMPSTTSA Compare Window A Temperature Sensor Output Compare Flag When window A operation is enabled (ADCMPCR.
RX23W Group 44.2.30 44. 12-Bit A/D Converter (S12ADE) A/D High-Potential/Low-Potential Reference Voltage Control Register (ADHVREFCNT) Address(es): S12AD.ADHVREFCNT 0008 908Ah b7 b6 b5 b4 b3 b2 b1 ADSLP — — LVSEL — — HVSEL[1:0] 0 0 0 0 0 0 Value after reset: 0 b0 0 Bit Symbol Bit Name Description R/W b1, b0 HVSEL[1:0] High-Potential Reference Voltage Select b1 b0 R/W b3, b2 — Reserved These bits are read as 0. The write value should be 0.
RX23W Group 44.2.31 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window A/B Status Monitor Register (ADWINMON) Address(es): S12AD.ADWINMON 0008 908Ch Value after reset: b7 b6 — — 0 0 b5 b4 MONC MONC MPB MPA 0 0 b3 b2 b1 b0 — — — MONC OMB 0 0 0 0 Bit Symbol Bit Name Description R/W b0 MONCOMB Combination Result Monitor Flag This flag indicates the combination result. This flag is valid when both window A operation and window B operation are enabled.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) [Clearing conditions] • The A/D-converted value does not meet the condition set by ADCMPBNSR.CMPLB bit when ADCMPCR.CMPBE = 1. • ADCMPCR.CMPBE = 0 (Automatically cleared when the ADCMPCR.CMPBE bit value changes from 1 to 0.) 44.2.32 A/D Compare Function Window B Channel Select Register (ADCMPBNSR) Address(es): S12AD.
RX23W Group 44.
RX23W Group 44.2.33 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window B Lower-Side Level Setting Register (ADWINLLB) Address(es): S12AD.ADWINLLB 0008 90A8h Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADWINLLB is a readable/writable register that sets the reference data when the compare window B function is used. ADWINLLB sets the lower-side level of window B.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) Set bits 15 to 2 to the lower-side comparison level for comparison with the A/D-converted value of the same channel. Write 0 to bits 1 and 0. • Flush-left format (A/D-converted value addition mode and 16-time conversion selected) Set bits 15 to 0 to the lower-side comparison level for comparison with the A/D-converted value of the same channel. When A/D-converted addition mode is selected, set the value added by the A/D-converted value of the same channel.
RX23W Group 44.2.34 44. 12-Bit A/D Converter (S12ADE) A/D Compare Function Window B Upper-Side Level Setting Register (ADWINULB) Address(es): S12AD.ADWINULB 0008 90AAh Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADWINULB is a readable/writable register that sets the reference data when the compare window B function is used. ADWINULB sets the upper-side level of window B.
RX23W Group 44. 12-Bit A/D Converter (S12ADE) • Flush-left format (A/D-converted value addition mode and 1-time to 4-time conversion selected) Set bits 15 to 2 to the upper-side comparison level for comparison with the A/D-converted value of the same channel. Write 0 to bits 1 and 0. • Flush-left format (A/D-converted value addition mode and 16-time conversion selected) Set bits 15 to 0 to the upper-side comparison level for comparison with the A/D-converted value of the same channel.
RX23W Group 44.2.36 44. 12-Bit A/D Converter (S12ADE) A/D Data Storage Buffer Register n (ADBUFn) (n = 0 to 15) Address(es): S12AD.ADBUF0 0008 90B0h, S12AD.ADBUF1 0008 90B2h, S12AD.ADBUF2 0008 90B4h, S12AD.ADBUF3 0008 90B6h, S12AD.ADBUF4 0008 90B8h, S12AD.ADBUF5 0008 90BAh, S12AD.ADBUF6 0008 90BCh, S12AD.ADBUF7 0008 90BEh, S12AD.ADBUF8 0008 90C0h, S12AD.ADBUF9 0008 90C2h, S12AD.ADBUF10 0008 90C4h, S12AD.ADBUF11 0008 90C6h, S12AD.ADBUF12 0008 90C8h, S12AD.ADBUF13 0008 90CAh, S12AD.