Manual

ManualsBrandsRainbow Electronics ManualsStorageAT25256A

8-lead SOIC

GND

VCC

HOLD

SCK

Features

• Serial Peripheral Interface (SPI) Compatible

• Supports SPI Modes 0 (0,0) and 3 (1,1)

• Medium-voltage and Standard-voltage Operation

– 5.0 (V

= 4.5V to 5.5V)

– 2.7 (V

= 2.7V to 5.5V)

• 3 MHz Clock Rate (5V)

• 64-byte Page Mode and Byte Write Operation

• Block Write Protection

– Protect 1/4, 1/2, or Entire Array

• Write Protect (WP) Pin and Write Disable Instructions for

both Hardware and Software Data Protection

• Self-timed Write Cycle (5 ms Typical)

• High-reliability

– Endurance: 100,000 Write Cycles

– Data Retention: >200 Years

• 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead EIAJ SOIC Packages

Description

The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro-

grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits

each. The device is optimized for use in many industrial and commercial applications

where low-power and low-voltage operation are essential. The devices are available in

space saving 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead EIAJ SOIC (AT25256A)

packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V) and 2.7V

(2.7V to 5.5V) versions.

Rev. 3404A–SEEPR–10/03

SPI Serial

Automotive

EEPROMs

128K (16,384 x 8)

256K (32,768 x 8)

AT25128A

AT25256A

Preliminary

Pin Configurations

Pin Name Function

Chip Select

SCK Serial Data Clock

SI Serial Data Input

SO Serial Data Output

GND Ground

VCC Power Supply

Write Protect

HOLD

Suspends Serial Input

NC No Connect

DC Don't Connect

8-lead PDIP

GND

VCC

HOLD

SCK

Summary of content (18 pages)

PAGE 1
Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • Medium-voltage and Standard-voltage Operation • • • • • • • – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.
PAGE 2
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection.
PAGE 3
AT25128A/256A [Preliminary] Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Symbol Test Conditions COUT CIN Note: Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from TA = -40°C to +125°C, VCC = +2.7V to +5.
PAGE 4
AC Characteristics Applicable over recommended operating range from TA = -40°C to +125°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 - 5.5 2.7 - 5.5 0 0 3.0 2.1 MHz tRI Input Rise Time 4.5 - 5.5 2.7 - 5.5 2 2 µs tFI Input Fall Time 4.5 - 5.5 2.7 - 5.5 2 2 µs tWH SCK High Time 4.5 - 5.5 2.7 - 5.5 150 200 ns tWL SCK Low Time 4.5 - 5.5 2.7 - 5.5 150 200 ns tCS CS High Time 4.
PAGE 5
AT25128A/256A [Preliminary] Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25128A/256A always operates as a slave. TRANSMITTER/RECEIVER: The AT25128A/256A has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
PAGE 6
SPI Serial Interface AT25128A/256A Functional Description The AT25128A/256A is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128A/256A utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition.. Table 1.
PAGE 7
AT25128A/256A [Preliminary] WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin.
PAGE 8
The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0.
PAGE 9
AT25128A/256A [Preliminary] The AT25128A/256A is capable of a 64-byte PAGE WRITE operation. After each byte of data is received, the six low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25128A/256A is automatically returned to the write disable state at the completion of a WRITE cycle.
PAGE 10
Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing t CS VIH CS VIL t CSH t CSS VIH t WH SCK t WL VIL tH t SU VIH SI VALID IN VIL tV VOH SO HI-Z t HO t DIS HI-Z VOL WREN Timing WRDI Timing 10 AT25128A/256A [Preliminary] 3404A–SEEPR–10/03
PAGE 11
AT25128A/256A [Preliminary] RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 7 6 5 11 12 13 14 15 2 1 0 SCK SI SO INSTRUCTION HIGH IMPEDANCE DATA OUT 4 3 MSB WRSR Timing READ Timing 11 3404A–SEEPR–10/03
PAGE 12
WRITE Timing HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ 12 AT25128A/256A [Preliminary] 3404A–SEEPR–10/03
PAGE 13
AT25128A/256A [Preliminary] AT25128A Ordering Information Ordering Code Package Operation Range AT25128A-10PA-5.0C AT25128AN-10SA-5.0C 8P3 8S1 Automotive (-40°C to 125°C) AT25128A-10PA-2.7C AT25128AN-10SA-2.7C 8P3 8S1 Automotive (-40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) Options -5.0 Standard Device (4.5V to 5.5V) -2.7 Low-voltage (2.7V to 5.
PAGE 14
AT25256A Ordering Information Ordering Code Package Operation Range AT25256A-10PA-5.0C AT25256AN-10SA-5.0C AT25256AW-10SA-5.0C 8P3 8S1 8S2 Automotive (-40°C to 125°C) AT25256A-10PA-2.7C AT25256AN-10SA-2.7C AT25256AW-10SA-2.7C 8P3 8S1 8S2 Automotive (-40°C to 125°C) Package Type 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.
PAGE 15
AT25128A/256A [Preliminary] Packaging Information 8P3 – PDIP E 1 E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D e D1 A2 A MIN NOM A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 D1 0.005 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 SYMBOL A b2 b3 b 4 PLCS Side View L Notes: 0.210 0.100 BSC eA 0.300 BSC 0.115 NOTE 2 3 3 e L MAX 0.
PAGE 16
8S1 – JEDEC SOIC 1 E E1 N L A1 Top View End View e b A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D Side View MIN NOM MAX A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e L NOTE 1.27 BSC 0.40 – 1.27 Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/3/03 R 16 1150 E. Cheyenne Mtn. Blvd.
PAGE 17
AT25128A/256A [Preliminary] 8S2 – EIAJ SOIC 1 E N Top View e b A D COMMON DIMENSIONS (Unit of Measure = mm) Side View SYMBOL C A1 L E1 End View NOM MAX NOTE A 1.70 2.16 A1 0.05 0.25 b 0.35 0.48 5 C 0.15 0.35 5 D 5.13 5.35 E1 5.18 5.40 E 7.70 8.26 L 0.51 e Notes: 1. 2. 3. 4. 5. MIN 2, 3 0.85 1.27 BSC 4 This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
PAGE 18
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg.