SC650T Hardware Design Smart LTE Module Series Rev: SC650T_Hardware_Design_V1.1 Date: 2019-03-01 Status: Preliminary www.quectel.
Smart LTE Module Series SC650T Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. Building 5, Shanghai Business Park Phase III (Area B), No.1016 Tianlin Road, Minhang District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
Smart LTE Module Series SC650T Hardware Design About the Document History Revision Date Author Description 1.
Smart LTE Module Series SC650T Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index .....................................................................................................................................
Smart LTE Module Series SC650T Hardware Design 3.21.2. Flashlight Interfaces ..................................................................................................... 73 3.22. Sensor Interfaces ................................................................................................................... 74 3.23. Audio Interfaces ..................................................................................................................... 74 3.23.1.
Smart LTE Module Series SC650T Hardware Design 9 Storage, Manufacturing and Packaging ...................................................................................... 106 9.1. Storage ................................................................................................................................. 106 9.2. Manufacturing and Soldering ................................................................................................ 107 9.3. Packaging......................................
Smart LTE Module Series SC650T Hardware Design Table Index TABLE 1: SC650T-NA FREQUENCY BANDS .................................................................................................. 15 TABLE 2: SC650T-EM FREQUENCY BANDS .................................................................................................. 15 TABLE 3: SC650T KEY FEATURES .................................................................................................................
Smart LTE Module Series SC650T Hardware Design TABLE 42: SC650T MODULE POWER SUPPLY RATINGS ............................................................................ 96 TABLE 43: OPERATION AND STORAGE TEMPERATURES .......................................................................... 97 TABLE 44: SC650T-NA CURRENT CONSUMPTION ....................................................................................... 98 TABLE 45: SC650T-EM CURRENT CONSUMPTION .............................................
Smart LTE Module Series SC650T Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 18 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 21 FIGURE 3: VOLTAGE DROP SAMPLE.............................................................................................................
Smart LTE Module Series SC650T Hardware Design GROUND) .................................................................................................................................................. 90 FIGURE 39: REFERENCE CIRCUIT DESIGN FOR WI-FI/BT ANTENNA INTERFACE .................................. 91 FIGURE 40: REFERENCE CIRCUIT DESIGN FOR GNSS PASSIVE ANTENNA ........................................... 92 FIGURE 41: REFERENCE CIRCUIT DESIGN FOR GNSS ACTIVE ANTENNA .................................
Smart LTE Module Series SC650T Hardware Design OEM/Integrators Installation Manual Important Notice to OEM integrators 1. This module is limited to OEM installation ONLY. 2. This module is limited to installation in mobile or fixed applications, according to Part 2.1091(b). 3. The separate approval is required for all other operating configurations, including portable configurations with respect to Part 2.1093 and different antenna configurations 4. For FCC Part 15.
Smart LTE Module Series SC650T Hardware Design be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures: - Reorient or relocate the receiving antenna. - Increase the separation between the equipment and receiver. - Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. - Consult the dealer or an experienced radio/TV technician for help.
Smart LTE Module Series SC650T Hardware Design point à point et non point à point, selon le cas CAN ICES-3(B)/ NMB-3(B) Radiation Exposure Statement This equipment complies with FCC/IC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with minimum distance 20 cm between the radiator & your body.
Smart LTE Module Series SC650T Hardware Design 1 Introduction This document defines the SC650T module and describes its air interface and hardware interface which are connected with customers’ applications. This document can help customers quickly understand module interface specifications, electrical and mechanical details as well as other related information of SC650T module.
Smart LTE Module Series SC650T Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating SC650T module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
Smart LTE Module Series SC650T Hardware Design 2 Product Concept 2.1. General Description SC650T is a series of Smart LTE module based on Qualcomm platform and Android operating system, and provides industrial grade performance. Its general features are listed below: Support worldwide LTE-FDD Support short-range wireless communication via Wi-Fi 802.11a/b/g/n/ac and BT4.
Smart LTE Module Series SC650T Hardware Design LTE-FDD B1/B3/B7/B20/B28 Wi-Fi 802.11a/b/g/n/ac 2402MHz~2482MHz; 5180MHz~5825MHz BT4.2 LE 2402MHz~2480MHz GNSS GPS: 1575.42MHz±1.023MHz GLONASS: 1597.5MHz~1605.8MHz BeiDou: 1561.098MHz±2.046MHz SC650T is an SMD type module which can be embedded into applications through its 323 pins (including 152 LCC pads and 171 LGA pads). With a compact profile of 43.0mm × 44.0mm × 2.
Smart LTE Module Series SC650T Hardware Design Cat 4 FDD: Max 150Mbps (DL)/Max 50Mbps (UL) WLAN Features 2.4GHz/5GHz, support 802.11a/b/g/n/ac, maximally up to 433Mbps Support AP and STA mode Bluetooth Features BT4.2 LE GNSS Features GPS/GLONASS/BeiDou SMS Text and PDU mode Point-to-point MO and MT SMS cell broadcast LCM Interfaces Support two groups of 4-lane MIPI_DSI Support dual LCDs Support WUXGA up to (1920×1200) at 60fps Camera Interfaces Support two groups of 4-lane MIPI_CSI, up to 2.
Smart LTE Module Series SC650T Hardware Design Support Dual SIM Dual Standby (supported by default) I2C Interfaces Five I2C interfaces, used for peripherals such as TP, camera, sensor, etc. I2S Interface Support for I2S peripherals Flashlight Interface 2 high current Flash and torch LED driver 1A for Flash mode and 300mA for torch mode by default 1.
Smart LTE Module Series SC650T Hardware Design 2.3. Evaluation Board In order to help customers develop applications with SC650T conveniently, Quectel supplies the evaluation board, USB to RS232 converter cable, USB Type-C data cable, power adapter, earphone, antenna and other peripherals to control or test the module. For more details, please refer to document [1].
Smart LTE Module Series SC650T Hardware Design 3 Application Interfaces 3.1. General Description SC650T is equipped with 323-pin 1.0mm pitch SMT pads that can be embedded into cellular application platform. The following chapters provide the detailed description of pins/interfaces listed below.
Smart LTE Module Series SC650T Hardware Design 3.2. Pin Assignment The following figure shows the pin assignment of SC650T module.
Smart LTE Module Series SC650T Hardware Design 3.3. Pin Description Table 4: I/O Parameters Definition Type Description IO Bidirectional DI Digital input DO Digital output PI Power input PO Power output AI Analog input AO Analog output OD Open drain The following tables show the SC650T’s pin definition and electrical characteristics. Table 5: Pin Description Power Supply Pin Name VBAT Pin No. 36，37，38 DC Characteristics Comment PI/PO Power supply for the battery. Vmax=4.
Smart LTE Module Series SC650T Hardware Design VRTC LDO5_1P8 LDO10_2P8 LDO6_1P8 LDO17_2P85 LDO13_3P07 5 LDO23_1P2 16 9 11 10 12 157 15 SC650T_Hardware_Design PI/PO PO PO PO PO PO PO module. Vmin=3.55V Vnorm=3.8V Power supply for internal RTC circuit VOmax=3.2V VI=2.0V~3.25V 1.8V output power supply 2.8V output power supply 1.8V output power supply 2.85V output power supply 13.125V output power supply 1.2V output power supply interface Vnorm=1.
Smart LTE Module Series SC650T Hardware Design used. If unused, keep this pin open. LDO2_1P1 13 LDO22_2P8 14 GND 3,4,18,20,3 1,34,35,40, 43,47,56,6 2,87,98,10 1,112,125, 128,130,13 3,135,148, 150,159,16 0,163,170, 173,176,18 2,193,195, 219,243,25 7--323 PO PO 1.1V output power supply 2.8V output power supply Vnorm=1.1V IOmax=1200mA Power supply for DVDD of rear cameras. Add a 1.0uF~2.2uF bypass capacitor if used. If unused, keep this pin open. Vnorm=2.
Smart LTE Module Series SC650T Hardware Design MIC_BIAS1 44 AO Microphone bias voltage VO=1.6V~2.85V Dias voltage for DMIC1 MIC_BIAS2 233 AO Microphone bias voltage VO=1.6V~2.85V Dias voltage for AMIC2 MIC_BIAS3 167 AO Microphone bias voltage VO=1.6V~2.
Smart LTE Module Series SC650T Hardware Design HS_DET 48 AI Headset insertion detection Pin No. I/O Description DC Characteristics Vmax=10V Vmin=4V Vnorm=5.0V Pulled up internally. USB Interface Pin Name USB_VBUS 41，42 PI/PO Charging power input. Power supply output for OTG device. USB/charger insertion detection. USB_DM 33 IO USB 2.0 differential data bus (minus) USB_DP 32 IO USB 2.0 differential data bus (plus) USB_SS_RX _P 171 AI USB 3.
Smart LTE Module Series SC650T Hardware Design through software configuration. USIM1_RST USIM1_CLK USIM1_DATA USIM1_VDD USIM2_DET USIM2_RST USIM2_CLK USIM2_DATA 144 143 142 141 256 207 208 209 SC650T_Hardware_Design DO (U)SIM1 card reset signal VOLmax=0.4V VOHmin= 0.8 × USIM1_VDD DO (U)SIM1 card clock signal VOLmax=0.4V VOHmin= 0.8 × USIM1_VDD (U)SIM1 card data signal VILmax= 0.2 × USIM1_VDD VIHmin= 0.7 × USIM1_VDD VOLmax=0.4V VOHmin= 0.
Smart LTE Module Series SC650T Hardware Design 0.8 × USIM2_VDD USIM2_VDD 210 PO (U)SIM2 card power supply 1.8V (U)SIM： Vmax=1.85V Vmin=1.75V 2.95V (U)SIM： Vmax=3.1V Vmin=2.8V Either 1.8V or 2.95V (U)SIM card is supported. UART Interface Pin Name UART2_TXD Pin No. 5 I/O Description DC Characteristics DO UART2 transmit data. Debug port by default. VOLmax=0.45V VOHmin=1.35V VILmax=0.63V VIHmin=1.17V UART2_RXD 6 DI UART2 receive data. Debug port by default.
Smart LTE Module Series SC650T Hardware Design 2.95V SD card： VOLmax=0.37V VOHmin=2.2V SD_CMD 69 IO SD_DATA0 68 IO SD_DATA1 67 IO SD_DATA2 66 IO Command signal of SD card High speed bidirectional digital signal lines of SD card 1.8V SD card： VILmax=0.58V VIHmin=1.27V VOLmax=0.45V VOHmin=1.4V 2.95V SD card： VILmax=0.73V VIHmin=1.84V VOLmax=0.37V VOHmin=2.2V 1.8V SD card： VILmax=0.58V VIHmin=1.27V VOLmax=0.45V VOHmin=1.4V 2.95V SD card： VILmax=0.73V VIHmin=1.84V VOLmax=0.37V VOHmin=2.
Smart LTE Module Series SC650T Hardware Design TP0_I2C_ SDA 206 OD I2C data signal of touch panel (TP0) TP1_RST 136 DO Reset signal of touch panel (TP1) VOLmax=0.45V VOHmin=1.35V 1.8V power domain. Active low. TP1_INT 137 DI Interrupt signal of touch panel (TP1) VILmax=0.63V VIHmin=1.17V 1.8V power domain. TP1_I2C_ SDA 204 OD I2C data signal of touch panel (TP1) 1.8V power domain. TP1_I2C_ SCL 205 OD I2C clock signal of touch panel (TP1) 1.8V power domain. Pin Name Pin No.
Smart LTE Module Series SC650T Hardware Design DSI0_LN1_P DSI0_LN2_N DSI0_LN2_P DSI0_LN3_N 119 122 121 124 AO LCD0 MIPI lane 1 data signal (positive) AO LCD0 MIPI lane 2 data signal (negative) AO LCD0 MIPI lane 2 data signal (positive) AO LCD0 MIPI lane 3 data signal (negative) DSI0_LN3_P 123 AO LCD0 MIPI lane 3 data signal (positive) DSI1_CLK_N 103 AO LCD1 MIPI clock signal (negative) DSI1_CLK_P 102 AO LCD1 MIPI clock signal (positive) DSI1_LN0_N 105 AO LCD1 MIPI lane 0 data
Smart LTE Module Series SC650T Hardware Design Camera Interfaces Pin Name CSI0_CLK_N CSI0_CLK_P CSI0_LN0_N CSI0_LN0_P CSI0_LN1_N CSI0_LN1_P CSI0_LN2_N CSI0_LN2_P Pin No.
Smart LTE Module Series SC650T Hardware Design CSI2_LN0_P CSI2_LN1_N CSI2_LN1_P CSI2_LN2_N CSI2_LN2_P CSI2_LN3_N 79 82 81 84 83 86 AI MIPI lane 0 data signal of front camera (positive) AI MIPI lane 1 data signal of front camera (negative) AI MIPI lane 1 data signal of front camera (positive) AI MIPI lane 2 data signal of front camera (negative) AI MIPI lane 2 data signal of front camera (positive) AI MIPI lane 3 data signal of front camera (negative) CSI2_LN3_P 85 AI MIPI lane 3
Smart LTE Module Series SC650T Hardware Design depth camera VOHmin=1.35V VOLmax=0.45V VOHmin=1.35V DCAM_ PWDN 181 DO Power down signal of depth camera DCAM_I2C_ SDA 197 OD I2C data signal of depth camera 1.8V power domain. DCAM_I2C_ SCL 196 OD I2C clock signal of depth camera 1.8V power domain. I/O Description DC Characteristics Comment VILmax=0.63V VIHmin=1.17V Pull-up to 1.8V internally. Active low. Keypad Interfaces Pin Name Pin No.
Smart LTE Module Series SC650T Hardware Design open. Charging Interface Pin Name BAT_PLUS BAT_MINUS Pin No. 27 28 DC Characteristics I/O Description Comment AI Differential input signal of battery voltage detection (plus) Must be connected. AI Differential input signal of battery voltage detection (minus) Must be connected. Antenna Interfaces Pin Name Pin No.
Smart LTE Module Series SC650T Hardware Design VOLmax=0.45V VOHmin=1.
Smart LTE Module Series SC650T Hardware Design I2S Interface Pin Name Pin No.
Smart LTE Module Series SC650T Hardware Design FLASH_LED1 26 AO Flash/torch current driver output FLASH_LED2 162 AO Flash/torch current driver output Support flash and torch modes. Emergency Download Interface Pin Name USB_BOOT Pin No. 57 I/O Description DI Force the module to enter into emergency download mode DC Characteristics Comment Pulled up to LDO5_1P8 during power-up will force the module to enter into emergency download mode.
Smart LTE Module Series SC650T Hardware Design RESERVED 164,165,16 6,190,191, 192，222 Keep these pins open. Reserved pins 3.4. Power Supply 3.4.1. Power Supply Pins SC650T provides 3 VBAT pins,2 VDD_RF pins and 2 VPH_PWR pins. VBAT pins are dedicated for connection with an external power supply. VDD_RF pins are designed for module’s RF part, and are used to connect bypass capacitors so as to eliminate voltage fluctuation of RF part. VPH_PWR pins are designed for peripherals. 3.4.2.
Smart LTE Module Series SC650T Hardware Design the structure of the power supply. VBAT VDD_RF VBAT + D1 C2 C1 100nF 100uF C5 C3 C4 33pF 10pF + C6 NM 100nF C7 C8 33pF 10pF Module Figure 3: Star Structure of Power Supply 3.4.3. Reference Design for Power Supply The power design for the module is very important, as the performance of module largely depends on the power source. The power supply of SC650T should be able to provide sufficient current up to 3A at least.
Smart LTE Module Series SC650T Hardware Design NOTES 1. 2. 3. It is recommended to switch off the power supply for module in abnormal state, and then switch on the power to restart the module. The module supports battery charging function by default. If the above power supply design is adopted, please make sure the charging function is disabled by software, or connect VBAT to Schottky diode in series to avoid the reverse current to the power supply chip.
Smart LTE Module Series SC650T Hardware Design S1 PWRKEY 1K TVS Close to S1 Figure 6: Turn on the Module Using Keystroke The turning on scenario is illustrated in the following figure. VBA T (Typ e:3.8V) Note2 PWRKEY >1.6s 61.
Smart LTE Module Series SC650T Hardware Design 1. 2. The turn-on timing might be different from the above figure when the module powers on for the first time. Make sure that VBAT is stable before pulling down PWRKEY pin. The recommended time between them is no less than 30ms. PWRKEY cannot be pulled down all the time. 3.5.2. Turn off Module Pull down PWRKEY for at least 1s, and then choose to turn off the module when the prompt window comes up.
Smart LTE Module Series SC650T Hardware Design If RTC is ineffective, it can be synchronized through network after the module is powered on. 2.0V~3.25V input voltage range and 3.0V typical value for VRTC, when VBAT is disconnected. When powered by VBAT, the RTC error is 50ppm. When powered by VRTC, the RTC error is about 200ppm. If the rechargeable battery is used, the ESR of battery should be less than 2K, and it is recommended to use the MS621FE FL11E of SEIKO. 3.7.
Smart LTE Module Series SC650T Hardware Design 3.8. Battery Charge and Management SC650T module supports a fully programmable switch-mode Li-ion battery charge function. It can charge single-cell Li-ion and Li-polymer battery. The battery charger of SC650T module supports trickle charging, pre-charge, constant current charging and constant voltage charging modes, which optimize the charging procedure for Li-ion batteries. Trickle charging: When the battery voltage is below 2.
Smart LTE Module Series SC650T Hardware Design thermistor (47K 1% NTC thermistor with B-constant of 4050K by default; SDNT1608X473F4050FTF of SUNLORD is recommended) and the thermistor is connected to VBAT_THERM pin. If VBAT_THERM pin is not connected, there will be malfunctions such as boot error, battery charging failure, battery level display error, etc. A reference design for battery charging circuit is shown as below.
Smart LTE Module Series SC650T Hardware Design 3.9. USB Interface SC650T provides one integrated Universal Serial Bus (USB) interface which complies with the USB 3.0/2.0 specifications and supports super speed (5Gbps) on USB 3.0, high speed (480Mbps) on USB 2.0 and full speed (12Mbps) modes. The USB interface supports USB OTG function, and is used for AT command communication, data transmission, software debugging and firmware upgrade. The following table shows the pin definition of USB interface.
Smart LTE Module Series SC650T Hardware Design the OTG device is attached: when USB_ID is kept open (high level by default), SC650T is in USB slave mode; if USB_ID is connected to ground, it is in OTG mode and USB_VBUS is used to supply power for peripherals with maximum output of 5V/1A. D2 D1 100nF ESD D3 VUSB USB_DM USB_DP USB_ID GND ESD ESD GND GND C1 1 2 3 4 5 6 Module 7 USB_VUSB USB_DM USB_DP USB_ID 9 GND 8 GND The following is a reference design for USB interface: Figure 11: USB 2.
Smart LTE Module Series SC650T Hardware Design important to route the USB differential traces in inner-layer with ground shielding on not only upper and lower layers but also right and left sides. Keep the ESD protection devices as close as possible to the USB connector. Make sure the trace length difference between USB 2.0 DM/DP differential pair and that between USB 3.0 RX/TX differential pairs both do not exceed 0.7mm. Table 9: USB Trace Length Inside the Module Pin No.
Smart LTE Module Series SC650T Hardware Design UART4_TXD 7 DO UART4 transmit data UART4_RXD 8 DI UART4 receive data UART5_RXD 198 DI UART5 receive data UART5_TXD 199 DO UART5 transmit data UART5_CTS 246 DI UART5 clear to send UART5_RTS 245 DO UART5 request to send UART6_RXD 61 DI UART6 receive data UART6_TXD 60 DO UART6 transmit data UART5 is a 4-wire UART interface with 1.8V power domain. A level translator chip should be used if customers’ application is equipped with a 3.
Smart LTE Module Series SC650T Hardware Design 1.8V OE VCCA UART5_TXD TXD_1.8V RTS_1.8V UART5_RTS 3.3V VCCB TXD_3.3V RTS_3.3V UART5_RXD RXD_1.8V RXD_3.3V UART5_CTS CTS_1.8V CTS_3.3V GND RXD CTS DIN 3 DOUT3 DIN 4 DOUT4 DIN 5 DOUT5 FORCEON 3.
Smart LTE Module Series SC650T Hardware Design USIM1_DATA 142 IO (U)SIM1 card data signal Pull up to USIM1_VDD with a 10K resistor. USIM1_VDD 141 PO (U)SIM1 card power supply Either 1.8V or 2.95V (U)SIM card is supported. Active low. Need external pull-up to 1.8V. If unused, keep this pin open. Disabled by default, and can be enabled through software configuration.
Smart LTE Module Series SC650T Hardware Design USIM _VDD R1 10K Module USIM_ VDD USIM_ RST USIM_ CLK USIM_ DET C1 (U)SIM Card Connector 100nF VCC RST CLK R2 22R R3 GND VPP IO 22R USIM_ DATA R4 22R C2 C3 C4 22pF 22pF 22pF D1 ESD Figure 16: Reference Circuit for (U)SIM Interface with a 6-pin (U)SIM Card Connector In order to ensure good performance and avoid damage of (U)SIM cards, please follow the criteria below in (U)SIM circuit design: Keep placement of (U)SIM card connector
Smart LTE Module Series SC650T Hardware Design Table 12: Pin Definition of SD Card Interface Pin Name Pin No. I/O Description Comment SD_LDO11 63 PO Power supply for SD card Vnorm=2.95V IOmax=800mA SD_LDO12 179 PO SD card pull-up power supply Support 1.8V or 2.95V power supply. The maximum drive current is 50mA.
Smart LTE Module Series SC650T Hardware Design CMD, CLK, DATA0, DATA1, DATA2 and DATA3 are all high speed signal lines. In PCB design, please control the characteristic impedance of them as 50Ω, and do not cross them with other traces. It is recommended to route the trace on the inner layer of PCB, and keep the same trace length for CLK, CMD, DATA0, DATA1, DATA2 and DATA3. CLK additionally needs ground shielding. Layout guidelines: Control impedance as 50Ω±10%, and ground shielding is required.
Smart LTE Module Series SC650T Hardware Design UART2_TXD 5 GPIO_4 B-PD:nppukp UART2_RXD 6 GPIO_5 B-PD:nppukp TP1_I2C_SDA 204 GPIO_6 B-PD:nppukp TP1_I2C_SCL 205 GPIO_7 B-PD:nppukp TP1_RST 136 GPIO_8 B-PD:nppukp TP1_INT 137 GPIO_9 B-PD:nppukp TP0_I2C_SDA 206 GPIO_10 B-PD:nppukp TP0_I2C_SCL 140 GPIO_11 B-PD:nppukp UART4_TXD 7 GPIO_12 B-PD:nppukp Wakeup UART4_RXD 8 GPIO_13 B-PD:nppukp Wakeup SENSOR_I2C_SDA 132 GPIO_14 B-PD:nppukp SENSOR_I2C_SCL 131 GPIO_15 B-PD:
Smart LTE Module Series SC650T Hardware Design CAM_I2C_SDA 76 GPIO_29 B-PD:nppukp CAM_I2C_SCL 75 GPIO_30 B-PD:nppukp DCAM_I2C_SDA 197 GPIO_31 B-PD:nppukp DCAM_I2C_SCL 196 GPIO_32 B-PD:nppukp GPIO_33 238 GPIO_33 B-PD:nppukp GPIO_36 237 GPIO_36 B-PD:nppukp MCAM_PWDN 73 GPIO_39 B-PD:nppukp MCAM_RST 74 GPIO_40 B-PD:nppukp GPIO_42 252 GPIO_42 B-PD:nppukp Wakeup GPIO_43 253 GPIO_43 B-PD:nppukp Wakeup GPIO_44 254 GPIO_44 B-PD:nppukp Wakeup GPIO_45 255 GPIO_45 B-PD
Smart LTE Module Series SC650T Hardware Design I2S_1_SCK 212 GPIO_91 B-PD:nppukp Wakeup I2S_1_WS 156 GPIO_92 B-PD:nppukp I2S_1_D0 154 GPIO_93 B-PD:nppukp I2S_1_D2 213 GPIO_94 B-PD:nppukp I2S_1_D3 214 GPIO_95 B-PD:nppukp WSA_EN 230 GPIO_96 B-PD:nppukp GPIO_97 229 GPIO_97 B-PD:nppukp GPIO_98 177 GPIO_98 B-PD:nppukp GPIO_99 178 GPIO_99 B-PD:nppukp GPIO_105 242 GPIO_105 B-PD:nppukp GPIO_107 241 GPIO_107 B-PD:nppukp CAM4_MCLK 236 GPIO_128 B-PD:nppukp SCAM_RST 72
Smart LTE Module Series SC650T Hardware Design 4. More details about GPIO configuration, please refer to document [2]. 3.14. I2C Interfaces SC650T provides five I2C interfaces. As an open drain output, each I2C interface should be pulled up to 1.8V voltage. The SENSOR_I2C interface supports only sensors of the aDSP architecture. CAM/DCAM_I2C bus is controlled by Linux Kernel code and supports connection to video output related devices.
Smart LTE Module Series SC650T Hardware Design Table 16: Pin Definition of I2S Interface Pin Name Pin No I/O Description Comment I2S_MCLK 234 DO Master clock signal of I2S interface I2S_MCLK I2S_1_SCK 212 DO Clock signal of I2S interface I2S_1_SCK I2S_1_WS 156 DO Channel selection signal of I2S interface I2S_1_WS I2S_1_D0 154 IO Data0 signal of I2S interface I2S_1_D0 I2S_1_D1 155 IO Data1 signal of I2S interface I2S_1_D1 I2S_1_D2 213 IO Data2 signal of I2S interface I2S_1_
Smart LTE Module Series SC650T Hardware Design multiplexed into I2S interface. FP_SPI_CLK 250 DO Clock signal of SPI interface FP_SPI_MOSI 249 DO Master out slave in of SPI interface FP_SPI_MISO 251 DI Master in salve out of SPI interface 3.17. ADC Interfaces SC650T provides two analog-to-digital converter (ADC) interfaces, and the pin definition is shown below. Table 18: Pin Definition of ADC Interfaces Pin Name Pin No.
Smart LTE Module Series SC650T Hardware Design VIB_DRV VIB_DRV GND Module 33pF C1 Motor PESD5V0H1BSF Figure 18: Reference Circuit for Vibrator Connection 3.19. LCM Interfaces SC650T module provides two LCM interfaces, and supports dual LCDs with WUXGA (1900×1200) display. The interfaces support high speed differential data transmission, with up to eight lanes. Table 20: Pin Definition of LCM Interfaces Pin Name Pin No. I/O Description LDO6_1P8 10 PO 1.
Smart LTE Module Series SC650T Hardware Design DSI0_CLK_N 116 AO LCD0 MIPI clock signal (negative) DSI0_CLK_P 115 AO LCD0 MIPI clock signal (positive) DSI0_LN0_N 118 AO LCD0 MIPI lane 0 data signal (negative) DSI0_LN0_P 117 AO LCD0 MIPI lane 0 data signal (positive) DSI0_LN1_N 120 AO LCD0 MIPI lane 1 data signal (negative) DSI0_LN1_P 119 AO LCD0 MIPI lane 1 data signal (positive) DSI0_LN2_N 122 AO LCD0 MIPI lane 2 data signal (negative) DSI0_LN2_P 121 AO LCD0 MIPI lane 2 data
Smart LTE Module Series SC650T Hardware Design LDO 6_1P8 1 2 3 4 5 6 LCD_BIAS_P LCD_BIAS_N LCD0_TE LCD0_ RST PMU_MPP2 10V 5 6 2 DSI0_LN3_N 1 5 2 DSI0_LN2_N 1 5 2 DSI0_LN1_N 1 5 2 1 5 2 DSI0_ CLK_N FL4 4 3 6 DSI0_ CLK_P FL3 4 3 6 DSI0_LN0_P DSI0_LN0_N FL2 4 3 6 DSI0_LN1_P 10V C3 1uF 4 3 6 DSI0_LN2_P C2 1uF FL1 3 1 DSI0_LN3_P C1 1uF FL5 4 EMI filter LCM _LED+ LCM _LED- Module LCD_BIAS_P NC LCD_BIAS_N NC LPTE RESET 7 LCD_ID 8 NC (SDA-TP) 9 NC (SCL-TP) 10 NC
Smart LTE Module Series SC650T Hardware Design LDO6_1P8 1 2 3 4 5 6 LCD_BIAS_P LCD_BIAS_N LCD1_TE LCD1_RST C1 10V 1uF C2 10V FL1 5 6 4 2 DSI1_LN3_N 5 6 1 DSI1_LN2_P DSI1_LN2_N 1 5 3 5 6 1 2 FL4 5 FL5 6 3 2 DSI1_CLK_N 3 4 1 DSI1_CLK_P FL3 4 2 DSI1_LN0_P DSI1_LN0_N FL2 6 DSI1_LN1_P DSI1_LN1_N 3 18 19 20 21 22 23 24 25 26 27 28 29 30 4 2 4 NC LPTE RESET LCD_ID NC (SDA-TP) NC (SCL-TP) NC (RST-TP) NC (EINT-TP) GND VIO18 VCC28 NC (VTP-TP) GND MIPI_TDP3 MIPI_TDN3 GND
Smart LTE Module Series SC650T Hardware Design 3.20. Touch Panel Interfaces SC650T provides two I2C interfaces for connection with Touch Panel (TP), and also provides the corresponding power supply and interrupt pins. The pin definition of touch panel interfaces is illustrated below. Table 21: Pin Definition of Touch Panel Interfaces Pin Name Pin No I/O Description Comment LDO10_2P8 11 PO 2.8V output power supply for TP VDD power Vnorm=2.8V IOmax=150mA Pull-up power supply of I2C Vnorm=1.
Smart LTE Module Series SC650T Hardware Design LDO 6_1P8 R1 LDO10_2P8 R2 2.2K 2.2K 1 2 3 4 5 6 TP_I2C_SDA TP_I2C_SCL TP_RST TP_INT D1 D2 D3 D4 C1 C2 SDA 1.8V SCL 1.8V RESET 1.8V INT 1.8V GND VDD 2.8V D5 4.7uF 100nF Module TP Figure 22: Reference Circuit Design for Touch Panel Interfaces NOTE TP is powered by LDO10_2P8 by default and LDO10_2P8 can output 150mA current. It is recommended to use an external LDO power supply if dual-TP or other applications need to be supported. 3.21.
Smart LTE Module Series SC650T Hardware Design for digital core circuit of front camera CSI0_CLK_N 89 AI MIPI clock signal of rear camera (negative) CSI0_CLK_P 88 AI MIPI clock signal of rear camera (positive) CSI0_LN0_N 91 AI MIPI lane 0 data signal of rear camera (negative) CSI0_LN0_P 90 AI MIPI lane 0 data signal of rear camera (positive) CSI0_LN1_N 93 AI MIPI lane 1 data signal of rear camera (negative) CSI0_LN1_P 92 AI MIPI lane 1 data signal of rear camera (positive) CSI0_LN2_
Smart LTE Module Series SC650T Hardware Design MCAM_MCLK 99 DO Master clock signal of rear camera SCAM_MCLK 100 DO Master clock signal of front camera MCAM_RST 74 DO Reset signal of rear camera MCAM_PWDN 73 DO Power down signal of rear camera SCAM_RST 72 DO Reset signal of front camera SCAM_PWDN 71 DO Power down signal of front camera CAM_I2C_SCL 75 OD I2C clock signal of camera CAM_I2C_SDA 76 OD I2C data signal of camera DCAM_MCLK 194 DO Clock signal of depth camera CAM
Smart LTE Module Series SC650T Hardware Design The following is a reference circuit design for two-camera applications. 4.7uF 4.7uF AF_VDD LDO22_2P8 AVDD LDO2_1P1 DVDD DOVDD LDO 6_1P8 2.2K Rear camera connector MCAM_ RST MCAM_PWDN MCAM_MCLK CAM_I2C_ SDA CAM_I2C_ SCL CSI0_LN3_P CSI0_LN3_N CSI0_LN2_P CSI0_LN2_N CSI0_LN1_P CSI0_LN1_N CSI0_LN0_P CSI0_LN0_N CSI0_ CLK_P CSI0_ CLK_N 1uF 1uF LDO17_2P85 2.2K EMI EMI EMI EMI EMI 4.
Smart LTE Module Series SC650T Hardware Design CSI0 is used for rear camera, and CSI2 is used for front camera. 3.21.1. 3.21.1. Design Considerations Special attention should be paid to the pin definition of LCM/camera connectors. Assure the SC650T and the connectors are correctly connected. MIPI are high speed signal lines, supporting maximum data rate up to 2.1Gbps. The differential impedance should be controlled as 100Ω.
Smart LTE Module Series SC650T Hardware Design 103 DSI1_CLK_N 11.69 0.02 102 DSI1_CLK_P 11.71 105 DSI1_LN0_N 11.46 104 DSI1_LN0_P 11.56 107 DSI1_LN1_N 15.26 0.09 0.01 106 DSI1_LN1_P 15.27 109 DSI1_LN2_N 15.12 108 DSI1_LN2_P 14.47 111 DSI1_LN3_N 16.15 110 DSI1_LN3_P 16.14 89 CSI0_CLK_N 17.80 88 CSI0_CLK_P 17.86 91 CSI0_LN0_N 17.73 90 CSI0_LN0_P 17.73 93 CSI0_LN1_N 12.98 -0.65 -0.01 0.06 -0.01 -0.03 92 CSI0_LN1_P 12.95 95 CSI0_LN2_N 11.
Smart LTE Module Series SC650T Hardware Design 84 CSI2_LN2_N 22.96 -0.01 83 CSI2_LN2_P 22.95 86 CSI2_LN3_N 22.77 85 CSI2_LN3_P 22.41 -0.36 3.21.2. Flashlight Interfaces SC650T module supports 2 flash LED drivers, with maximal output current up to 1.5A in flash mode and 300mA in torch mode. The default output current is 1A in flash mode and 300mA in torch mode. Table 24: Pin Definition of Flashlight Interfaces Pin Name Pin No.
Smart LTE Module Series SC650T Hardware Design 3.22. Sensor Interfaces SC650T module supports communication with sensors via I2C interface, and it supports various sensors such as acceleration sensor, gyroscopic sensor, compass, optical sensor, temperature sensor. Table 25: Pin Definition of Sensor Interfaces Pin Name Pin No.
Smart LTE Module Series SC650T Hardware Design Dias voltage for DMIC2 MIC_BIAS3 167 AO Microphone bias voltage LINE_OUT_3 228 AO Audio output LINE_OUT_REF 227 AI Audio output reference ground LINE_OUT_4 226 AO Audio output AMIC1_P 218 AI Analog microphone positive input for channel 1 AMIC1_M 217 AI Analog microphone negative input for channel 1 AMIC2_P 216 AI Analog microphone positive input for headset AMIC2_M 215 AI Analog microphone input for headset EAR_P 53 AO Earpi
Smart LTE Module Series SC650T Hardware Design 3.23.1. Reference Circuit Design for Microphone Interfaces MIC_BIASn R4 R1 AMICx_P 1.1K 0R R2 AMICx_M 0R Module C1 R3 ECM-MIC 0.1uF 1.
Smart LTE Module Series SC650T Hardware Design MIC_ BIAS R2 NC GND VDD L/R NC R1 NC Digital MIC DMIC_CLK DMIC_CLK DMIC_DATA DMIC_DATA C2 100nF C3 10uF Module Figure 27:Reference Circuit Design for Digital Microphone 3.23.2. Reference Circuit Design for Earpiece Interface C4 C2 NM_8.2pF NM_33pF R1 EAR_P 0R R2 EAR_N C1 C3 NM_8.
Smart LTE Module Series SC650T Hardware Design 3.23.3. Reference Circuit Design for Headphone Interface R1 33pF AMIC2_M C2 0R C2 R6 C2 33pF 2.2K %1 MIC_BIAS2 100pF R4 F1 AMIC2_P R2 R5 NC 0R HPH_R HPH_REF C3 Module 1 5 4 6 3 2 F2 HPH_L HS_DET NC R7 C4 680pF 680pF F3 F4 D1 D2 D3 D4 D5 0R ESD Figure 29: Reference Circuit Design for Headphone Interface 3.23.4.
Smart LTE Module Series SC650T Hardware Design that the resonant frequency point of a capacitor largely depends on the material and production technique. Therefore, customers would have to discuss with their capacitor vendors to choose the most suitable capacitor for filtering out high-frequency noises. The severity degree of the RF interference in the voice channel during GSM transmitting largely depends on the application design.
Smart LTE Module Series SC650T Hardware Design Table 27: Pin Definition of LED Driver Interfaces Pin Name Pin No. I/O Description Comment LED_RED 23 PO Red LED light The output current does not exceed 12mA LED_GRN 24 PO Green LED light The output current does not exceed 12mA LED_BLU 25 PO Blue LED light The output current does not exceed 12mA A reference circuit design for LED interfaces is shown below.
Smart LTE Module Series SC650T Hardware Design 4 Wi-Fi and BT SC650T module provides a shared antenna interface ANT_WIFI/BT for Wi-Fi and Bluetooth (BT) functions. The interface impedance is 50Ω. External antennas such as PCB antenna, sucker antenna and ceramic antenna can be connected to the module via the interface, so as to achieve Wi-Fi and BT functions. 4.1. Wi-Fi Overview SC650T module supports 2.4GHz and 5GHz dual-band WLAN wireless communication based on IEEE 802.11a/b/g/n/ac standard protocols.
Smart LTE Module Series SC650T Hardware Design 802.11g 54Mbps 14dBm±2.5dB 802.11n HT20 MCS0 15dBm±2.5dB 802.11n HT20 MCS7 13dBm±2.5dB 802.11n HT40 MCS0 15dBm±2.5dB 802.11n HT40 MCS7 13dBm±2.5dB 802.11a 6Mbps 17dBm±2.5dB 802.11a 54Mbps 16dBm±2.5dB 802.11n HT20 MCS0 17dBm±2.5dB 802.11n HT20 MCS7 16dBm±2.5dB 802.11n HT40 MCS0 17dBm±2.5dB 802.11n HT40 MCS7 16dBm±2.5dB 802.11ac VHT20 MCS0 16dBm±2.5dB 802.11ac VHT20 MCS8 15dBm±2.5dB 802.11ac VHT40 MCS0 15dBm±2.5dB 802.
Smart LTE Module Series SC650T Hardware Design 5GHz 802.11n HT20 MCS7 -72dBm 802.11n HT40 MCS0 -89dBm 802.11n HT40 MCS7 -70dBm 802.11a 6Mbps -92dBm 802.11a 54Mbps -74dBm 802.11n HT20 MCS0 -91dBm 802.11n HT20 MCS7 -73dBm 802.11n HT40 MCS0 -88dBm 802.11n HT40 MCS7 -70dBm 802.11ac VHT20 MCS8 -68dBm 802.11ac VHT40 MCS9 -63dBm 802.11ac VHT80 MCS9 -59dBm Reference specifications are listed below: IEEE 802.11n WLAN MAC and PHY, October 2009 + IEEE 802.
Smart LTE Module Series SC650T Hardware Design Table 30: BT Data Rate and Versions Version Data rate Maximum Application 1.2 1Mbit/s > 80Kbit/s 2.0+EDR 3Mbit/s > 80Kbit/s 3.0+HS 24Mbit/s Reference to 3.0+HS 4.0 24Mbit/s Reference to 4.0 LE Throughput Comment Reference specifications are listed below: Bluetooth Radio Frequency TSS and TP Specification 1.2/2.0/2.0 + EDR/2.1/2.1+ EDR/3.0/3.0 + HS, August 6, 2009 Bluetooth Low Energy RF PHY Test Specification, RF-PHY.TS/4.0.
Smart LTE Module Series SC650T Hardware Design 5 GNSS SC650T module integrates a Qualcomm IZat™ GNSS engine (Gen 8C) which supports multiple positioning and navigation systems including GPS, GLONASS and BeiDou. With an embedded LNA, the module provides greatly improved positioning accuracy. 5.1. GNSS Performance The following table lists the GNSS performance of SC650T module in conduction mode. Table 32: GNSS Performance Parameter Sensitivity (GNSS) TTFF (GNSS) Static Drift (GNSS) Description Typ.
Smart LTE Module Series SC650T Hardware Design 5.2. GNSS RF Design Guidelines Bad design of antenna and layout may cause reduced GNSS receiving sensitivity, longer GNSS positioning time, or reduced positioning accuracy. In order to avoid these, please follow the design rules listed below: Maximize the distance between the GNSS RF part and the GPRS RF part (including trace routing and antenna layout) to avoid mutual interference.
Smart LTE Module Series SC650T Hardware Design 6 Antenna Interfaces SC650T provides four antenna interfaces for main antenna, Rx-diversity/MIMO antenna, GNSS antenna, and Wi-Fi/BT antenna, respectively. The antenna ports have an impedance of 50Ω. 6.1. Main/Rx-diversity Antenna Interfaces The pin definition of main/Rx-diversity antenna interfaces is shown below. Table 33: Pin Definition of Main/Rx-diversity Antenna Interfaces Pin Name Pin No.
Smart LTE Module Series SC650T Hardware Design LTE-FDD B25 1930~1995 1850~1915 MHz LTE-FDD B26 859~894 814~849 MHz LTE-FDD B66 2110~2200 1710~1780 MHz Table 35: SC650T-EM Module Operating Frequencies 3GPP Band Receive Transmit Unit LTE-FDD B1 2110~2170 1920~1980 MHz LTE-FDD B3 1805~1880 1710~1785 MHz LTE-FDD B7 2620~2690 2500~2570 MHz LTE-FDD B20 791~821 832~862 MHz LTE-FDD B28 758~803 703~748 MHz 6.1.1. 6.1.1. 6.1.1.
Smart LTE Module Series SC650T Hardware Design Figure 33: Reference Circuit Design for Main and Rx-diversity Antenna Interfaces 6.1.2. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S).
Smart LTE Module Series SC650T Hardware Design Figure 36: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 37: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω.
Smart LTE Module Series SC650T Hardware Design 6.2. Wi-Fi/BT Antenna Interface Table 36: Pin Definition of Wi-Fi/BT Antenna Interface Pin Name Pin No. I/O Description Comment ANT_WIFI/BT 129 IO Wi-Fi/BT antenna interface 50Ω impedance Table 37: Wi-Fi/BT Frequency Type Frequency Unit 802.11a/b/g/n/ac 2402~2482 5180~5825 MHz BT4.2 LE 2402~2480 MHz A reference circuit design for Wi-Fi/BT antenna interface is shown as below.
Smart LTE Module Series SC650T Hardware Design Table 38: Pin Definition of GNSS Antenna Pin Name Pin No. I/O Description Comment ANT_GNSS 134 AI GNSS antenna Interface 50Ω impedance GNSS_LNA_EN 202 DO LNA enable control For test purpose only. If unused, keep it open. Table 39: GNSS Frequency Type Frequency Unit GPS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz BeiDou 1561.098±2.046 MHz 6.3.1.
Smart LTE Module Series SC650T Hardware Design still requires stable and clean power supplies. It is recommended to use high performance LDO as the power supply. A reference design of GNSS active antenna is shown below. 3V3 Active Antenna R1 C4 0R NM Module C2 1uF 100pF C3 R2 ANT_GNSS C1 10R L1 56nH C5 100pF NM Figure 40: Reference Circuit Design for GNSS Active Antenna 6.4. Antenna Installation 6.4.1.
Smart LTE Module Series SC650T Hardware Design Frequency range: 1559MHz~1609MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive Antenna Gain: > 0dBi Active Antenna Noise Figure: < 1.5dB (Typ.) Active Antenna Gain: > -2dBi Active Antenna Embedded LNA Gain: < 17dB (Typ.) Active Antenna Total Gain: < 17dBi (Typ.) GNSS 1) NOTE 1) It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance.
Smart LTE Module Series SC650T Hardware Design Figure 42: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 43: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
Smart LTE Module Series SC650T Hardware Design 7 Electrical, Reliability and Radio Characteristics 7.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 41: Absolute Maximum Ratings Parameter Min Max Unit VBAT -0.5 6 V USB_VBUS -0.5 20 V 0 3 A 2.3 V Current on VBAT Voltage on Digital Pins -0.3 7.2.
Smart LTE Module Series SC650T Hardware Design Parameter Description Conditions Min Typ. Max Unit battery. 7.3. Operation and Storage Temperatures The operation and storage temperatures are listed in the following table. Table 43: Operation and Storage Temperatures Parameter Min Typ. Max Unit Operating temperature range 1) -35 +25 +65 °C Extended temperature range 2) -40 +75 °C Storage temperature range -40 +90 °C NOTES 1. 2.
Smart LTE Module Series SC650T Hardware Design Table 44: SC650T-NA Current Consumption Parameter Description Conditions OFF state Power down 73 uA Sleep (USB disconnected) @DRX=6 5.3 mA Sleep (USB disconnected) @DRX=8 3.5 mA Sleep (USB disconnected) @DRX=9 3.
Smart LTE Module Series SC650T Hardware Design LTE-FDD B3 @max power 721 mA LTE-FDD B7 @max power 702 mA LTE-FDD B20 @max power 571 mA LTE-TDD B28 @max power 607 mA 7.5. 7.5. RF Output Power The following table shows the RF output power of SC650T module.
Smart LTE Module Series SC650T Hardware Design LTE-FDD B7 23dBm±2dB <-39dBm LTE-FDD B20 23dBm±2dB <-39dBm LTE-FDD B28 23dBm±2dB <-39dBm 7.6. RF Receiving Sensitivity The following table shows the conducted RF receiving sensitivity of SC650T module. Table 48: SC650T-NA RF Receiving Sensitivity x` Receive Sensitivity (Typ.) Frequency Primary Diversity SIMO 3GPP (SIMO) LTE-FDD B2 (10M) -99.5dBm -100.4dBm -102.9dBm -94.3dBm LTE-FDD B4 (10M) -98.7dBm -99.6dBm -102.3dBm -96.
Smart LTE Module Series SC650T Hardware Design LTE-FDD B1 (10M) -99.1dBm -99dBm -102.3dBm -96.3dBm LTE-FDD B3 (10M) -98.9dBm -99.5dBm -102.1dBm -93.3dBm LTE-FDD B7 (10M) -98.5dBm -98.8dBm -101.9dBm -94.3dBm LTE-FDD B20 (10M) -99.7dBm -99.6dBm -102.4dBm -93.3dBm LTE-TDD B28 (10M) -99.8dBm -99.4dBm -102.2dBm -94.8dBm 7.7. 7.7. Electrostatic Discharge The module is not protected against electrostatic discharge (ESD) in general.
Smart LTE Module Series SC650T Hardware Design 8 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in millimeter (mm), and the tolerances for dimensions without tolerance values are ±0.05mm. 8.1.
Smart LTE Module Series SC650T Hardware Design Figure 45: Module Bottom Dimensions (Top View) SC650T_Hardware_Design 103 / 131
Smart LTE Module Series SC650T Hardware Design 8.2. Recommended Footprint Figure 46: Recommended Footprint (Top View) NOTES 1. 2. For easy maintenance of the module, keep about 3mm between the module and other components on host PCB. All RESERVED pins should be kept open and MUST NOT be connected to ground.
Smart LTE Module Series SC650T Hardware Design 8.3. Top and Bottom View of the Module Figure 47: Top View of the Module Figure 48: Bottom View of the Module NOTE These are renderings of SC650T module. For authentic dimension and appearance, please refer to the module that you receive from Quectel.
Smart LTE Module Series SC650T Hardware Design 9 Storage, Manufacturing and Packaging 9.1. Storage SC650T is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are shown as below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be: Mounted within 168 hours at the factory environment of ≤30ºC/60%RH. Stored at <10%RH. 3.
Smart LTE Module Series SC650T Hardware Design 9.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.18mm~0.20mm.
Smart LTE Module Series SC650T Hardware Design Reflow Zone Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 240°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 9.3. Packaging SC650T is packaged in tape and reel carriers. Each reel is 330mm in diameter and contains 200 modules. The following figures show the package details, measured in mm.
Smart LTE Module Series SC650T Hardware Design Figure 51: Reel Dimensions Table 52: Reel Packaging Model Name SC650T MOQ for MP 200 SC650T_Hardware_Design Minimum Package: 200pcs Minimum Package×4=800pcs Size: 398mm × 383mm × 83mm Size: 420mm × 350mm × 405mm N.W: 1.92kg G.W: 3.67kg N.W: 8.18kg G.W: 15.
Smart LTE Module Series SC650T Hardware Design 10 Appendix A References Table 53: Related Documents SN Document Name Remark [1] Quectel_Smart_EVB-G2_User_Guide EVB User Guide for SC650T [2] Quectel_SC650T_GPIO_Configuration GPIO Configuration of SC650T [3] Quectel_RF_Layout_Application_Note RF Layout Application Note [4] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide [5] Quectel_SC650T_Reference_Design Reference Design for SC650T Table 54: Terms and Abbreviations
Smart LTE Module Series SC650T Hardware Design GPS Global Positioning System GPU Graphics Processing Unit HR Half Rate HSDPA High Speed Down Link Packet Access HSPA High Speed Packet Access I/O Input/Output IQ Inphase and Quadrature LCD Liquid Crystal Display LCM LCD Module LED Light Emitting Diode LNA Low Noise Amplifier LRA Linear Resonant Actuator MIPI Mobile Industry Processor Interface PCB Printed Circuit Board PDU Protocol Data Unit PMI Power Management Interface PMU
Smart LTE Module Series SC650T Hardware Design SMS Short Message Service TE Terminal Equipment TX Transmitting Direction UART Universal Asynchronous Receiver & Transmitter UMTS Universal Mobile Telecommunications System (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VI Voltage Input VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VO Voltage Output VOHmin Mini
