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BG95 Hardware Design

LPWA Module Series

Rev. BG95_Hardware_Design_V1.0

Date: 2019-05-15

Status: Preliminary

www.quectel.com

Summary of content (84 pages)

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BG95 Hardware Design LPWA Module Series Rev. BG95_Hardware_Design_V1.0 Date: 2019-05-15 Status: Preliminary www.quectel.
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LPWA Module Series BG95 Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
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LPWA Module Series BG95 Hardware Design About the Document History Revision Date Author Description 1.
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LPWA Module Series BG95 Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index ............................................................................................................................................
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LPWA Module Series BG95 Hardware Design 3.17. GPIO Interfaces ...................................................................................................................... 52 4 GNSS Receiver ................................................................................................................................ 54 4.1. General Description ................................................................................................................ 54 4.2. GNSS Performance ...............
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LPWA Module Series BG95 Hardware Design Table Index TABLE 1: VERSION SELECTION FOR BG95 SERIES MODULE ................................................................... 13 TABLE 2: FREQUENCY BANDS AND GNSS TYPES OF BG95 SERIES MODULE ...................................... 13 TABLE 3: KEY FEATURES OF BG95 SERIES MODULES ............................................................................. 16 TABLE 4: DEFINITION OF I/O PARAMETERS ......................................................................
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LPWA Module Series BG95 Hardware Design TABLE 42: DESCRIPTION OF DIFFERENT CODING SCHEMES .................................................................. 80 TABLE 43: GPRS MULTI-SLOT CLASSES ...................................................................................................... 81 TABLE 44: EDGE MODULATION AND CODING SCHEMES ..........................................................................
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LPWA Module Series BG95 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 18 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 21 FIGURE 3: SLEEP MODE APPLICATION VIA UART ......................................................................................
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LPWA Module Series BG95 Hardware Design 1 Introduction This document defines BG95 module and describes its air interface and hardware interfaces which are connected with customers’ applications. This document can help customers quickly understand the interface specifications, electrical and mechanical details, as well as other related information of BG95. To facilitate its application in different fields, reference design is also provided for customers’ reference.
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LPWA Module Series BG95 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating BG95. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
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LPWA Module Series BG95 Hardware Design 1.2. FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met: 1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.
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LPWA Module Series BG95 Hardware Design ❒NB LTE Band71:≤11.687 dBi 5. This module must not transmit simultaneously with any other antenna or transmitter 6. The host end product must include a user manual that clearly defines operating requirements and conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.
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LPWA Module Series BG95 Hardware Design The final host / module combination may also need to be evaluated against the FCC Part 15B criteria for unintentional radiators in order to be properly authorized for operation as a Part 15 digital device. The user’s manual or instruction manual for an intentional or unintentional radiator shall caution the user that changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
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LPWA Module Series BG95 Hardware Design 2 Product Concept 2.1. General Description BG95 is a series of embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless communication module. It provides data connectivity on LTE-FDD/GPRS/EGPRS networks, and supports half-duplex operation in LTE networks. It also provides GNSS 1) and voice 2) functionality to meet customers’ specific application demands.
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LPWA Module Series BG95 Hardware Design BG95-M2* Cat M1: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B14/B18/B19/B20/B25/B26*/ B27/B28/B66/B85 Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26*/B28/B66/ B71/B85 Power Class 5 (20dBm) GPS, GLONASS, BeiDou, Galileo Power Class 5 (20dBm) GPS, GLONASS, BeiDou, Galileo Power Class 5 (20dBm) GPS, GLONASS, BeiDou, Galileo Power Class 5 (20dBm) GPS, GLONASS, BeiDou, Galileo Power Class 3 (23dBm) GPS, GLONASS, BeiDou, Galileo Cat M1: LTE-FDD: B1/B
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LPWA Module Series BG95 Hardware Design B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26/B28/B66/ B71/B85 Cat M1: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B14/B18/B19/B20/B25/B26/B27/ B28/B66/B85 BG95-MF 4) Cat NB2: LTE-FDD: B1/B2/B3/B4/B5/B8/B12/B13/ B18/B19/B20/B25/B26/ B28/B66/B71/B85 Power Class 5 (20dBm) GPS, GLONASS, BeiDou, Galileo Wi-Fi (For Positioning Only): 2.4GHz/5GHz NOTES 1. 2. 3. 4. 5. 1) GNSS function is optional.
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LPWA Module Series BG95 Hardware Design Table 3: Key Features of BG95 Series Modules Features Power Supply Details BG95-M1/-M2/-N1:  Supply voltage: 2.4V~4.8V  Typical supply voltage: 3.3V BG95-M3:  Supply voltage: 3.3V~4.3V  Typical supply voltage: 3.
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LPWA Module Series BG95 Hardware Design SMS storage: ME by default (U)SIM Interface Support 1.8V USIM/SIM card Audio Feature* Support one digital audio interface: PCM interface USB Interface Compliant with USB 2.0 specification (slave only) Support operations at low-speed and full-speed Used for AT command communication, data transmission, GNSS NMEA output, software debugging and firmware upgrade Support USB serial drivers for Windows 7/8/8.1/10, Linux 2.6/3.x (3.4 or later)/4.1~4.15, Android 4.x/5.
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LPWA Module Series BG95 Hardware Design are also no effects on radio spectrum and no harm to radio network. Only one or more parameters like Pout might reduce in their value and exceed the specified tolerances. When the temperature returns to the normal operating temperature levels, the module will meet 3GPP specifications again. 2.3. Functional Diagram The following figure shows a block diagram of BG95 and illustrates the major functional parts.
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LPWA Module Series BG95 Hardware Design NOTES 1. eSIM function is optional. If eSIM is selected, then the external (U)SIM cannot be used simultaneously. 2. RESET_N will be supported in the next hardware design version. 3. ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version. 4. “*” means under development. 2.4.
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LPWA Module Series BG95 Hardware Design 3 Application Interfaces BG95 is equipped with 102 LGA pads that can be connected to customers’ cellular application platforms. The following sub-chapters will provide detailed description of interfaces listed below:          Power supply (U)SIM interface USB interface UART interfaces PCM* and I2C* interfaces Status indication USB_BOOT interface ADC interfaces GPIO interfaces NOTE “*” means under development.
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LPWA Module Series BG95 Hardware Design 3.1. Pin Assignment GND VBAT_RF VBAT_RF RESERVED GND 53 52 51 50 RESERVED 56 GND RESERVED 57 54 GND 58 55 ANT_MAIN GND 59 GND 61 60 GND 62 The following figure shows the pin assignment of BG95.
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LPWA Module Series BG95 Hardware Design NOTES 1. 2. 3. 4. 5. 6. 1) ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version. 2) PWRKEY output voltage is 1.5V because of the diode drop in the Qualcomm chipset. PWRKEY should never be pulled down to GND permanently. 3) RESET_N will be supported in the next hardware design version.
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LPWA Module Series BG95 Hardware Design Table 5: Pin Description Power Supply Pin Name VBAT_BB VBAT_RF Pin No. 32, 33 52, 53 VDD_EXT 29 GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67~74, 79~82, 89~91, 100~102 I/O PI PI PO Description Power supply for the module’s baseband part Power supply for the module’s RF part 1.8V output power supply for external circuit DC Characteristics Comment BG95-M1/-M2/-N1: Vmax=4.8V Vmin=2.4V Vnorm=3.3V BG95-M3: Vmax=4.3V Vmin=3.3V Vnorm=3.
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LPWA Module Series BG95 Hardware Design never be pulled down to GND permanently. Reset Pin Name Pin No. I/O Description DC Characteristics Comment DI Reset the module VILmax=0.45V RESET_N will be supported in the next hardware design version. I/O Description DC Characteristics Comment DO Indicate the module’s operation status VOHmin=1.35V VOLmax=0.45V 1.8V power domain. If unused, keep this pin open. 21 DO Indicate the module’s network activity status VOHmin=1.35V VOLmax=0.45V 1.
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LPWA Module Series BG95 Hardware Design (U)SIM card VOHmin=1.35V USIM_DATA 45 IO Data signal of (U)SIM card VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V USIM_CLK 46 DO Clock signal of (U)SIM card VOLmax=0.45V VOHmin=1.35V USIM_GND Specified ground for (U)SIM card 47 Main UART Interface Pin Name DTR RXD TXD CTS RTS DCD RI Pin No.
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LPWA Module Series BG95 Hardware Design Pin Name DBG_RXD DBG_TXD Pin No. 22 23 I/O Description DC Characteristics Comment Receive data VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. DO Transmit data VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. I/O Description DC Characteristics Comment Transmit data VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep this pin open. 1.8V power domain.
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LPWA Module Series BG95 Hardware Design pin open. I2C_SDA* 41 OD I2C serial data. Used for external codec. External pull-up resistor is required. 1.8V only. If unused, keep this pin open. Antenna Interfaces Pin Name Pin No. I/O Description ANT_MAIN 60 IO Main antenna interface 50Ω impedance 49 AI GNSS antenna interface 50Ω impedance. If unused, keep this pin open. Pin No. I/O Description DC Characteristics Comment Generalpurpose input/ output interface VOLmax=0.45V VOHmin=1.
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LPWA Module Series BG95 Hardware Design GPIO65 65 GPIO66 DO Generalpurpose input/ output interface VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. DC Characteristics Comment 66 DO Generalpurpose input/ output interface Pin No.
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LPWA Module Series BG95 Hardware Design DI Application processor sleep state detection VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. 75 DI Force the module to enter into emergency download mode VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep this pin open. Pin Name Pin No.
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LPWA Module Series BG95 Hardware Design Table 6: Overview of Operating Modes Mode Normal Operation Details Connected Network has been connected. In this mode, the power consumption may vary with the network setting and data transfer rate. Idle Software is active. The module remains registered on network, and it is ready to send and receive data.
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LPWA Module Series BG95 Hardware Design Hardware: W_DISABLE#* is pulled up by default. Driving it to low level will let the module enter into airplane mode. Software: AT+CFUN= provides choice of the functionality level, through setting into 0, 1 or 4.  AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.  AT+CFUN=1: Full functionality mode (by default).  AT+CFUN=4: Airplane mode. RF function is disabled. NOTES 1.
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LPWA Module Series BG95 Hardware Design 3.4.3. Extended Idle Mode DRX (e-I-DRX) The module (UE) and the network may negotiate over non-access stratum signalling the use of e-I-DRX for reducing its power consumption, while being available for mobile terminating data and/or network originated procedures within a certain delay dependent on the DRX cycle value.
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LPWA Module Series BG95 Hardware Design Figure 3: Sleep Mode Application via UART    When BG95 has URC to report, RI signal will wake up the host. Please refer to Chapter 3.14 for details about RI behavior. Driving the host DTR to low level will wake up the module. AP_READY* will detect the sleep state of the host (can be configured to high level or low level detection). Please refer to AT+QCFG="apready" command in document [2] for details. NOTE “*” means under development. 3.5. Power Supply 3.5.1.
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LPWA Module Series BG95 Hardware Design Table 7: VBAT and GND Pins Pin Name VBAT_RF VBAT_BB GND Pin No. Description 52, 53 Power supply for the module’s RF part Power supply for the module’s baseband part 32, 33 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67~74, 79~82, 89~91, 100~102 Module Min. Typ. Max. Unit BG95-M1/-M2/-N1 2.4 3.3 4.8 V BG95-M3 3.3 3.8 4.3 V BG95-M1/-M2/-N1 2.4 3.3 4.8 V BG95-M3 3.3 3.8 4.3 V - - - - Ground 3.5.2.
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LPWA Module Series BG95 Hardware Design a single voltage source and can be expanded to two sub paths with star structure. The width of VBAT_BB trace should be no less than 0.5mm, and the width of VBAT_RF trace should be no less than 2mm. In principle, the longer the VBAT trace is, the wider it will be.
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LPWA Module Series BG95 Hardware Design Table 8: Pin Definition of PWRKEY Pin Name PWRKEY Pin No. Description 15 Turn on/off the module DC Characteristics Comment Vnorm=1.5V VILmax=0.45V The output voltage is 1.5V because of the diode drop in the Qualcomm chipset. When BG95 is in power off mode, it can be turned on to normal mode by driving the PWRKEY pin to a low level for a duration between 500ms and 1000ms. It is recommended to use an open drain/collector driver to control the PWRKEY.
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LPWA Module Series BG95 Hardware Design NOTE VBA T PWRKEY 500ms~1000ms VIL≤0.45V RESET_N TBD STATUS (DO) Typ. 2s USB Inactive Active Typ. 2s UART Inactive Active Figure 8: Timing of Turning on Module NOTES 1. Make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than 30ms. 2. PWRKEY is internally pulled up to an internal voltage in the Qualcomm chipset, and its output voltage is the internal voltage minus a diode drop in the chipset.
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LPWA Module Series BG95 Hardware Design The power-down scenario is illustrated in the following figure. VBA T 650ms~150 0ms TBD PWRKEY VIL≤0.45V STATUS Module Status Power-down procedure RUNNING OFF Figure 9: Timing of Turning off Module 3.6.2.2. Turn off Module Using AT Command It is also a safe way to use AT+QPOWD command to turn off the module, which is similar to turning off the module via PWRKEY pin. Please refer to document [2] for details about AT+QPOWD command. 3.7.
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LPWA Module Series BG95 Hardware Design VBA T ≤3.8s ≥2s RESET_N VIL≤0.45V Module Status Running Resetting Restart Figure 10: Timing of Reset Module The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N pin. RESET_N 2s~3.8s 4.
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LPWA Module Series BG95 Hardware Design NOTE Please assure that there is no large capacitance on RESET_N pin. 3.8. (U)SIM Interface The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. BG95 supports 1.8V (U)SIM card only. Table 10: Pin Definition of (U)SIM Interface Pin Name Pin No.
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LPWA Module Series BG95 Hardware Design Figure 13: Reference Circuit of (U)SIM Interface with an 8-Pin (U)SIM Card Connector If (U)SIM card detection function is not needed, please keep USIM_PRESENCE* unconnected. A reference circuit for (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure.
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LPWA Module Series BG95 Hardware Design     Assure the ground between the module and the (U)SIM card connector short and wide. Keep the trace width of ground and USIM_VDD no less than 0.5mm to maintain the same electric potential. Make sure the bypass capacitor between USIM_VDD and USIM_GND less than 1uF, and place it as close to (U)SIM card connector as possible. If the system ground plane is complete, USIM_GND can be connected to the system ground directly.
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LPWA Module Series BG95 Hardware Design The USB interface is recommended to be reserved for firmware upgrade in customers’ designs. The following figure shows a reference circuit of USB interface. Figure 15: Reference Circuit of USB Interface A common mode choke L1 is recommended to be added in series between the module and customer’s MCU in order to suppress EMI spurious transmission.
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LPWA Module Series BG95 Hardware Design 3.10. UART Interfaces The module provides three UART interfaces: Main UART, Debug UART and GNSS UART interfaces. Features of them are illustrated below:    The Main UART interface supports 9600bps, 19200bps, 38400bps, 57600bps, 115200bps, 230400bps, 460800bps and 921600bps baud rates, and the default is 115200bps. It is used for data transmission and AT command communication, and supports RTS and CTS hardware flow control.
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LPWA Module Series BG95 Hardware Design Table 13: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_RXD 22 DI Receive data 1.8V power domain DBG_TXD 23 DO Transmit data 1.8V power domain Table 14: Pin Definition of GNSS UART Interface Pin Name Pin No. I/O Description Comment GNSS_UART_TXD 27 DO Transmit data 1.8V power domain GNSS_UART_RXD 28 DI Receive data 1.
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LPWA Module Series BG95 Hardware Design VDD_EXT VCCA 120K VCCB 10K 0.1uF 0.1uF VDD_MCU OE GND RI A1 B1 RI_MCU DCD A2 B2 DCD_MCU B3 CTS_MCU Translator CTS A3 RTS A4 B4 RTS_MCU DTR A5 B5 DTR_MCU TXD A6 B6 TXD_MCU A7 B7 A8 B8 RXD 51K 51K RXD_MCU Figure 16: Reference Circuit with Translator Chip Please visit http://www.ti.com for more information. Another example with transistor translation circuit is shown as below.
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LPWA Module Series BG95 Hardware Design 3.11. PCM* and I2C* Interfaces BG95 provides one Pulse Code Modulation (PCM) digital interface and one I2C interface. The following table shows the pin definition of the two interfaces which can be applied on audio codec design. Table 16: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_CLK* 4 DO PCM clock output 1.8V power domain PCM_SYNC* 5 DO PCM frame synchronization output 1.
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LPWA Module Series BG95 Hardware Design 3.12. Network Status Indication BG95 provides one network status indication pin: NETLIGHT. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NETLIGHT in different network activity status. Table 17: Pin Definition of NETLIGHT Pin Name Pin No. I/O Description Comment NETLIGHT 21 DO Indicate the module’s network activity status 1.
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LPWA Module Series BG95 Hardware Design 3.13. STATUS The STATUS pin is used to indicate the operation status of BG95 module. It will output high level when the module is powered on. The following table describes the pin definition of STATUS. Table 19: Pin Definition of STATUS Pin Name STATUS Pin No. 20 I/O Description Comment DO Indicate the module’s operation status 1.8V power domain The following figure shows a reference circuit of STATUS. Figure 20: Reference Circuit of STATUS 3.14.
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LPWA Module Series BG95 Hardware Design Table 20: Default Behaviors of RI State Response Idle RI keeps in high level. URC RI outputs 120ms low pulse when new URC returns. The default RI behaviors can be configured flexibly by AT+QCFG=“urc/ri/ring” command. For more details about AT+QCFG*, please refer to document [2]. NOTES 1. URC can be outputted from UART port, USB AT port and USB modem port, through configuration via AT+QURCCFG command. The default port is USB AT port. 2.
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LPWA Module Series BG95 Hardware Design Figure 21: Reference Circuit of USB_BOOT Interface NOTE It is recommended to reserve the above circuit design during application design. 3.16. ADC Interfaces The module provides two analog-to-digital converter (ADC) interfaces but only one ADC interface can be used for each time. AT+QADC=0 command can be used to read the voltage value on the ADC being used. For more details about the AT command, please refer to document [2].
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LPWA Module Series BG95 Hardware Design Table 23: Characteristics of ADC Interfaces Parameter Min. ADC0/ADC1 Voltage Range 0.3 Typ. Max. Unit 1.8 V ADC0/ADC1 Resolution 64.979 uV ADC0/ADC1 Sampling Rate 4.8 MHz NOTES 1. 2. 3. 4. ADC0 and ADC1 cannot be used simultaneously. BG95 supports using of only one ADC interface at a time: either ADC0 or ADC1. Currently only ADC0 is enabled, and ADC1 will be enabled in the next hardware design version. ADC input voltage must not exceed 1.8V.
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LPWA Module Series BG95 Hardware Design The following table describes the characteristics of GPIO interfaces. Table 25: Logic Levels of GPIO Interfaces Parameter Min. Max. Unit VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V NOTE “*” means under development.
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LPWA Module Series BG95 Hardware Design 4 GNSS Receiver 4.1. General Description BG95 includes a fully integrated global navigation satellite system solution that supports Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou and Galileo). BG95 supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, BG95 GNSS engine is switched off. It has to be switched on via AT command.
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LPWA Module Series BG95 Hardware Design Hot start @open sky Accuracy (GNSS) CEP-50 Autonomous TBD s XTRA enabled TBD s Autonomous @open sky TBD m NOTES 1. 2. 3. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock.
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LPWA Module Series BG95 Hardware Design 5 Antenna Interfaces BG95 includes a main antenna interface and a GNSS antenna interface. The antenna ports have an impedance of 50Ω. 5.1. Main Antenna Interface 5.1.1. Pin Definition The pin definition of main antenna interface is shown below. Table 27: Pin Definition of Main Antenna Interface Pin Name Pin No. I/O Description Comment ANT_MAIN 60 IO Main antenna interface 50Ω characteristic impedance 5.1.2.
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LPWA Module Series BG95 Hardware Design LTE-FDD B13 777~787 746~756 MHz LTE-FDD B14 1) 788~798 758~768 MHz LTE-FDD B18 815~830 860~875 MHz LTE-FDD B19 830~845 875~890 MHz LTE-FDD B20 832~862 791~821 MHz LTE-FDD B25 1850~1915 1930~1995 MHz LTE-FDD B26* 814~849 859~894 MHz LTE-FDD B27 1) 807~824 852~869 MHz LTE-FDD B28 703~748 758~803 MHz LTE-TDD B66 1710~1780 2110~2200 MHz LTE-TDD B71 2) 663~698 617~652 MHz LTE-TDD B85 698~716 728~746 MHz NOTES 1.
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LPWA Module Series BG95 Hardware Design Figure 22: Reference Circuit of RF Antenna Interface 5.1.4. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled as 50Ω. The impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S).
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LPWA Module Series BG95 Hardware Design Figure 24: Coplanar Waveguide Line Design on a 2-layer PCB Figure 25: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 26: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) BG95_Hardware_Design 59 / 80
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LPWA Module Series BG95 Hardware Design In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:      Use impedance simulation tool to control the characteristic impedance of RF traces as 50Ω. The GND pins adjacent to RF pins should not be designed as thermal relief pads, and should be fully connected to ground.
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LPWA Module Series BG95 Hardware Design Figure 27: Reference Circuit of GNSS Antenna Interface NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then the VDD circuit is not needed. 5.3. Antenna Installation 5.3.1. Antenna Requirements The following table shows the requirements on main antenna and GNSS antenna.
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LPWA Module Series BG95 Hardware Design Cable Insertion Loss: < 1dB (LTE B5/B8/B12/B13/B14 2)/B18/B19/B20/B26*/B27 2)/B28/B71 3)/ B85, GSM850/EGSM900) Cable Insertion Loss: < 1.5dB (LTE B1/B2/B3/B4/B25/B66, DCS1800/PCS1900) NOTES 1. 1) It is recommended to use a passive GNSS antenna when LTE B13 or B14 is supported, as the use of active antenna may generate harmonics which will affect the GNSS performance. 2. 2) LTE-FDD B14 and B27 are supported by Cat M1 only. 3.
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LPWA Module Series BG95 Hardware Design Figure 29: Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector. Figure 30: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
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LPWA Module Series BG95 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 32: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_BB -0.5 6.0 V VBAT_RF -0.3 6.0 V USB_VBUS -0.3 5.5 V Voltage at Digital Pins -0.3 2.3 V 6.2.
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LPWA Module Series BG95 Hardware Design current (during transmission slot) USB_VBUS control level on EGSM900 BG95-M1/ BG95-M2/ BG95-N1/ BG95-M3 USB detection 3.0 5.0 5.25 V 6.3. Operation and Storage Temperatures The operation and storage temperatures of the module are listed in the following table. Table 34: Operation and Storage Temperatures Parameter Min. Typ. Max.
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LPWA Module Series BG95 Hardware Design Table 35: BG95 RF Output Power Frequency Max. Min. LTE-FDD B1/B2/B3/B4/B5/B8/B12/B13/B14 1)/B18/B19/B20/B25/ B26*/B27 1)/B28/B66/B71 2)/B85 20dBm±2dB <-39dBm GSM850/EGSM900 33dBm±2dB 5dBm±5dB DCS1800/PCS1900 30dBm±2dB 0dBm±5dB GSM850/EGSM900 (8-PSK) 27dBm±3dB 5dBm±5dB DCS1800/PCS1900 (8-PSK) 26dBm±3dB 0dBm±5dB NOTES 1. 2. 3. 1) LTE-FDD B14 and B27 are supported by Cat M1 only. LTE-FDD B71 is supported by Cat NB2 only. “*” means under development.
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LPWA Module Series BG95 Hardware Design LTE-FDD B13 TBD /-99.3 TBD/-107.5 LTE-FDD B14 TBD /-99.3 / LTE-FDD B18 TBD /-102.3 TBD/-107.5 LTE-FDD B19 TBD /-102.3 TBD/-107.5 LTE-FDD B20 TBD /-99.8 TBD/-107.5 LTE-FDD B25 TBD /-100.3 TBD/-107.5 LTE-FDD B26* TBD /-100.3 TBD/-107.5 LTE-FDD B27 TBD /-100.8 / LTE-FDD B28 TBD /-100.8 TBD/-107.5 LTE-FDD B66 TBD TBD/-107.5 LTE-FDD B71 / TBD/-107.5 LTE-FDD B85 TBD TBD/-107.
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LPWA Module Series BG95 Hardware Design Table 37: Electrostatic Discharge Characteristics (25ºC, 45% Relative Humidity) Tested Points Contact Discharge Air Discharge Unit VBAT, GND TBD TBD kV Main/GNSS Antenna Interfaces TBD TBD kV BG95_Hardware_Design 68 / 80
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LPWA Module Series BG95 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and the tolerances for dimensions without tolerance values are ±0.05mm. 7.1. Mechanical Dimensions of the Module 19.90±0.15 2.2±0.2 23.60±0.
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LPWA Module Series BG95 Hardware Design 19.90±0.15 7.45 7.15 1.95 1.10 0.55 1.10 0.20 1.00 1.00 0.20 5.10 Pin 1 23.60±0.15 8.50 1.00 0.85 1.70 1.90 1.10 1.00 1.70 1.00 1.70 1.15 0.55 0.20 40x1.0 0.70 0.50 0.20 62x0.7 40x1.0 62x1.
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LPWA Module Series BG95 Hardware Design 7.2. Recommended Footprint 19.90±0.15 9.18 9.18 1.10 1.95 0.55 1.10 0.20 1.00 Pin 1 0.20 5.10 2.55 2.55 1.90 0.85 4.25 5.95 7.65 1.70 0.15 8.50 0.85 4.25 5.95 7.65 23.60±0.15 1.00 1.10 0.85 0.85 1.70 1.00 0.50 0.20 0.70 1.15 1.70 1.00 0.20 0.55 4.25 5.95 4.25 5.95 40x1.0 62x0.7 62x1.15 9.70 11.03 1.00 7.15 9.60 11.03 7.45 40x1.0 Figure 33: Recommended Footprint (Top View) NOTES 1. 2. 3.
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LPWA Module Series BG95 Hardware Design 7.3. Design Effect Drawings of the Module Figure 34: Top View of the Module Figure 35: Bottom View of the Module NOTE These are renderings of BG95 module. For authentic appearance, please refer to the module that you receive from Quectel.
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LPWA Module Series BG95 Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage BG95 is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in the vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:   Mounted within 168 hours at the factory environment of ≤30ºC/60%RH. Stored at <10%RH. 3.
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LPWA Module Series BG95 Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.13mm~0.15mm. For more details, please refer to document [5].
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LPWA Module Series BG95 Hardware Design Reflow Zone Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 238°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 8.3. Packaging BG95 is packaged in a vacuum-sealed bag which is ESD protected. The bag should not be opened until the devices are ready to be soldered onto the application. The reel is 330mm in diameter and each reel contains 250 modules.
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LPWA Module Series BG95 Hardware Design DETAIL:A 6 PS DETAIL:A Figure 38: Reel Dimensions Table 39: Reel Packaging Model Name BG95 MOQ for MP Minimum Package: 250pcs Minimum Package x 4=1000pcs 250pcs Size: 370mm × 350mm × 56mm N.W: 0.61kg G.W: 1.35kg Size: 380mm × 250mm × 365mm N.W: 2.45kg G.W: 6.
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LPWA Module Series BG95 Hardware Design 9 Appendix A References Table 40: Related Documents SN Document Name Remark [1] Quectel_UMTS<E_EVB_User_Guide UMTS<E EVB User Guide [2] Quectel_BG95_AT_Commands_Manual BG95 AT Commands Manual [3] Quectel_BG95_GNSS_AT_Commands_Manual BG95 GNSS AT Commands Manual [4] Quectel_RF_Layout_Application_Note RF Layout Application Note [5] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide Table 41: Terms and Abbreviations Abbreviat
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LPWA Module Series BG95 Hardware Design ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GMSK Gaussian Minimum Shift Keying GSM Global System for Mobile Communications HSS Home Subscriber Server I/O Input/Output Inorm Normal Current LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol D
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LPWA Module Series BG95 Hardware Design TX Transmitting Direction UL Uplink UE User Equipment URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Abso
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LPWA Module Series BG95 Hardware Design 10 Appendix B GPRS Coding Schemes Table 42: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
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LPWA Module Series BG95 Hardware Design 11 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
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LPWA Module Series BG95 Hardware Design 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 BG95_Hardware_Design 82 / 80
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LPWA Module Series BG95 Hardware Design 12 Appendix D EDGE Modulation and Coding Schemes Table 44: EDGE Modulation and Coding Schemes Coding Schemes Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1 GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2 GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3 GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4 GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps MCS-3 GMSK A 14.