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EG21-G

Hardware Design

LTE Module Series

Rev. EG21-G_Hardware_Design_V1.0

Date: 2019-03-12

Status: Released

www.quectel.com

Summary of content (96 pages)

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EG21-G Hardware Design LTE Module Series Rev. EG21-G_Hardware_Design_V1.0 Date: 2019-03-12 Status: Released www.quectel.
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LTE Module Series EG21-G Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
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LTE Module Series EG21-G Hardware Design About the Document History Revision Date Author Description 1.
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LTE Module Series EG21-G Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index ...........................................................................................................................................
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LTE Module Series EG21-G Hardware Design 3.17. Behaviors of RI ..................................................................................................................... 51 3.18. USB_BOOT Interface............................................................................................................ 51 4 GNSS Receiver ................................................................................................................................ 54 4.1. General Description ..................
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LTE Module Series EG21-G Hardware Design Table Index TABLE 1: FREQUENCY BANDS OF EG21-G MODULE ................................................................................... 11 TABLE 2: KEY FEATURES OF EG21-G MODULE........................................................................................... 12 TABLE 3: I/O PARAMETERS DEFINITION ....................................................................................................... 18 TABLE 4: PIN DESCRIPTION .............................
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LTE Module Series EG21-G Hardware Design TABLE 44: EDGE MODULATION AND CODING SCHEMES ...........................................................................
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LTE Module Series EG21-G Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 15 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 17 FIGURE 3: SLEEP MODE APPLICATION VIA UART .......................................................................................
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LTE Module Series EG21-G Hardware Design FIGURE 41: REFERENCED HEATSINK DESIGN (HEATSINK AT THE TOP OF THE MODULE) .................. 75 FIGURE 42: REFERENCED HEATSINK DESIGN (HEATSINK AT THE BACKSIDE OF CUSTOMERS’ PCB) ................................................................................................................................................................... 75 FIGURE 43: MODULE TOP AND SIDE DIMENSIONS...................................................................................
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LTE Module Series EG21-G Hardware Design 1 Introduction This document defines EG21-G module, and describes its air interfaces and hardware interfaces which are connected with customers’ applications. This document can help customers quickly understand module interface specifications, electrical and mechanical details as well as other related information of EG21-G module. To facilitate its application in different fields, relevant reference design is also provided for customers’ reference.
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LTE Module Series EG21-G Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating EG21-G module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
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LTE Module Series EG21-G Hardware Design 2 Product Concept 2.1. General Description EG21-G is an LTE-FDD/LTE-TDD/UMTS/GSM wireless communication module with receive diversity. It provides data connectivity on LTE-FDD, LTE-TDD, DC-HSDPA, HSPA+, HSDPA, HSUPA, UMTS, EDGE and GPRS networks. It also provides GNSS 1) and voice functionality 2) for customers’ specific applications. The following table shows the frequency bands of EG21-G module.
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LTE Module Series EG21-G Hardware Design 2.2. Key Features The following table describes the detailed features of EG21-G module. Table 2: Key Features of EG21-G Module Feature Details Power Supply Supply voltage: 3.3V~4.3V Typical supply voltage: 3.
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LTE Module Series EG21-G Hardware Design Internet Protocol Features Support TCP/UDP/PPP/FTP/HTTP/NTP/PING/QMI/NITZ/CMUX*/HTTPS*/ SMTP/MMS*/FTPS*/SMTPS*/SSL*/FILE* protocols Support PAP (Password Authentication Protocol) and CHAP (Challenge Handshake Authentication Protocol) protocols which are usually used for PPP connections SMS Text and PDU mode Point to point MO and MT SMS cell broadcast SMS storage: ME by default (U)SIM Interface Support USIM/SIM card: 1.8V, 3.
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LTE Module Series EG21-G Hardware Design Antenna Interfaces Including main antenna interface (ANT_MAIN), Rx-diversity antenna interface (ANT_DIV) and GNSS antenna interface (ANT_GNSS) Physical Characteristics Size: (29.0±0.15)mm × (32.0±0.15)mm × (2.4±0.2)mm Weight: approx. 4.
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LTE Module Series EG21-G Hardware Design ANT_MAIN ANT_GNSS ANT_DIV PAM SAW Switch Duplex LNA SAW VBAT_RF PA APT PRx DRx Tx NAND DDR2 SDRAM Transceiver IQ VBAT_BB PMIC Control Control PWRKEY Baseband RESET_N ADCs 19.2M XO STATUS VDD_EXT USB (U)SIM PCM I2C UARTs GPIOs SD Figure 1: Functional Diagram NOTE “*” means under development. 2.4.
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LTE Module Series EG21-G Hardware Design 3 Application Interfaces 3.1. General Description EG21-G is equipped with 144 LGA pads that can be connected to cellular application platform.
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LTE Module Series EG21-G Hardware Design 3.2. Pin Assignment The following figure shows the pin assignment of EG21-G module.
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LTE Module Series EG21-G Hardware Design 3.3. Pin Description The following tables show the pin definition of EG21-G modules. Table 3: I/O Parameters Definition Type Description AI Analog input AO Analog output DI Digital input DO Digital output IO Bidirectional OD Open drain PI Power input PO Power output Table 4: Pin Description Power Supply Pin Name VBAT_BB VBAT_RF Pin No.
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LTE Module Series EG21-G Hardware Design 56, 72, 85~112 Turn on/off Pin Name Description DC Characteristics Comment Turn on/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V The output voltage is 0.8V because of the diode drop in the Qualcomm chipset. DI Reset the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V If unused, keep it open. I/O Description DC Characteristics Comment OD Indicate the module operating status The drive current should be less than 0.9mA.
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LTE Module Series EG21-G Hardware Design Pin Name Pin No. USIM_GND 10 I/O Description DC Characteristics Specified ground for (U)SIM card Comment Connect (U)SIM card connector GND. For 1.8V (U)SIM: Vmax=1.9V Vmin=1.7V USIM_VDD 14 PO Power supply for (U)SIM card For 3.0V (U)SIM: Vmax=3.05V Vmin=2.7V Either 1.8V or 3.0V is supported by the module automatically.
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LTE Module Series EG21-G Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment 1.8V power domain. If unused, keep it open. RI 62 DO Ring indicator VOLmax=0.45V VOHmin=1.35V DCD 63 DO Data carrier detection VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Clear to send VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Request to send VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain.
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LTE Module Series EG21-G Hardware Design analog to digital converter ADC1 0.3V to VBAT_BB open. Voltage range: 0.3V to VBAT_BB If unused, keep it open. Comment 44 AI General purpose analog to digital converter Pin No. I/O Description DC Characteristics PCM Interface Pin Name PCM_IN 24 DI PCM data input VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V PCM_OUT 25 DO PCM data output VOLmax=0.45V VOHmin=1.35V PCM data frame synchronization signal VOLmax=0.45V VOHmin=1.35V VILmin=-0.
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LTE Module Series EG21-G Hardware Design VOHmin=1.4V VILmin=-0.3V VILmax=0.58V VIHmin=1.27V VIHmax=2.0V 3.0V signaling: VOLmax=0.38V VOHmin=2.01V VILmin=-0.3V VILmax=0.76V VIHmin=1.72V VIHmax=3.34V SDC2_ DATA2 SDC2_ DATA1 29 30 IO IO EG21-G_Hardware_Design SD card SDIO bus DATA2 SD card SDIO bus DATA1 1.8V signaling: VOLmax=0.45V VOHmin=1.4V VILmin=-0.3V VILmax=0.58V VIHmin=1.27V VIHmax=2.0V 3.0V signaling: VOLmax=0.38V VOHmin=2.01V VILmin=-0.3V VILmax=0.76V VIHmin=1.72V VIHmax=3.34V 1.
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LTE Module Series EG21-G Hardware Design SDC2_ DATA0 SDC2_CLK SDC2_CMD SD_INS_ DET 31 32 33 23 IO DO IO DI EG21-G_Hardware_Design SD card SDIO bus DATA0 SD card SDIO bus clock SD card SDIO bus command SD card insertion detect 1.8V signaling: VOLmax=0.45V VOHmin=1.4V VILmin=-0.3V VILmax=0.58V VIHmin=1.27V VIHmax=2.0V 3.0V signaling: VOLmax=0.38V VOHmin=2.01V VILmin=-0.3V VILmax=0.76V VIHmin=1.72V VIHmax=3.34V 1.8V signaling: VOLmax=0.45V VOHmin=1.4V 3.0V signaling: VOLmax=0.38V VOHmin=2.
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LTE Module Series EG21-G Hardware Design VDD_SDIO 34 SD card SDIO bus pull-up power IOmax=50mA 1.8V/2.85V configurable. Cannot be used for SD card power. If unused, keep it open. DI BT UART request to send VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. DO BT UART transmit data VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. BT UART receive data VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain.
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LTE Module Series EG21-G Hardware Design the module. If unused, keep it open. W_DISABLE# 4 AP_READY 2 1.8V power domain. Pull-up by default. In low voltage level, module can enter into airplane mode. If unused, keep it open. DI Airplane mode control VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V DI Application processor sleep state detection VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open.
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LTE Module Series EG21-G Hardware Design Table 5: Overview of Operating Modes Mode Normal Operation Details Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate. Minimum Functionality Mode AT+CFUN command can set the module to a minimum functionality mode without removing the power supply.
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LTE Module Series EG21-G Hardware Design Host Module RXD TXD TXD RXD RI EINT DTR GPIO AP_READY GPIO GND GND Figure 3: Sleep Mode Application via UART    Driving the host DTR to low level will wake up the module. When EG21-G has a URC to report, RI signal will wake up the host. Please refer to Chapter 3.19 for details about RI behaviors. AP_READY will detect the sleep state of the host (can be configured to high level or low level detection).
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LTE Module Series EG21-G Hardware Design Host Module USB_VBUS VDD USB_DP USB_DP USB_DM USB_DM AP_READY GPIO GND GND Figure 4: Sleep Mode Application with USB Remote Wakeup   Sending data to EG21-G through USB will wake up the module. When EG21-G has a URC to report, the module will send remote wake-up signals via USB bus so as to wake up the host. 3.5.1.3.
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LTE Module Series EG21-G Hardware Design Figure 5: Sleep Mode Application with RI   Sending data to EG21-G through USB will wake up the module. When EG21-G has a URC to report, RI signal will wake up the host. 3.5.1.4. USB Application without USB Suspension Function If the host does not support USB suspension function, USB_VBUS should be disconnected via an additional control circuit to let the module enter into sleep mode.    Execute AT+QSCLK=1 command to enable the sleep mode.
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LTE Module Series EG21-G Hardware Design Hardware: The W_DISABLE# pin is pulled up by default; driving it to low level will let the module enter into airplane mode. Software: AT+CFUN command provides the choice of the functionality level through setting into 0, 1 or 4.  AT+CFUN=0: Minimum functionality mode. Both (U)SIM and RF functions are disabled.  AT+CFUN=1: Full functionality mode (by default).  AT+CFUN=4: Airplane mode. RF function is disabled. NOTES 1. 2.
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LTE Module Series EG21-G Hardware Design 56, 72, 85~112 3.6.2. Decrease Voltage Drop The power supply range of the module is from 3.3V to 4.3V. Please make sure that the input voltage will never drop below 3.3V. The following figure shows the voltage drop during burst transmission in 2G network. The voltage drop will be less in 3G and 4G networks. Burst Transmission Burst Transmission VBAT Ripple Drop Min.3.
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LTE Module Series EG21-G Hardware Design Figure 8: Star Structure of the Power Supply 3.6.3. Reference Design for Power Supply Power design for the module is very important, as the performance of the module largely depends on the power source. The power supply should be able to provide sufficient current up to 2A at least. If the voltage drop between the input and output is not too high, it is suggested that an LDO should be used to supply power for the module.
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LTE Module Series EG21-G Hardware Design 3.7. Power-on and off Scenarios 3.7.1. Turn on Module Using the PWRKEY The following table shows the pin definition of PWRKEY. Table 7: Pin Definition of PWRKEY Pin Name PWRKEY Pin No. 21 I/O DI Description Comment Turn on/off the module The output voltage is 0.8V because of the diode drop in the Qualcomm chipset. When EG21-G is in power-down mode, it can be turned on to normal mode by driving the PWRKEY pin to a low level for at least 500ms.
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LTE Module Series EG21-G Hardware Design Figure 11: Turn on the Module by Using Keystroke The power-on scenario is illustrated in the following figure. NOTE VBA T ≥500ms VIH ≥1.3V PWRKEY VIL≤0.5V Abo ut 100ms VDD_EXT BOO T_CONFIG & USB_BOO T ≥100ms. Ater thi s time, the BOOT_CONFIG pin can be se t high level by external circu it. RESET_N ≥2.
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LTE Module Series EG21-G Hardware Design 3.7.2.1. Turn off Module Using the PWRKEY Pin Driving the PWRKEY pin to a low level voltage for at least 650ms, the module will execute power-down procedure after the PWRKEY is released. The power-off scenario is illustrated in the following figure. VBAT ≥650ms ≥29.5s PWRKEY STATUS (OD) Module Status RUNNING Power-down procedure OFF Figure 13: Power-off Scenario of Module 3.7.2.2.
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LTE Module Series EG21-G Hardware Design Table 8: RESET_N Pin Description Pin Name Pin No. I/O Description Comment RESET_N 20 DI Reset the module 1.8V power domain The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N. RESET_N 150ms~460ms 4.
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LTE Module Series EG21-G Hardware Design VBAT ≤460ms ≥150ms VIH≥1.3V RESET_N VIL≤0.5V Module Status Running Resetting Restart Figure 16: Timing of Resetting Module NOTES 1. 2. Use RESET_N only when failed to turn off the module by AT+QPOWD command and PWRKEY pin. Ensure that there is no large capacitance on PWRKEY and RESET_N pins. 3.9. (U)SIM Interface The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8V and 3.0V (U)SIM cards are supported.
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LTE Module Series EG21-G Hardware Design and high level detections, and is disabled by default. Please refer to document [2] for more details about AT+QSIMDET command. The following figure shows a reference design for (U)SIM interface with an 8-pin (U)SIM card connector.
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LTE Module Series EG21-G Hardware Design In order to enhance the reliability and availability of the (U)SIM card in customers’ applications, please follow the criteria below in (U)SIM circuit design:       Keep placement of (U)SIM card connector to the module as close as possible. Keep the trace length as less than 200mm as possible. Keep (U)SIM card signals away from RF and VBAT traces. Assure the ground between the module and the (U)SIM card connector short and wide.
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LTE Module Series EG21-G Hardware Design For more details about the USB 2.0 specifications, please visit http://www.usb.org/home. The USB interface is recommended to be reserved for firmware upgrade in customers’ designs. The following figure shows a reference circuit of USB interface.
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LTE Module Series EG21-G Hardware Design 1. 2. EG21-G module can only be used as a slave device. “*” means under development. 3.11. UART Interfaces The module provides two UART interfaces: the main UART interface and the debug UART interface. The following shows their features.   The main UART interface supports 4800bps, 9600bps, 19200bps, 38400bps, 57600bps, 115200bps, 230400bps, 460800bps and 921600bps baud rates, and the default is 115200bps.
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LTE Module Series EG21-G Hardware Design The logic levels are described in the following table. Table 13: Logic Levels of Digital I/O Parameter Min. Max. Unit VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V The module provides 1.8V UART interface. A level translator should be used if customers’ application is equipped with a 3.3V UART interface. A level translator TXS0108EPWR provided by Texas Instruments is recommended. The following figure shows a reference design.
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LTE Module Series EG21-G Hardware Design VDD_EXT MCU/ARM 4.7K VDD_EXT 1nF 10K Module RXD TXD RXD TXD 10K VCC_MCU RTS CTS GPIO EINT GPIO GND 1nF 4.7K VDD_EXT RTS CTS DTR RI DCD GND Figure 21: Reference Circuit with Transistor Circuit NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps. 3.12.
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LTE Module Series EG21-G Hardware Design 125us PCM_CLK 1 2 255 256 PCM_SYNC MSB LSB MSB MSB LSB MSB PCM_OUT PCM_IN Figure 22: Primary Mode Timing 125us 1 PCM_CLK 2 31 32 PCM_SYNC MSB LSB MSB LSB PCM_OUT PCM_IN Figure 23: Auxiliary Mode Timing The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio codec design. Table 14: Pin Definition of PCM and I2C Interfaces Pin Name Pin No.
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LTE Module Series EG21-G Hardware Design PCM_SYNC 26 IO PCM data frame synchronization signal 1.8V power domain PCM_CLK 27 IO PCM data bit clock 1.8V power domain I2C_SCL 41 OD I2C serial clock Require external pull-up to 1.8V I2C_SDA 42 OD I2C serial data Require external pull-up to 1.8V Clock and mode can be configured by AT command, and the default configuration is master mode using short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC.
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LTE Module Series EG21-G Hardware Design Table 15: Pin Definition of SD Card Interface Pin Name Pin No. I/O Description Comment SDC2_DATA3 28 IO SD card SDIO bus DATA3 SDC2_DATA2 29 IO SD card SDIO bus DATA2 SDC2_DATA1 30 IO SD card SDIO bus DATA1 SDC2_DATA0 31 IO SD card SDIO bus DATA0 SDC2_CLK 32 DO SD card SDIO bus clock SDC2_CMD 33 IO SD card SDIO bus command SDIO signal level can be selected according to SD card supported level, please refer to SD 3.
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LTE Module Series EG21-G Hardware Design        should be provided. As the maximum output current of VDD_SDIO is 50mA which can only be used for SDIO pull-up resistors, an externally power supply is needed for SD card. To avoid jitter of bus, resistors R7~R11 are needed to pull up the SDIO to VDD_SDIO. Value of these resistors is among 10KΩ~100KΩ and the recommended value is 100KΩ. VDD_SDIO should be used as the pull-up power.
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LTE Module Series EG21-G Hardware Design Table 17: Characteristic of ADC Parameter Min. ADC0 Voltage Range ADC1 Voltage Range Typ. Max. Unit 0.3 VBAT_BB V 0.3 VBAT_BB V ADC Resolution 15 Bits NOTES 1. 2. 3. ADC input voltage must not exceed VBAT_BB. It is prohibited to supply any voltage to ADC pins when VBAT is removed. It is recommended to use resistor divider circuit for ADC application. 3.15.
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LTE Module Series EG21-G Hardware Design Flicker slowly (1800ms High/200ms Low) Idle Flicker quickly (125ms High/125ms Low) Data transfer is ongoing Always High Voice calling A reference circuit is shown in the following figure. Module VBAT 2.2K Network Indicator 4.7K 47K Figure 26: Reference Circuit of the Network Indicator 3.16. STATUS The STATUS pin is an open drain output for indicating the module’s operation status.
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LTE Module Series EG21-G Hardware Design Module Module VDD_MCU VBAT 10K 2.2K STATUS MCU_GPIO STATUS Figure 27: Reference Circuits of STATUS 3.17. Behaviors of RI AT+QCFG="risignaltype","physical" command can be used to configure RI behavior. No matter on which port a URC is presented, the URC will trigger the behavior of RI pin. NOTE URC can be outputted from UART port, USB AT port and USB modem port through configuration via AT+QURCCFG command. The default port is USB AT port.
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LTE Module Series EG21-G Hardware Design EG21-G provides a USB_BOOT pin. Customers can pull up USB_BOOT to VDD_EXT before powering on the module, thus the module will enter into emergency download mode when powered on. In this mode, the module supports firmware upgrade over USB interface. Table 22: Pin Definition of USB_BOOT Interface Pin Name USB_BOOT Pin No. I/O 115 DI Description Comment Force the module to enter into emergency download mode 1.8V power domain. Active high.
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LTE Module Series EG21-G Hardware Design Figure 29: Timing Sequence for Entering into Emergency Download Mode NOTES 1. 2. Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than 30ms. When using MCU to control module to enter into the forced download mode, follow the above timing sequence. It is not recommended to pull up USB_BOOT to 1.8V before powering up the VBAT.
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LTE Module Series EG21-G Hardware Design 4 GNSS Receiver 4.1. General Description EG21-G includes a fully integrated global navigation satellite system solution that supports Gen8C Lite of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS ). EG21-G supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, EG21-G GNSS engine is switched off. It has to be switched on via AT command.
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LTE Module Series EG21-G Hardware Design Accuracy (GNSS) @open sky XTRA enabled 1.6 s CEP-50 Autonomous @open sky <4 m NOTES 1. 2. 3. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock.
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LTE Module Series EG21-G Hardware Design 5 Antenna Interfaces EG21-G antenna interfaces include a main antenna interface, an Rx-diversity antenna interface which is used to resist the fall of signals caused by high speed movement and multipath effect, and a GNSS antenna interface. The impedance of the antenna port is 50Ω. 5.1. Main/Rx-diversity Antenna Interfaces 5.1.1. Pin Definition The pin definition of main antenna and Rx-diversity antenna interfaces is shown below.
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LTE Module Series EG21-G Hardware Design WCDMA B2 1850~1910 1930~1990 MHz WCDMA B4 1710~1755 2110~2155 MHz WCDMA B5 824~849 869~894 MHz WCDMA B6 830~840 875~885 MHz WCDMA B8 880~915 925~960 MHz WCDMA B19 830~845 875~890 MHz LTE-FDD B1 1920~1980 2110~2170 MHz LTE-FDD B2 1850~1910 1930~1990 MHz LTE-FDD B3 1710~1785 1805~1880 MHz LTE-FDD B4 1710~1755 2110~2155 MHz LTE-FDD B5 824~849 869~894 MHz LTE-FDD B7 2500~2570 2620~2690 MHz LTE-FDD B8 880~915 925~960 MHz
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LTE Module Series EG21-G Hardware Design 5.1.3. Reference Design of RF Antenna Interface A reference design of ANT_MAIN and ANT_DIV antenna pads is shown as below. A π-type matching circuit should be reserved for better RF performance. The capacitors are not mounted by default. Main Antenna Module R1 0R ANT_MAIN C1 C2 NM NM Diversity Antenna R2 0R ANT_DIV C3 C4 NM NM Figure 30: Reference Circuit of RF Antenna Interface NOTES 1. 2. 3.
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LTE Module Series EG21-G Hardware Design .
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LTE Module Series EG21-G Hardware Design Figure 34: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) To ensure RF performance and reliability, the following principles should be complied with in RF layout design:      Use an impedance simulation tool to control the characteristic impedance of RF traces as 50Ω. The GND pins adjacent to RF pins should be designed as thermal relief pads, and should be fully connected to ground.
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LTE Module Series EG21-G Hardware Design Table 27: GNSS Frequency Type Frequency Unit GPS/Galileo/QZSS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz BeiDou 1561.098±2.046 MHz A reference design of GNSS antenna is shown as below. VDD GNSS Antenna 10R 0.1uF Module 47nH 100pF ANT_GNSS NM NM Figure 35: Reference Circuit of GNSS Antenna NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement.
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LTE Module Series EG21-G Hardware Design Table 28: Antenna Requirements Type Requirements GNSS 1) Frequency range: 1559MHz~1609MHz Polarization: RHCP or linear VSWR: <2 (Typ.) Passive antenna gain: >0dBi Active antenna noise figure: <1.5dB Active antenna gain: >-2dBi Active antenna embedded LNA gain: 20dB (Typ.) Active antenna total gain: >18dBi (Typ.
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LTE Module Series EG21-G Hardware Design Figure 36: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 37: Mechanicals of U.
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LTE Module Series EG21-G Hardware Design The following figure describes the space factor of mated connector. Figure 38: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://hirose.com.
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LTE Module Series EG21-G Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 29: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 0.8 A Peak Current of VBAT_RF 0 1.8 A Voltage at Digital Pins -0.3 2.
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LTE Module Series EG21-G Hardware Design 6.2. Power Supply Ratings Table 30: The Module Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT_BB and VBAT_RF The actual input voltages must stay between the minimum and maximum values. 3.3 3.8 4.3 V Voltage drop during burst transmission Maximum power control level on EGSM900. 400 mV IVBAT Peak supply current (during transmission slot) Maximum power control level on EGSM900. 1.8 2.
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LTE Module Series EG21-G Hardware Design 6.4. Current Consumption Table 32: EG21-G Current Consumption Parameter Description Conditions Typ.
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LTE Module Series EG21-G Hardware Design LTE-TDD @PF=64 (USB suspended) TBD mA LTE-TDD @PF=128 (USB disconnected) TBD mA LTE-TDD @PF=256 (USB disconnected) TBD mA EGSM @DRX=5 (USB disconnected) TBD mA EGSM @DRX=5 (USB connected) TBD mA WCDMA @PF=64 (USB disconnected) TBD mA WCDMA @PF=64 (USB connected) TBD mA LTE-FDD @PF=64 (USB disconnected) TBD mA LTE-FDD @PF=64 (USB connected) TBD mA LTE-TDD @ PF=64 (USB disconnected) TBD mA LTE-TDD @ PF=64 (USB connected) TBD mA GSM900
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LTE Module Series EG21-G Hardware Design EDGE data transfer (GNSS OFF) WCDMA data transfer (GNSS OFF) EG21-G_Hardware_Design GSM900 4DL/1UL @27dBm TBD mA GSM900 3DL/2UL @26dBm TBD mA GSM900 2DL/3UL @24dBm TBD mA GSM900 1DL/4UL @23dBm TBD mA GSM850 4DL/1UL @27dBm TBD mA GSM850 3DL/2UL @26dBm TBD mA GSM850 2DL/3UL @24dBm TBD mA GSM850 1DL/4UL @23dBm TBD mA DCS1800 4DL/1UL @26dBm TBD mA DCS1800 3DL/2UL @25dBm TBD mA DCS1800 2DL/3UL @23dBm TBD mA DCS1800 1DL/4UL @22dBm TBD
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LTE Module Series EG21-G Hardware Design LTE data transfer (GNSS OFF) GSM voice call EG21-G_Hardware_Design WCDMA B8 HSUPA @20.5dBm TBD mA WCDMA B19 HSDPA @21dBm TBD mA WCDMA B19 HSUPA @20.5dBm TBD mA LTE-FDD B1 @22.3dBm TBD mA LTE-FDD B2 @22.3dBm TBD mA LTE-FDD B3 @22.3dBm TBD mA LTE-FDD B4 @22.3dBm TBD mA LTE-FDD B5 @22.3dBm TBD mA LTE-FDD B7 @22.3dBm TBD mA LTE-FDD B8 @22.3dBm TBD mA LTE-FDD B12 @22.3dBm TBD mA LTE-FDD B13 @22.3dBm TBD mA LTE-FDD B18 @22.
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LTE Module Series EG21-G Hardware Design WCDMA voice call GSM850PCL=19 @5.5dBm TBD mA DCS1800 PCL=0 @29.5dBm TBD mA DCS1800 PCL=7 @16.5dBm TBD mA DCS1800 PCL=15 @0.5dBm TBD mA PCS1900 PCL=0 @29.5dBm TBD mA PCS1900 PCL=7 @16.5dBm TBD mA PCS1900 PCL=15 @0.5dBm TBD mA WCDMA B1 @22.5dBm TBD mA WCDMA B2 @22.5dBm TBD mA WCDMA B4 @22.5dBm TBD mA WCDMA B5 @22.5dBm TBD mA WCDMA B6 @22.5dBm TBD mA WCDMA B8 @22.5dBm TBD mA WCDMA B19 @22.
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LTE Module Series EG21-G Hardware Design 6.5. RF Output Power The following table shows the RF output power of EG21-G module. Table 34: RF Output Power Frequency Max. Min.
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LTE Module Series EG21-G Hardware Design PCS1900MHz -107.5dBm NA NA -102dBm WCDMA B1 -108.2dBm -108.5dBm -109.2dBm -106.7dBm WCDMA B2 -109.5dBm -109dBm -110dBm -104.7dBm WCDMA B4 -109.5dBm NA NA -106.7dBm WCDMA B5 -109.2dBm -109.5dBm -110.4dBm -104.7dBm WCDMA B6 -109dBm -109.5dBm -110.5dBm -106.7dBm WCDMA B8 -109.5dBm NA NA -103.7dBm WCDMA B19 -109dBm -109.5dBm -110.1dBm -106.7dBm LTE-FDD B1 (10M) -97.3dBm -98.3dBm -99.5dBm -96.
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LTE Module Series EG21-G Hardware Design LTE-TDD B40 (10M) -97.8dBm -97.5dBm -99.2dBm -96.3dBm LTE-TDD B41 (10M) -97.3dBm -97.4dBm -99dBm -94.3dBm 6.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general. Consequently, it is subject to ESD handling precautions that typically apply to ESD sensitive components.
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LTE Module Series EG21-G Hardware Design  The heatsink should be designed with as many fins as possible to increase heat dissipation area. Meanwhile, a thermal pad with high thermal conductivity should be used between the heatsink and module/PCB. The following shows two kinds of heatsink designs for reference and customers can choose one or both of them according to their application structure.
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LTE Module Series EG21-G Hardware Design NOTES 1. 2. The module offers the best performance when the internal BB chip stays below 105°C. When the maximum temperature of the BB chip reaches or exceeds 105°C, the module works normal but provides reduced performance (such as RF output power, data rate, etc.).
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LTE Module Series EG21-G Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm. The tolerances for dimensions without tolerance values are ±0.05mm. 7.1. Mechanical Dimensions of the Module 2.4+/-0.2 (29+/-0.15) (32+/-0.15) 0.
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LTE Module Series EG21-G Hardware Design 32㊣0.15 1.90 3.85 3.5 1.30 3.35 5.96 1.30 1.30 2.0 0.82 1.8 3.0 1.15 2.15 1.8 2.8 4.88 1.10 1.10 1.05 1.6 4.8 6.75 29㊣0.15 2.0 0.80 1.7 4.4 2.49 3.2 3.4 3.2 1.50 2.40 3.45 3.4 3.5 1.25 3.2 1.
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LTE Module Series EG21-G Hardware Design 7.2. Recommended Footprint Figure 43: Recommended Footprint (Top View) NOTES 1. 2. 3. The keepout area should not be designed. For easy maintenance of the module, please keep about 3mm between the module and other components in the host PCB. EG21-G share the same recommended footprint with EC25, but different recommended stencil. Refer to document [4] for more information.
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LTE Module Series EG21-G Hardware Design 7.3. Design Effect Drawings of the Module Figure 44: Top View of the Module Figure 45: Bottom View of the Module NOTE These are design effect drawings of EG21-G module. For more accurate pictures, please refer to the module that you get from Quectel.
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LTE Module Series EG21-G Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage EG21-G is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:   Mounted within 168 hours at the factory environment of ≤30ºC/60%RH. Stored at <10% RH. 3.
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LTE Module Series EG21-G Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.13mm~0.15mm. For more details, please refer to document [4].
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LTE Module Series EG21-G Hardware Design Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 240°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 NOTES 1. During manufacturing and soldering, or any other processes that may contact the module directly, NEVER wipe the module’s shielding can with organic solvents, such as acetone, ethyl alcohol, isopropyl alcohol, trichloroethylene, etc. Otherwise, the shielding can may become rusted. 2.
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LTE Module Series EG21-G Hardware Design 48.5 Cover tape 13 100 Direction of feed 44.5+0.20 -0.
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LTE Module Series EG21-G Hardware Design 9 Appendix A References Table 38: Related Documents SN Document Name Remark [1] Quectel_EC2x&EGxx&EM05_Power_Management_ Application_Note Power management application note for EC25, EC21, EC20 R2.0, EC20 R2.1, EG95, EG91, EG25-G and EM05 modules [2] Quectel_EG25-G _AT_Commands_Manual EG25-G AT Commands Manual [3] Quectel_EC2x&EGxx&EM05_GNSS_AT_Commands_ Manual GNSS AT Commands Manual for EC25, EC21, EC20 R2.0, EC20 R2.
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LTE Module Series EG21-G Hardware Design CSD Circuit Switched Data CTS Clear To Send DC-HSPA+ Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air DL Downlink DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GNSS Globa
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LTE Module Series EG21-G Hardware Design MIMO Multiple Input Multiple Output MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PF Paging Frame PPP Point-to-Point Protocol QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SGMII Serial Gigabit Media Independent Interface SIM Subscribe
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LTE Module Series EG21-G Hardware Design (U)SIM (Universal )Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin
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LTE Module Series EG21-G Hardware Design 10 Appendix B GPRS Coding Schemes Table 40: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
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LTE Module Series EG21-G Hardware Design 11 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
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LTE Module Series EG21-G Hardware Design 14 4 4 NA 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 EG21-G_Hardware_Design 91 / 100
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LTE Module Series EG21-G Hardware Design 12 Appendix D EDGE Modulation and Coding Schemes Table 42: EDGE Modulation and Coding Schemes Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2: GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3: GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4: GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps MCS-3 GMSK A 14.
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LTE Module Series EG21-G Hardware Design 13 IC & FCC Requirement FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met: 1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.
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LTE Module Series EG21-G Hardware Design conditions that must be observed to ensure compliance with current FCC RF exposure guidelines. For portable devices, in addition to the conditions 3 through 6 described above, a separate approval is required to satisfy the SAR requirements of FCC Part 2.1093 If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations.
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LTE Module Series EG21-G Hardware Design IC Statement IRSS-GEN "This device complies with Industry Canada’s licence-exempt RSSs. Operation is subject to the following two conditions: (1) This device may not cause interference; and (2) This device must accept any interference, including interference that may cause undesired operation of the device." or "Le présent appareil est conforme aux CNR d’Industrie Canada applicables aux appareils radio exempts de licence.