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ManualsBrandsQuectel ManualsElectronicsLTE Module

AG35-Quecopen

Hardware Design

LTE Module Series

Rev. AG35-Quecopen_Hardware_Design_V1.3

Date: 2018-12-12

Status: Released

www.quectel.com

Summary of content (141 pages)

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AG35-Quecopen Hardware Design LTE Module Series Rev. AG35-Quecopen_Hardware_Design_V1.3 Date: 2018-12-12 Status: Released www.quectel.
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LTE Module Series AG35-Quecopen Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
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LTE Module Series AG35-Quecopen Hardware Design About the Document History Revision 1.0 Date Author Description 2017-10-19 Eden LIU/ Dominic GONG/ Jun WU Initial 1. 1.1 1.2 2018-03-19 2018-08-27 Eden LIU/ Dominic GONG Updated the variants and/or frequency bands of AG35-Quecopen in Table 1. 2. Changed pins 132 and 133 into RESERVED pins (Table 4, Table 8 and Figure 2). 3. Deleted SIM IC in Figure 1. 4. Updated transmitting power and GSM features in Table 2. 5.
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LTE Module Series AG35-Quecopen Hardware Design 3. Enabled SHDN_N, and added the description of the pin in Table 4 and Chapter 3.7.2.3. 4. Changed the name of pin 143 from OTG_PWR_EN to GPIO8 (Table 4). 5. Updated the description of alternate functions of multiplexing pins (Table 5). 6. Enabled the analog audio interface, and added the description of the interface in Table 4 and Chapter 3.12. 7. Enabled UART4 and UART5 interfaces (Chapter 3.11). 8. Added a note for I2C1 interface (Chapter 3.13). 9.
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LTE Module Series AG35-Quecopen Hardware Design 8. 9. 10. 11. 1.4 2019-02-01 Eden AG35-QuecOpen_Hardware_Design AG35-NA and AG35-J (Chapter 4.2). Updated the maximum clock frequency of SPI2 interface into 38MHz (Chapter 3.15). Updated current consumption values of the module (Chapter 6.4). Completed the RF output power values of the module (Chapter 6.5). Added the RF receiving sensitivity of AG35-E, AG35-NA and AG35-J (Chapter 6.6). 1. Updated the description of the notes (table 5).
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LTE Module Series AG35-Quecopen Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 5 Table Index ....................................................................................................................................
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LTE Module Series AG35-Quecopen Hardware Design 3.14.1. SDIO1 Interface ........................................................................................................... 64 3.14.2. SDIO2 Interface ........................................................................................................... 64 3.14.2.1. Reference Design for SD Card Application ....................................................... 65 3.14.2.2. Reference Design for eMMC Application ...................................
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LTE Module Series AG35-Quecopen Hardware Design 8.1. 8.2. 8.3. 9 10 11 12 Storage ................................................................................................................................. 126 Manufacturing and Soldering ................................................................................................ 127 Packaging ............................................................................................................................. 128 Appendix A References ..
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LTE Module Series AG35-Quecopen Hardware Design Table Index TABLE 1: FREQUENCY BANDS OF AG35-QUECOPEN MODULES.............................................................. 15 TABLE 2: KEY FEATURES OF AG35-QUECOPEN MODULES ...................................................................... 15 TABLE 3: I/O PARAMETERS DEFINITION ....................................................................................................... 23 TABLE 4: PIN DESCRIPTION .............................................
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LTE Module Series AG35-Quecopen Hardware Design TABLE 42: PIN DEFINITION OF THE RF ANTENNA INTERFACES ............................................................... 84 TABLE 43: AG35-CE OPERATING FREQUENCIES ........................................................................................ 84 TABLE 44: AG35-E OPERATING FREQUENCIES ........................................................................................... 85 TABLE 45: AG35-NA OPERATING FREQUENCIES .................................
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LTE Module Series AG35-Quecopen Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 20 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 22 FIGURE 3: SLEEP MODE CURRENT CONSUMPTION DIAGRAM ................................................................
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LTE Module Series AG35-Quecopen Hardware Design FIGURE 40: COPLANAR WAVEGUIDE DESIGN ON A 4-LAYER PCB (LAYER 4 AS REFERENCE GROUND) ................................................................................................................................................................... 90 FIGURE 41: REFERENCE CIRCUIT OF GNSS ANTENNA ............................................................................. 91 FIGURE 42: DIMENSIONS OF THE U.FL-R-SMT CONNECTOR (UNIT: MM) .......................
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LTE Module Series AG35-Quecopen Hardware Design 1 Introduction This document defines the AG35-Quecopen module and describes its air interface and hardware interface which are connected with customers’ applications. This document can help customers quickly understand module interface specifications, electrical and mechanical details, as well as other related information of the module.
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LTE Module Series AG35-Quecopen Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating AG35-Quecopen module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
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LTE Module Series AG35-Quecopen Hardware Design 2 Product Concept 2.1. General Description Quecopen® is an application solution where the module acts as a main processor. With the development of communication technology and the ever-changing market demands, more and more customers have realized the advantages of Quecopen® solution. Especially, its advantage in reducing the product cost is greatly valued by customers.
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LTE Module Series AG35-Quecopen Hardware Design Table 1: Frequency Bands of AG35-Quecopen Modules Network Type AG35-CE AG35-E AG35-NA AG35-LA* AG35-J* LTE-FDD (with Rx-diversity) B1/B3/ B5/B8 B1/B3/B5/ B7/B8/B20/ B28 B2/B4/B5/ B7/B12/B13/ B17/B28 1) B1/B2/B3/ B4/B5/B7/ B8/B28 B1/B3/B5/B8/ B9/B19/B21/ B28/ LTE-TDD (with Rx-diversity) B34/B38/ B39/B40/ B41 B38/B40 N/A N/A B41 WCDMA (with Rx-diversity) B1/B8 B1/B5/B8 B2/B4/B5 B1/B2/B3/ B4/B5/B8 B1/B3/B5/ B6/B8/B19 TD-SCDMA B34/B39 N/
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LTE Module Series AG35-Quecopen Hardware Design Transmitting Power Class 4 (33dBm±2dB) for GSM850 Class 4 (33dBm±2dB) for EGSM900 Class 1 (30dBm±2dB) for DCS1800 Class 1 (30dBm±2dB) for PCS1900 Class E2 (27dBm±3dB) for GSM850 8-PSK Class E2 (27dBm±3dB) for EGSM900 8-PSK Class E2 (26dBm±3dB) for DCS1800 8-PSK Class E2 (26dBm±3dB) for PCS1900 8-PSK Class 3 (24dBm+2/-1dB) for EVDO/CDMA BC0 Class 3 (24dBm+1/-3dB) for WCDMA bands Class 2 (24dBm+1/-3dB) for TD-SCDMA bands Class 3 (23dBm±2dB) for LTE-FDD bands C
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LTE Module Series AG35-Quecopen Hardware Design connections SMS Text and PDU modes Point to point MO and MT SMS cell broadcast SMS storage: ME by default (U)SIM Interface Support USIM/SIM card: 1.8V, 3.
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LTE Module Series AG35-Quecopen Hardware Design SPI Interfaces SDIO2: Compliant with SD 3.0 protocol Support eMMC and SD card Support master mode only Maximum clock frequency rate: 50MHz I2C Interfaces I2C1: Compliant with I2C specification version 5.0 Multi-master is not supported Used for codec configuration by default I2C2: Compliant with I2C specification version 5.
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LTE Module Series AG35-Quecopen Hardware Design 3. 4. tolerances. When the temperature returns to normal operation temperature levels, the module will meet 3GPP specifications again. 3) Within eCall temperature range, the emergency call function must be functional until the module is broken.
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LTE Module Series AG35-Quecopen Hardware Design Figure 1: Functional Diagram 2.4. Evaluation Board In order to help customers develop applications conveniently with AG35-Quecopen module, Quectel supplies the evaluation board (EVB), USB data cable, earphone, antenna and other peripherals to control or test the module. For more details, please refer to document [4].
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LTE Module Series AG35-Quecopen Hardware Design 3 Application Interfaces 3.1. General Description AG35-Quecopen is equipped with 299-pin LGA pads that can be connected to cellular application platform.
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298 89 90 196 92 91 RESERVED 93 95 94 197 96 198 199 98 97 RESERVED 99 101 100 200 103 102 201 202 104 105 107 106 203 108 204 205 110 109 ANT_MAIN RESERVED 111 206 112 113 114 207 208 116 115 ANT_GNSS 117 119 118 209 121 120 210 123 122 211 84 135 82 215 216 217 218 219 220 221 222 139 224 225 226 227 228 229 230 231 168 NET_STATUS ADC2 GND 233 234 235 236 237 238 239 240 72 147 149 242 243 245 244 246 247 248 249 PCM_OUT 68 PCM
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LTE Module Series AG35-Quecopen Hardware Design 3. 4. GND pins 215~299 should be connected to ground in the design. Keep all RESERVED pins and unused pins unconnected. 3.3. Pin Description The following tables show the pin definition of AG35-Quecopen module, as well as the alternate functions of multiplexing pins.
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LTE Module Series AG35-Quecopen Hardware Design Table 4: Pin Description Power Supply Pin Name VBAT_BB VBAT_RF Pin No. 155, 156 85, 86, 87, 88 VDD_EXT 168 GND 10, 13, 16, 17, 30, 31, 35, 39, 44, 45, 54, 55, 63, 64, 69, 70, 75, 76, 81~84, 89~94, 96~100, 102~106, 108~112, 114, 116~118, 120~126, 128~131, 142, 148, 153, 154, 157, 158, 167, 174, 177, 178, 181, 184, 187, 191, 196~299 I/O Description DC Characteristics Comment PI Power supply for module’s baseband part Vmax=4.3V Vmin=3.3V Vnorm=3.
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LTE Module Series AG35-Quecopen Hardware Design VILmax=0.5V RESET_N SHDN_N 1 176 DI Reset the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V DI Emergency shutdown for the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V I/O Description DC Characteristics diode drop in the Qualcomm chipset. Internally pulled up to 1.8V. Active low. (U)SIM Interface Pin Name USIM_GND USIM_ PRESENCE Pin No. 25 Connect to ground of (U)SIM card connector.
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LTE Module Series AG35-Quecopen Hardware Design VOLmax=0.45V VOHmin=1.35V For 3.0V (U)SIM: VILmax=1.0V VIHmin=1.95V VOLmax=0.45V VOHmin=2.55V USB Interface Pin Name USB_VBUS USB_DM USB_DP Pin No. 32 33 34 I/O Description DC Characteristics Comment PI USB connection detection Vmax=5.25V Vmin=3.0V Vnorm=5.0V Maximum current: 1mA. IO USB differential data bus (-) Compliant with USB 2.0 standard specification. IO USB differential data bus (+) Compliant with USB 2.0 standard specification.
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LTE Module Series AG35-Quecopen Hardware Design VIHmax=2.0V UART1_TXD 60 1.8V power domain. If unused, keep it open. DO Transmit data VOLmax=0.45V VOHmin=1.35V I/O Description DC Characteristics Comment Transmit data VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DTE clear to send VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Receive data VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open.
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LTE Module Series AG35-Quecopen Hardware Design ADC2 172 AI General purpose analog to digital converter interface Voltage range: 0.1V to 1.7V If unused, keep it open. DC Characteristics Comment Audio Interface (Optional) Pin Name Pin No. I/O Description SPK2_P 132 AO Earphone analog output 2 (+) If unused, keep it open. SPK2_N 133 AO Earphone analog output 2 (-) If unused, keep it open. SPK1_P 134 AO Earphone analog output 1 (+) If unused, keep it open.
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LTE Module Series AG35-Quecopen Hardware Design PCM_CLK PCM_OUT MCLK 67 68 152 IO DO DO PCM clock VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. PCM data output VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Output 12.288MHZ VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open.
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LTE Module Series AG35-Quecopen Hardware Design Pin Name VDD_SDIO Pin No. 46 I/O Description PO SD card application: SDIO pull up power source. DC Characteristics Comment IOmax=50mA 1.8V/2.85V configurable power output. If unused, keep it open. eMMC application: Keep it open when used for eMMC.
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LTE Module Series AG35-Quecopen Hardware Design Pin Name SPI_MOSI Pin No. 77 I/O Description DC Characteristics Comment DO SPI master out slave in VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. SPI_MISO 78 DI SPI master in slave out SPI_CS_N 79 DO SPI chip selection VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. DO SPI serial clock VOLmax=0.
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LTE Module Series AG35-Quecopen Hardware Design VOHmin=2.55V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. DC Characteristics Comment 9 DI Ethernet PHY interrupt Pin Name Pin No. I/O Description SGMII_RX_M 11 AI SGMII receiving (-) If unused, keep it open. SGMII_RX_P 12 AI SGMII receiving (+) If unused, keep it open. SGMII_TX_P 14 AO SGMII transmission (+) If unused, keep it open.
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LTE Module Series AG35-Quecopen Hardware Design VIHmin=1.2V VIHmax=2.0V WLAN SDIO data bus (bit 2) VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. WLAN SDIO data bus (bit 3) VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. DI Wake up the module via WLAN VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. Active low. If unused, keep it open.
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LTE Module Series AG35-Quecopen Hardware Design GPIO Pins Pin Name Pin No. I/O GPIO1 59 IO GPIO2 61 IO GPIO3 62 IO GPIO4 144 IO GPIO5 147 IO GPIO6 150 IO GPIO7 159 IO GPIO8 143 IO Description DC Characteristics Comment General purpose input/output interface VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep the pins open. DC Characteristics Comment BT Control Interface Pin Name Pin No.
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LTE Module Series AG35-QuecOpen Hardware Design The following table lists the multiplexing pins and their respective alternate functions of AG35-Quecopen. Table 5: Alternate Functions of Multiplexing Pins Pin Name Pin No.
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LTE Module Series AG35-QuecOpen Hardware Design PM_ENABLE 5 PM_ENABLE PMU_ GPIO_03 -- -- B-PD,L Low level NO SDC1_CMD 18 SDC1_CMD GPIO_17 UART_RXD_ BLSP4 -- B-PD,L Low level YES SDC1_CLK 19 SDC1_CLK GPIO_16 UART_TXD_ BLSP4 -- B-NP,L Low level YES SDC1_DATA0 20 SDC1_DATA0 GPIO_15 UART_CTS_ BLSP1 SPI_CLK_ BLSP1 B-PD,L Low level NO SDC1_DATA1 21 SDC1_DATA1 GPIO_14 UART_RTS_ BLSP1 SPI_CS_N _BLSP1 B-PD,L Low level NO SDC1_DATA2 22 SDC1_DATA2 GPIO_13 UART_RXD_ BLS
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LTE Module Series AG35-QuecOpen Hardware Design UART1_RXD 58 UART_RXD_ BLSP3 GPIO_1 SPI_MISO_B LSP3 -- B-PD,L Low level YES UART1_TXD 60 UART_TXD_ BLSP3 GPIO_0 SPI_MOSI_B LSP3 -- B-PD,L Low level NO PCM_SYNC 65 PCM_SYNC GPIO_79 -- -- B-PD,L Low level YES PCM_IN 66 PCM_IN GPIO_76 -- -- B-PD,L Low level YES PCM_CLK 67 PCM_CLK GPIO_78 -- -- B-PD,L Low level NO PCM_OUT 68 PCM_OUT GPIO_77 -- -- B-PD,L Low level NO I2C2_SDA 73 I2C_SDA_ BLSP2 GPIO_6 -- --
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LTE Module Series AG35-QuecOpen Hardware Design UART2_CTS 164 UART_CTS_B LSP5 GPIO_11 SPI_CLK_BL SP5 -- B-PU,L High level YES UART2_RXD 165 UART_RXD_ BLSP5 GPIO_9 SPI_MISO_B LSP5 -- B-PD,L Low level YES UART2_RTS 166 UART_RTS_B LSP5 GPIO_10 SPI_CS_N_B LSP5 -- B-PD,L Low level NO WLAN_SLP_ CLK 169 WLAN_SLP_ CLK PMU_ GPIO_06 -- -- B-PD,L Low level NO NET_STATUS 170 PMU_GPIO_0 1 NET_STA -TUS -- B-PD,L Low level NO NOTES 1.
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LTE Module Series AG35-QuecOpen Hardware Design Table 6: Pull-up/Pull-down Resistance of GPIOs Symbol Description Pin number Min Typ.
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LTE Module Series AG35-QuecOpen Hardware Design 3.4. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters. Table 7: Overview of Operating Modes Mode Normal Operation Details Idle Software is active. The module has registered on the network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network setting and data transfer rate.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 3: Sleep Mode Current Consumption Diagram NOTE DRX cycle index values are broadcasted by the wireless network. 3.5.1.1. USB Application with USB Remote Wakeup Function If the host supports USB suspend/resume and remote wakeup function, the following three preconditions must be met to let the module enter into the sleep mode.    Use sleep & wakeup API to enable the sleep mode.
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LTE Module Series AG35-QuecOpen Hardware Design   Sending data to AG35-Quecopen through USB will wake up the module. When AG35-Quecopen has URC to report, the module will send remote wake-up signals via USB bus so as to wake up the host. 3.5.1.2. USB Application without USB Remote Wakeup Function If the host supports USB suspend/resume, but does not support remote wake-up function, it needs to be woken up via the module’s GPIO. There are three preconditions to let the module enter into the sleep mode.
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LTE Module Series AG35-QuecOpen Hardware Design  status. Disconnect USB_VBUS. The following figure shows the connection between the module and the host. Figure 6: Sleep Mode Application without Suspend Function Switching on the power switch to supply power to USB_VBUS will wake up the module. NOTE Please pay attention to the level match shown in dotted line between the module and the host. Refer to document [1] for more details about the module’s power management application. 3.5.2.
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LTE Module Series AG35-QuecOpen Hardware Design 3.6. Power Supply 3.6.1. Power Supply Pins AG35-Quecopen provides six VBAT pins for connection with an external power supply. There are two separate voltage domains for VBAT.   Four VBAT_RF pins for module’s RF part Two VBAT_BB pins for module’s baseband part The following table shows the details of VBAT pins and ground pins. Table 8: VBAT and GND Pins Pin Name Pin No. Description Min. Typ. Max.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 7: Power Supply Limits during Burst Transmission To decrease voltage drop, a bypass capacitor of about 100µF with low ESR should be used, and a multi-layer ceramic chip capacitor (MLCC) array should also be reserved due to its low ESR. It is recommended to use three ceramic capacitors (100nF, 33pF, 10pF) for composing the MLCC array, and place these capacitors close to VBAT pins.
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LTE Module Series AG35-QuecOpen Hardware Design (VBAT), a buck converter is preferred to be used as the power supply. The following figure shows a reference design for +12V/+24V input power source. The designed output for the power supply is about 3.8V and the maximum rated current is 5A. Figure 9: Reference Circuit of Power Supply 3.6.4. Monitor the Power Supply AT+CBC command can be used to monitor the VBAT_BB voltage value. Please refer to document [2] for more details. 3.7.
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LTE Module Series AG35-QuecOpen Hardware Design After STATUS pin (require external pull-up) outputting a low level, PWRKEY pin can be released. A simple reference circuit is illustrated in the following figure. Figure 10: Turn on the Module Using Driving Circuit Another way to control the PWRKEY is using a button directly. When pressing the key, electrostatic strike may generate from the finger. Therefore, a TVS component is indispensable to be placed nearby the button for ESD protection.
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LTE Module Series AG35-QuecOpen Hardware Design The turn on scenario is illustrated in the following figure. Figure 12: Timing of Turning on Module NOTES 1. 2. Please make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than 30ms. It is recommended to use an external OD/OC circuit to control the PWRKEY pin. 3.7.2.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 13: Timing of Turning off Module 3.7.2.2. Turn off Module Using AT Command or API Interface It is also a safe way to use AT+QPOWD command or API interface to turn off the module, which is similar to turning off the module via PWRKEY Pin. Please refer to document [2] and [3] for details about the AT command and API function, respectively. NOTES 1. 2.
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LTE Module Series AG35-QuecOpen Hardware Design Table 10: Pin Definition of SHDN_N Pin Name SHDN_N Pin No. 176 Description DC Characteristics Emergency shutdown for the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Comment Driving the SHDN_N pin to a low level voltage and then releasing it will make the module shut down unconditionally. The shut-down scenario is illustrated in the following figure.
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LTE Module Series AG35-QuecOpen Hardware Design 2. an external OD circuit to control the SHDN_N pin. Never pull up SHDN_N pin. 3.8. Reset the Module The RESET_N can be used to reset the module. The module can be reset by driving the RESET_N to a low level voltage for 150~460ms. As the RESET_N pin is sensitive to interference, the routing trace on the interface board of the module is recommended to be as short as possible and totally ground shielded.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 17: Reference Circuit of RESET_N by Using Button The reset scenario is illustrated in the following figure. Figure 18: Timing of Resetting Module NOTES 1. 2. Use RESET_N only when turning off the module by AT command, API interface and PWRKEY pin all failed. Please assure that there is no large capacitance on PWRKEY and RESET_N pins. 3.9. (U)SIM Interface The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Both 1.8V and 3.
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LTE Module Series AG35-QuecOpen Hardware Design Table 12: Pin Definition of (U)SIM Interface Pin Name Pin No. I/O Description Comment Either 1.8V or 3.0V is supported by the module automatically.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 20: Reference Circuit of (U)SIM Interface with a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in customers’ applications, please follow the criteria below in the (U)SIM circuit design:       Keep the placement of (U)SIM card connector as close to the module as possible. Keep the trace length as less than 200mm as possible. Keep (U)SIM card signals away from RF and VBAT traces.
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LTE Module Series AG35-QuecOpen Hardware Design 3.10. USB Interface AG35-Quecopen contains one integrated Universal Serial Bus (USB) interface which complies with the USB 2.0 specification and supports high-speed (480Mbps) and full-speed (12Mbps) modes. The USB interface is used for AT command communication, data transmission, GNSS NMEA sentences output, software debugging, firmware upgrade and voice over USB*. The following table shows the pin definition of USB interface.
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LTE Module Series AG35-QuecOpen Hardware Design In order to ensure signal integrity of USB data lines, components R1, R2 and L1 must be placed close to the module, and also these resistors should be placed close to each other. The extra stubs of trace must be as short as possible. The following principles should be complied with when design the USB interface, so as to meet USB 2.0 specification.     It is important to route the USB signal traces as differential pairs with total grounding.
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LTE Module Series AG35-QuecOpen Hardware Design Table 14: Pin Definition of UART1 Interface Pin Name Pin No. I/O Description Comment UART1_CTS 56 DO DTE clear to send 1.8V power domain UART1_RTS 57 DI DTE request to send 1.8V power domain UART1_RXD 58 DI Receive data 1.8V power domain UART1_TXD 60 DO Transmit data 1.8V power domain Table 15: Pin Definition of UART2 Interface Function Pin Name Pin No.
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LTE Module Series AG35-QuecOpen Hardware Design Table 17: Pin Definition of UART4 Interface (Multiplexed from SDIO1) Function Pin Name Pin No.
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LTE Module Series AG35-QuecOpen Hardware Design Table 20: Logic Levels of Digital I/O Parameter Min. Max. Unit VIL -0.3 0.6 V VIH 1.2 2.0 V VOL 0 0.45 V VOH 1.35 1.8 V The module provides 1.8V UART interfaces. A level translator should be used if customers’ application is equipped with a 3.3V UART interface. A level translator TXS0104E-Q1 provided by Texas Instruments (please visit http://www.ti.com for more information) is recommended. The following figure shows a reference design.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 23: Reference Circuit with Transistor Circuit NOTE Transistor circuit solution is not suitable for applications with high baud rates exceeding 460Kbps. 3.12. Audio Interface (Optional) AG35-Quecopen is designed with an optional built-in audio codec to enable analog audio function. The following table shows the pin definition of analog audio interface. Table 21: Pin Definition of Analog Audio Interface Pin Name Pin No.
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LTE Module Series AG35-QuecOpen Hardware Design MIC2_N 137 AI Microphone analog input 2 (-) MIC2_P 138 AI Microphone analog input 2 (+) MIC1_N 139 AI Microphone analog input 1 (-) MIC1_P 140 AI Microphone analog input 1 (+) AGND 141 Analog ground NOTES 1. The built-in codec uses the same signals as the module’s PCM interface (pins 65~68) for external digital audio design.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 24: Primary Mode Timing Figure 25: Auxiliary Mode Timing The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio codec design.
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LTE Module Series AG35-QuecOpen Hardware Design Table 22: Pin Definition of PCM Interface Pin Name Pin No. I/O Description Comment PCM_SYNC 65 IO PCM data frame sync signal 1.8V power domain PCM_IN 66 DI PCM data input 1.8V power domain PCM_CLK 67 IO PCM data bit clock 1.8V power domain PCM_OUT 68 DO PCM data output 1.8V power domain MCLK 152 DO Output 12.288MHZ 1.8V power domain Table 23: Pin Definition of I2C Interfaces Pin Name Pin No.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 26: Reference Circuit of PCM Application with Audio Codec NOTES 1. 2. It is recommended to reserve an RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for PCM_CLK. AG35-Quecopen works as a master device pertaining to I2C interface. 3.14. SDIO Interfaces AG35-Quecopen provides two SDIO interfaces which support SD 3.0 protocol. 3.14.1. SDIO1 Interface SDIO1 interface is used for WLAN function. More details are provided in Chapter 3.17. 3.14.
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LTE Module Series AG35-QuecOpen Hardware Design Table 24: Pin Definition of SDIO2 Interface Pin Name Pin No. I/O Description Comment 1.8V/2.85V configurable output. SDIO pull up power source for SD card. Keep it open for eMMC.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 27: Reference Circuit Design for SD Card Application Please follow the principles below in the SD card circuit design:         The voltage range of SD card power supply VDD_3V is 2.7~3.6V and a sufficient current up to 0.8A should be provided. As the maximum output current of VDD_SDIO is 50mA which can only be used for SDIO pull-up resistors, an externally power supply is needed for SD card.
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LTE Module Series AG35-QuecOpen Hardware Design 3.14.2.2. Reference Design for eMMC Application Figure 28: Reference Circuit Design for eMMC Application Please follow the principles below in eMMC circuit design:       To avoid jitter of bus, it is recommended to reserve resistors R7~R11 for pulling up SDIOs to VDD_1.8V. Resistors R7~R10 are not mounted by default, and the recommended resistor value is 10~100kΩ.
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LTE Module Series AG35-QuecOpen Hardware Design 3.15. SPI Interfaces AG35-Quecopen provides three SPI interfaces (two of them multiplexed from UARTs) supporting only master mode. The maximum clock frequency of SPI1 and SPI3 is up to 50MHz, while that of SPI2 is 38MHz. The following tables show the pin definition of SPI interfaces. Table 25: Pin Definition of SPI1 Interface Pin Name Pin No. I/O Description Comment SPI_MOSI 77 DO SPI master out slave in 1.8V power domain. If unused, keep it open.
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LTE Module Series AG35-QuecOpen Hardware Design UART2_CTS 164 DO UART_CTS_BLSP5 GPIO_11 SPI_CLK_BLSP5 UART2_RXD 165 DI UART_RXD_BLSP5 GPIO_9 SPI_MISO_BLSP5 UART2_RTS 166 DI UART_RTS_BLSP5 GPIO_10 SPI_CS_N_BLSP5 NOTE For more details about non-default alternate functions for the pins mentioned in the above table, please refer to corresponding chapters. The following figure shows the timing relationship of SPI interfaces. The related parameters of SPI timing are shown in the table below.
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LTE Module Series AG35-QuecOpen Hardware Design t(mis) SPI master data input setup time 5.0 - - ns t(mih) SPI master data input hold time 1.0 - - ns NOTE The module provides 1.8V SPI interfaces. A level translator should be used between the module and the host if customers’ application is equipped with a 3.3V processor or device interface. 3.16. SGMII Interface (Optional) AG35-Quecopen includes an integrated Ethernet MAC with an SGMII interface and two management interfaces.
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LTE Module Series AG35-QuecOpen Hardware Design SGMII Signal Part SGMII_TX_M 15 AO SGMII transmission (-) Connect with a 0.1uF capacitor, close to the PHY side. SGMII_TX_P 14 AO SGMII transmission (+) Connect with a 0.1uF capacitor, close to the PHY side. SGMII_RX_P 12 AI SGMII receiving (+) SGMII_RX_M 11 AI SGMII receiving (-) The following figure shows the simplified block diagram for Ethernet application.
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LTE Module Series AG35-QuecOpen Hardware Design In order to enhance the reliability and availability of customers’ application, please follow the criteria below in the Ethernet PHY circuit design:      Keep SGMII data and control signals away from RF and VBAT traces. Keep the maximum trace length less than 10 inches and keep the intra-pair length matching less than 20 mils. The differential impedance of SGMII data trace is 100Ω±10%.
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LTE Module Series AG35-QuecOpen Hardware Design WLAN_EN 149 DO WLAN_EN WLAN_WAKE 1) 160 DI WLAN_WAKE WLAN_SLP_ CLK 169 DO WLAN_SLP_ CLK GPIO_54 Coexistence Interface COEX_UART_ TX 145 DO COEX_UART_ TX COEX_UART_ RX/ USB_BOOT 146 DI COEX_UART_ RX BT_EN* 3 DO BT_EN* UART2_TXD 163 DO UART_TXD_ BLSP5 GPIO_8 SPI_MOSI_ BLSP5 UART2_CTS 164 DO UART_CTS_ BLSP5 GPIO_11 SPI_CLK_ BLSP5 UART2_RXD 165 DI UART_RXD_ BLSP5 GPIO_9 SPI_MISO_ BLSP5 UART2_RTS 166 DI UART_RTS_ BLSP5
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LTE Module Series AG35-QuecOpen Hardware Design The following figure shows a reference design for the connection between wireless connectivity interfaces and Quectel AF20 module. Figure 32: Reference Circuit for Connection with AF20 Module NOTES 1. 2. 3. 4. AF20 module can only be used as a slave device. When BT function is enabled on AG35-Quecopen module, PCM_SYNC and PCM_CLK pins are only used to output signals.
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LTE Module Series AG35-QuecOpen Hardware Design 3.17.1. WLAN Interface AG35-Quecopen provides SDIO1 interface and a control interface for WLAN design. The WLAN interface (SDIO1 interface) supports the following modes:  Single data rate (SDR) mode (up to 208MHz)  Double data rate (DDR) mode (up to 50MHz) As SDIO signals are very high-speed signals, in order to ensure the SDIO1 interface design corresponds with the SDIO 3.
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LTE Module Series AG35-QuecOpen Hardware Design In order to improve the accuracy of ADC, the traces of ADC interfaces should be surrounded by ground. Table 31: Pin Definition of ADC Interfaces Pin Name Pin No. Description ADC2 172 General purpose analog to digital converter interface ADC1 175 General purpose analog to digital converter interface ADC0 173 General purpose analog to digital converter interface The following table describes the characteristic of ADC interfaces.
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LTE Module Series AG35-QuecOpen Hardware Design Table 33: Pin Definition of the Network Status Indicator (NET_STATUS) Pin Name Pin No. I/O Description Comment NET_STATUS 170 DO Indicate the module’s network activity status. 1.
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LTE Module Series AG35-QuecOpen Hardware Design Table 35: Pin Definition of STATUS Pin Name STATUS Pin No. 171 I/O Description Comment OD Indicate the module’s operation status Require external pull-up The following figure shows different circuit designs of STATUS, and customers can choose either one according to specific application demands. Figure 34: Reference Circuits of STATUS NOTES 1. 2.
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LTE Module Series AG35-QuecOpen Hardware Design Table 36: Pin Definition of USB_BOOT Interface Pin Name COEX_ UART_RX/ USB_BOOT Pin No. 146 I/O Description Comment DI Force the module to enter into emergency download mode 1.8V power domain. Active high. If unused, keep it open. The following figure shows a reference circuit of USB_BOOT interface. Figure 35: Reference Circuit of USB_BOOT Interface 3.22.
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LTE Module Series AG35-QuecOpen Hardware Design 4 GNSS Receiver 4.1. General Description AG35-Quecopen includes a fully integrated global navigation satellite system solution that supports Gen8C-Lite of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). AG35-Quecopen supports standard NMEA-0183 protocol, and outputs NMEA sentences at 10Hz data update rate via USB interface by default. By default, GNSS engine of the module is switched off. It has to be switched on via AT command.
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LTE Module Series AG35-QuecOpen Hardware Design Autonomous 2.5 s XTRA enabled 1.8 s Autonomous @open sky < 2.5 m Description Conditions Typ. Unit Cold start Autonomous TBD dBm Reacquisition Autonomous TBD dBm Tracking Autonomous TBD dBm Autonomous TBD s XTRA enabled TBD s Autonomous TBD s XTRA enabled TBD s Autonomous TBD s XTRA enabled TBD s Autonomous @open sky TBD m Description Conditions Typ. Unit Cold start Autonomous -146.
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LTE Module Series AG35-QuecOpen Hardware Design @open sky XTRA enabled 2.2 s Autonomous 2.5 s XTRA enabled 1.8 s Autonomous @open sky < 2.5 m Description Conditions Typ. Unit Cold start Autonomous TBD dBm Reacquisition Autonomous TBD dBm Tracking Autonomous TBD dBm Autonomous TBD s XTRA enabled TBD s Autonomous TBD s XTRA enabled TBD s Autonomous TBD s XTRA enabled TBD s Autonomous @open sky TBD m Description Conditions Typ.
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LTE Module Series AG35-QuecOpen Hardware Design Warm start @open sky Hot start @open sky Accuracy (GNSS) CEP-50 Autonomous 26 s XTRA enabled 2.2 s Autonomous 2.5 s XTRA enabled 1.8 s Autonomous @open sky < 2.5 m NOTES 1. 2. 3. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes.
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LTE Module Series AG35-QuecOpen Hardware Design 5 Antenna Interfaces AG35-Quecopen include a main antenna interface, an Rx-diversity antenna interface which is used to resist the fall of signals caused by high speed movement and multipath effect, and a GNSS antenna interface. The antenna ports have an impedance of 50Ω. 5.1. Main/Rx-diversity Antenna Interface 5.1.1. Pin Definition The pin definition of main antenna and Rx-diversity antenna interfaces are shown below.
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LTE Module Series AG35-QuecOpen Hardware Design TD-SCDMA B39 1880~1920 1880~1920 MHz LTE-FDD B1 1920~1980 2110~2170 MHz LTE-FDD B3 1710~1785 1805~1880 MHz LTE-FDD B5 824~849 869~894 MHz LTE-FDD B8 880~915 925~960 MHz LTE-TDD B34 2010~2025 2010~2025 MHz LTE-TDD B38 2570~2620 2570~2620 MHz LTE-TDD B39 1880~1920 1880~1920 MHz LTE-TDD B40 2300~2400 2300~2400 MHz LTE-TDD B41 2555~2655 2555~2655 MHz Table 44: AG35-E Operating Frequencies 3GPP Band Transmit Receive Unit
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LTE Module Series AG35-QuecOpen Hardware Design LTE-TDD B38 2570~2620 2570~2620 MHz LTE-TDD B40 2300~2400 2300~2400 MHz Table 45: AG35-NA Operating Frequencies 3GPP Band Transmit Receive Unit GSM850 824~849 869~894 MHz PCS1900 1850~1910 1930~1990 MHz WCDMA B2 1850~1910 1930~1990 MHz WCDMA B4 1710~1755 2110~2155 MHz WCDMA B5 824~849 869~894 MHz LTE-FDD B2 1850~1910 1930~1990 MHz LTE-FDD B4 1710~1755 2110~2155 MHz LTE-FDD B5 824~849 869~894 MHz LTE-FDD B7 2500~257
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LTE Module Series AG35-QuecOpen Hardware Design WCDMA B2 1850~1910 1930~1990 MHz WCDMA B3 1710~1785 1805~1880 MHz WCDMA B4 1710~1755 2110~2155 MHz WCDMA B5 824~849 869~894 MHz WCDMA B8 880~915 925~960 MHz LTE-FDD B1 1920~1980 2110~2170 MHz LTE-FDD B2 1850~1910 1930~1990 MHz LTE-FDD B3 1710~1785 1805~1880 MHz LTE-FDD B4 1710~1755 2110~2155 MHz LTE-FDD B5 824~849 869~894 MHz LTE-FDD B7 2500~2570 2620~2690 MHz LTE-FDD B8 880~915 925~960 MHz LTE FDD B28 703~748
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LTE Module Series AG35-QuecOpen Hardware Design LTE-FDD B8 880~915 925~960 MHz LTE-FDD B9 1749.9~1784.8 1844.9~1879.8 MHz LTE-FDD B19 830~845 875~890 MHz LTE-FDD B21 1747.9~1462.8 1495.9~1510.8 MHz LTE FDD B28 703~748 758~803 MHz LTE TDD B41 2535~2655 2535~2655 MHz NOTE 1) EVDO/CDMA BC0 for AG35-CE and LTE-FDD B28 for AG35-NA are optional. 5.1.3. Reference Design of RF Antenna Interface A reference design of main and Rx-diversity antenna interfaces is shown as below.
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LTE Module Series AG35-QuecOpen Hardware Design NOTES 1. Keep a proper distance between the main antenna and the Rx-diversity antenna to improve receiving sensitivity. 2. ANT_DIV function is enabled by default. AT+QCFG="diversity",0 command can be used to disable receive diversity. Please refer to document [2] for details. 5.1.4. Reference Design of RF Layout For user’s PCB, the characteristic impedance of all RF traces should be controlled to 50Ω.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 39: Coplanar Waveguide Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 40: Coplanar Waveguide Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design:      Use an impedance simulation tool to accurately control the characteristic impedance of RF traces to 50Ω.
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LTE Module Series AG35-QuecOpen Hardware Design 5.2. GNSS Antenna Interface The following tables show the pin definition and frequency specification of GNSS antenna interface. Table 48: Pin Definition of GNSS Antenna Interface Pin Name Pin No. I/O Description Comment ANT_GNSS 119 AI GNSS antenna interface 50Ω impedance Table 49: GNSS Frequency Type Frequency Unit GPS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz Galileo 1575.42±2.046 MHz BeiDou 1561.098±2.046 MHz QZSS 1575.
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LTE Module Series AG35-QuecOpen Hardware Design NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement. If the module is designed with a passive antenna, then the VDD circuit is not needed. 5.3. Antenna Installation 5.3.1. Antenna Requirements The following table shows the requirements on main antenna, Rx-diversity antenna and GNSS antenna.
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LTE Module Series AG35-QuecOpen Hardware Design 5.3.2. Recommended RF Connector for Antenna Installation If RF connector is used for antenna connection, it is recommended to use the U.FL-R-SMT connector provided by HIROSE. Figure 42: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connector listed in the following figure can be used to match the U.FL-R-SMT. Figure 43: Mechanicals of U.
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LTE Module Series AG35-QuecOpen Hardware Design The following figure describes the space factor of mated connector. Figure 44: Space Factor of Mated Connector (Unit: mm) For more details, please visit https://www.hirose.com.
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LTE Module Series AG35-QuecOpen Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 51: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 0.8 A Peak Current of VBAT_RF 0 1.8 A Voltage at Digital Pins -0.3 2.
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LTE Module Series AG35-QuecOpen Hardware Design 6.2. Power Supply Ratings Table 52: Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT_BB and VBAT_RF The actual input voltages must stay between the minimum and maximum values. 3.3 3.8 4.3 V Voltage drop during burst transmission Maximum power control level on EGSM900. 400 mV IVBAT Peak supply current (during transmission slot) Maximum power control level on EGSM900. 1.8 2.
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LTE Module Series AG35-QuecOpen Hardware Design 3. tolerances. When the temperature returns to normal operation temperature levels, the module will meet 3GPP specifications again. 3) Within eCall temperature range, the emergency call function must be functional until the module is broken.
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LTE Module Series AG35-QuecOpen Hardware Design GPRS data transfer (GNSS OFF) EDGE data transfer (GNSS OFF) EVDO/CDMA data transfer (GNSS OFF) TD-SCDMA data transfer (GNSS OFF) WCDMA data transfer (GNSS OFF) LTE-TDD PF=64 (USB connected) 35.0 mA LTE-TDD PF=64 (USB disconnected) 23.0 mA EGSM900 4DL/1UL @32.66dBm 249.2 mA EGSM900 3DL/2UL @32.51dBm 421.6 mA EGSM900 2DL/3UL @30.65dBm 495.0 mA EGSM900 1DL/4UL @29.37dBm 568.9 mA DCS1800 4DL/1UL @29.21dBm 174.1 mA DCS1800 3DL/2UL @29.
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LTE Module Series AG35-QuecOpen Hardware Design LTE data transfer (GNSS OFF) LTE-FDD B1 @23.01dBm 698.07 mA LTE-FDD B3 @23.24dBm 708.78 mA LTE-FDD B5 @23.28dBm 629.16 mA LTE-FDD B8 @23.27dBm 597.21 mA LTE-TDD B34 @22.73dBm 334.99 mA LTE-TDD B38 @22.85dBm 430.39 mA LTE-TDD B39 @22.97dBm 330.62 mA LTE-TDD B40 @22.94dBm 405.78 mA LTE-TDD B41 @22.91dBm 456.63 mA EGSM900, PCL=5 @32.3dBm 230.4 mA EGSM900, PCL=12 @19.3dBm 103.2 mA EGSM900, PCL=19 @5.3dBm 73.
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LTE Module Series AG35-QuecOpen Hardware Design GSM DRX=9 (USB disconnected) 1.6 mA WCDMA PF=128 (USB disconnected) 1.8 mA WCDMA PF=512 (USB disconnected) 1.5 mA LTE-FDD PF=128 (USB disconnected) 2.1 mA LTE-FDD PF=256 (USB disconnected) 1.8 mA LTE-TDD PF=128 (USB disconnected) 2.0 mA LTE-TDD PF=256 (USB disconnected) 1.7 mA GSM DRX=5 (USB connected) 17.
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LTE Module Series AG35-QuecOpen Hardware Design WCDMA data transfer (GNSS OFF) LTE data transfer (GNSS OFF) GSM voice call EGSM900 2DL/3UL @26.9dBm 331 mA EGSM900 1DL/4UL @25.3dBm 385 mA DCS1800 4DL/1UL @26.2dBm 150 mA DCS1800 3DL/2UL @26dBm 232 mA DCS1800 2DL/3UL @25dBm 307 mA DCS1800 1DL/4UL @24.6dBm 386 mA WCDMA B1 HSDPA @22.2dBm 552 mA WCDMA B5 HSDPA @22.8dBm 435 mA WCDMA B8 HSDPA @22.2dBm 495 mA WCDMA B1 HSUPA @21.9dBm 569 mA WCDMA B5 HSUPA @22.
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LTE Module Series AG35-QuecOpen Hardware Design WCDMA voice call DCS1800 @PCL=0 177 mA DCS1800 @PCL=7 128 mA DCS1800 @PCL=15 109 mA WCDMA B1 (max power) @23.07dBm 640 mA WCDMA B5 (max power) @23.24dBm 450 mA WCDMA B8 (max power) @23.1dBm 550 mA Table 56: AG35-NA Current Consumption Parameter Description Conditions Typ. Unit OFF state Power down 20 uA AT+CFUN=0 (USB disconnected) 1.2 mA GSM DRX=2 (USB disconnected) 2.3 mA GSM DRX=9 (USB disconnected) 1.
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LTE Module Series AG35-QuecOpen Hardware Design EDGE data transfer (GNSS OFF) WCDMA data transfer (GNSS OFF) LTE data transfer (GNSS OFF) PCS1900 4DL/1UL @29.21dBm 185 mA PCS1900 3DL/2UL @29.03dBm 296 mA PCS1900 2DL/3UL @28.95dBm 390 mA PCS1900 1DL/4UL @28.81dBm 480 mA GSM850 4DL/1UL @27.02dBm 160 mA GSM850 3DL/2UL @27.05dBm 265 mA GSM850 2DL/3UL @26.82dBm 355 mA GSM850 1DL/4UL @26.69dBm 456 mA PCS1900 4DL/1UL @25.21dBm 155 mA PCS1900 3DL/2UL @25.
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LTE Module Series AG35-QuecOpen Hardware Design LTE-FDD B17(max power) @23.2dBm 670 mA LTE-FDD B28A 1) (max power) @23.2dBm 240 mA LTE-FDD B28B 1) (max power) @23.2dBm 105 mA GSM850 @PCL=5 80 mA GSM850 @PCL=12 190 mA GSM850 @PCL=19 110 mA PCS1900 @PCL=0 90 mA PCS1900 @PCL=7 590 mA PCS1900 @PCL=15 595 mA WCDMA B2 (max power) @22.96dBm 580 mA WCDMA B4 (max power) @22.96dBm 560 mA WCDMA B5 (max power) @23.
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LTE Module Series AG35-QuecOpen Hardware Design GPRS data transfer (GNSS OFF) EDGE data transfer (GNSS OFF) WCDMA PF=64 (USB connected) TBD mA WCDMA PF=64 (USB disconnected) TBD mA LTE-FDD PF=64 (USB connected) TBD mA LTE-FDD PF=64 (USB disconnected) TBD mA GSM850 4DL/1UL @32.66dBm TBD mA GSM850 3DL/2UL @32.51dBm TBD mA GSM850 2DL/3UL @30.65dBm TBD mA GSM850 1DL/4UL @29.37dBm TBD mA EGSM900 4DL/1UL @32.66dBm TBD mA EGSM900 3DL/2UL @32.51dBm TBD mA EGSM900 2DL/3UL @30.
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LTE Module Series AG35-QuecOpen Hardware Design WCDMA data transfer (GNSS OFF) LTE data transfer (GNSS OFF) EGSM900 3DL/2UL @27.05dBm TBD mA EGSM900 2DL/3UL @26.82dBm TBD mA EGSM900 1DL/4UL @26.69dBm TBD mA DCS1800 4DL/1UL @25.21dBm TBD mA DCS1800 3DL/2UL @25.11dBm TBD mA DCS1800 2DL/3UL @25.01dBm TBD mA DCS1800 1DL/4UL @24.84dBm TBD mA PCS1900 4DL/1UL @25.21dBm TBD mA PCS1900 3DL/2UL @25.11dBm TBD mA PCS1900 2DL/3UL @25.01dBm TBD mA PCS1900 1DL/4UL @24.
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LTE Module Series AG35-QuecOpen Hardware Design LTE-FDD B3 @23.08dBm TBD mA LTE-FDD B4 @23.08dBm TBD mA LTE-FDD B5 @23.18dBm TBD mA LTE-FDD B7 @23dBm TBD mA LTE-FDD B8 @23.
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LTE Module Series AG35-QuecOpen Hardware Design Table 58: AG35-J Current Consumption Parameter Description Conditions Typ.
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LTE Module Series AG35-QuecOpen Hardware Design WCDMA B6 HSUPA @22.28dBm 545 mA WCDMA B8 HSUPA @22.28dBm 578 mA WCDMA B19 HSUPA @22.28dBm 565 mA LTE-FDD B1 @22.85dBm 660 mA LTE-FDD B3 @23.08dBm 680 mA LTE-FDD B5 @23.08dBm 670 mA LTE-FDD B8 @23.18dBm 630 mA LTE-FDD B9 @23dBm 629 mA LTE-FDD B19 @23.19dBm 645 mA LTE-FDD B21 @23dBm 600 mA LTE-FDD B28 @23dBm 700 mA LTE-TDD B41 @23dBm 430 mA WCDMA B1 (max power) @22.96dBm 590 mA WCDMA B3 (max power) @22.
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LTE Module Series AG35-QuecOpen Hardware Design Tracking (AT+CFUN=0) Open Sky @Passive Antenna 28.8 mA Conditions Typ. Unit Cold Start @Passive Antenna 48.5 mA Hot Start @Passive Antenna 47.3 mA Lost State @Passive Antenna 49.1 mA Open Sky @Passive Antenna 30.6 mA Conditions Typ. Unit Cold Start @Passive Antenna 50 mA Hot Start @Passive Antenna 49 mA Lost State @Passive Antenna 50 mA Open Sky @Passive Antenna 29 mA Conditions Typ.
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LTE Module Series AG35-QuecOpen Hardware Design Table 63: AG35-J GNSS Current Consumption Parameter Description Searching IVBAT (GNSS) (AT+CFUN=0) Tracking (AT+CFUN=0) Conditions Typ. Unit Cold Start @Passive Antenna TBD mA Hot Start @Passive Antenna TBD mA Lost State @Passive Antenna TBD mA Open Sky @Passive Antenna TBD mA NOTE 1) EVDO/CDMA BC0 for AG35-CE and LTE-FDD B28 for AG35-NA are optional. 6.5.
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LTE Module Series AG35-QuecOpen Hardware Design LTE-FDD B8 23dBm±2dB <-39dBm LTE-TDD B34 23dBm±2dB <-39dBm LTE-TDD B38 23dBm±2dB <-39dBm LTE-TDD B39 23dBm±2dB <-39dBm LTE-TDD B40 23dBm±2dB <-39dBm LTE-TDD B41 23dBm±2dB <-39dBm Table 65: AG35-E RF Output Power Frequency Max. Min.
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LTE Module Series AG35-QuecOpen Hardware Design Table 66: AG35-NA RF Output Power Frequency Max. Min.
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LTE Module Series AG35-QuecOpen Hardware Design WCDMA B5 24dBm+1/-3dB <-49dBm WCDMA B8 24dBm+1/-3dB <-49dBm LTE-FDD B1 23dBm±2dB <-39dBm LTE-FDD B2 23dBm±2dB <-39dBm LTE-FDD B3 23dBm±2dB <-39dBm LTE-FDD B4 23dBm±2dB <-39dBm LTE-FDD B5 23dBm±2dB <-39dBm LTE-FDD B7 23dBm±2dB <-39dBm LTE-FDD B8 23dBm±2dB <-39dBm LTE-FDD B28 23dBm±2dB <-39dBm Table 68: AG35-J RF Output Power Frequency Max. Min.
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LTE Module Series AG35-QuecOpen Hardware Design LTE-FDD B21 23dBm±2dB <-39dBm LTE-FDD B28 23dBm±2dB <-39dBm LTE-TDD B41 23dBm±2dB <-39dBm NOTES 1. 2. 1) EVDO/CDMA BC0 for AG35-CE and LTE-FDD B28 for AG35-NA are optional. In GPRS 4 slots TX mode, the maximum output power is reduced by 3.0dB. The design conforms to the GSM specification as described in Chapter 13.16 of 3GPP TS 51.010-1. 6.6. RF Receiving Sensitivity Table 69: AG35-CE RF Receiving Sensitivity Receive Sensitivity (Typ.
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LTE Module Series AG35-QuecOpen Hardware Design LTE-TDD B38 (10M) -98.5dBm -98dBm -102dBm -94.3dBm LTE-TDD B39 (10M) -98.4dBm -99dBm -102.1dBm -96.3dBm LTE-TDD B40 (10M) -98.3dBm -99dBm -101.5dBm -96.3dBm LTE-TDD B41 (10M) -97.6dBm -98dBm -101dBm -94.3dBm Table 70: AG35-E RF Receiving Sensitivity Receive Sensitivity (Typ.) Frequency Primary Diversity SIMO 3GPP (SIMO) EGSM900 -108.5 / / -102dBm DCS1800 -108.7 / / -102dBm WCDMA B1 -110 / / -106.7dBm WCDMA B5 -110.
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LTE Module Series AG35-QuecOpen Hardware Design Table 71: AG35-NA RF Receiving Sensitivity Receive Sensitivity (Typ.) Frequency Primary Diversity SIMO 3GPP (SIMO) GSM850 -108.5 / / -102dBm PCS1900 -108.2 / / -102dBm WCDMA B2 -109.5 -110.2 -110.4 -104.7dBm WCDMA B4 -109.8 -109,5 -110.9 -106.7dBm WCDMA B5 -110 -109.5 -110.8 -104.7dBm LTE-FDD B2 (10M) -98 -98.5 -100.6 -94.3dBm LTE-FDD B4 (10M) -97.9 -98,2 -100.3 -96.3dBm LTE-FDD B5 (10M) -98.5 -99 -100.8 -94.
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LTE Module Series AG35-QuecOpen Hardware Design WCDMA B2 TBD TBD TBD -104.7dBm WCDMA B4 TBD TBD TBD -106.7dBm WCDMA B3 TBD TBD TBD -103.7dBm WCDMA B5 TBD TBD TBD -104.7dBm WCDMA B8 TBD TBD TBD -103.7dBm LTE-FDD B1 (10M) TBD TBD TBD -96.3dBm LTE-FDD B2 (10M) TBD TBD TBD -94.3dBm LTE-FDD B3 (10M) TBD TBD TBD -93.3dBm LTE-FDD B4 (10M) TBD TBD TBD -96.3dBm LTE-FDD B5 (10M) TBD TBD TBD -94.3dBm LTE-FDD B7 (10M) TBD TBD TBD -94.
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LTE Module Series AG35-QuecOpen Hardware Design LTE-FDD B8 (10M) -98.5 -98.6 -100 -93.3dBm LTE-FDD B9(10M) -98,2 -98 -100 -95.3dBm LTE-FDD B19 (10M) -97.9 -98 -99.8 -96.3dBm LTE-FDD B21 (10M) -97 -97 -99 -96.3dBm LTE-FDD B28 (10M) -97 -97.2 -110.2 -94.8dBm LTE-TDD B41 (10M) -109 -109.8 -110.2 -94.3dBm NOTE 1) EVDO/CDMA BC0 for AG35-CE and LTE-FDD B28 for AG35-NA are optional. 6.7.
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LTE Module Series AG35-QuecOpen Hardware Design        On customers’ PCB design, please keep placement of the module away from heating sources, especially high power components such as ARM processor, audio power amplifier, power supply, etc. Do not place components on the opposite side of the PCB area where the module is mounted, in order to facilitate adding of heatsink when necessary.
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LTE Module Series AG35-QuecOpen Hardware Design Figure 46: Referenced Heatsink Design (Heatsink at the Backside of Customers’ PCB) NOTES 1. 2. For better performance, the maximum temperature of the internal BB chip should be kept below 105°C. When the maximum temperature of the BB chip reaches or exceeds 105°C, the module works normal but provides reduced performance (such as RF output power, data rate, etc.).
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LTE Module Series AG35-QuecOpen Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm, and the tolerances for dimensions without tolerance values are ±0.05mm. 7.1. Mechanical Dimensions of the Module 3.00±0.20 33.00±0.15 Pin 1 37.50±0.
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LTE Module Series AG35-QuecOpen Hardware Design Pin 1 3.45 3.45 3.15 3.50 R0.70 2.75 2.50 1.40 33.00±0.15 1.30 3.30 0.70 3.15 0.70 1.65 1.00 37.50±0.
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LTE Module Series AG35-QuecOpen Hardware Design 7.2. Recommended Footprint 4.1 Pin 1 4.45 3.80 3.45 3.45 3.15 3.50 0.70 3.30 2.75 R0.70 33.00±0.15 1.30 2.50 1.40 3.15 1.00 1.30 1.65 1.30 0.70 37.50±0.15 0.30 3.80 3.15 3.45 0.50 1.30 0.35 1.00 0.70 Figure 49: Recommended Footprint (Top View) NOTE For convenient maintenance of the module, please keep about 3mm between the module and other components on the host PCB.
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LTE Module Series AG35-QuecOpen Hardware Design 7.3. Design Effect Drawings of the Module Figure 50: Top View of the Module Figure 51: Bottom View of the Module NOTE These are renderings of AG35-Quecopen module. For authentic dimension and appearance, please refer to the module that you receive from Quectel.
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LTE Module Series AG35-QuecOpen Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage AG35-Quecopen is stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are shown as below. 1. Shelf life in vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be:   Mounted within 168 hours at the factory environment of ≤30ºC/60%RH.
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LTE Module Series AG35-QuecOpen Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properly so as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, the thickness of stencil for the module is recommended to be 0.15mm~0.18mm. For more details, please refer to document [8].
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LTE Module Series AG35-QuecOpen Hardware Design Reflow Zone Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 240°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 8.3. Packaging AG35-Quecopen is packaged in tape and reel carriers. One reel is 10.56 meters long and contains 220 modules. The figures below show the packaging details, measured in mm.
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LTE Module Series AG35-QuecOpen Hardware Design Cover taper Direction of feed Figure 54: Reel Specifications AG35-QuecOpen_Hardware_Design 129 / 137
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LTE Module Series AG35-QuecOpen Hardware Design 9 Appendix A References Table 76: Related Documents SN Document Name Remark [1] Quectel_AG35_Power_Management_Application_ Note AG35 Power Management Application Note [2] Quectel_AG35_AT_Commands_Manual AG35 AT Commands Manual [3] Quectel_AG35-Quecopen_Developer_Guide AG35-Quecopen Developer Guide [4] Quectel_LTE_OPEN_EVB_User_Guide EVB User Guide for LTE Quecopen Modules [5] Quectel_AG35_GNSS_AT_Commands_ Manual AG35 GNSS AT Commands Manua
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LTE Module Series AG35-QuecOpen Hardware Design CSD Circuit Switched Data CTS Clear To Send DC-HSPA+ Dual-carrier High Speed Packet Access DFOTA Delta Firmware Upgrade Over The Air DL Downlink DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate ESD Electrostatic Discharge EVDO Evolution-Data Optimized FDD Frequency Division Duplex FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite System GMSK Gau
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LTE Module Series AG35-QuecOpen Hardware Design LTE Long Term Evolution MIMO Multiple Input Multiple Output MO Mobile Originated MS Mobile Station (GSM engine) MT Mobile Terminated PAP Password Authentication Protocol PCB Printed Circuit Board PDU Protocol Data Unit PPP Point-to-Point Protocol Ppp Peak Pulse Power QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SIMO Single Input Multiple
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LTE Module Series AG35-QuecOpen Hardware Design Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value VILmin Minimum Input Low Level Voltage Value VImax Absolute Maximum Input Voltage Value VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value
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LTE Module Series AG35-QuecOpen Hardware Design 10 Appendix B GPRS Coding Schemes Table 78: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
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LTE Module Series AG35-QuecOpen Hardware Design 11 Appendix C GPRS Multi-slot Classes Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependent, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
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LTE Module Series AG35-QuecOpen Hardware Design 15 5 5 NA 16 6 6 NA 17 7 7 NA 18 8 8 NA 19 6 2 NA 20 6 3 NA 21 6 4 NA 22 6 4 NA 23 6 6 NA 24 8 2 NA 25 8 3 NA 26 8 4 NA 27 8 4 NA 28 8 6 NA 29 8 8 NA 30 5 1 6 31 5 2 6 32 5 3 6 33 5 4 6 AG35-QuecOpen_Hardware_Design 136 / 137
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LTE Module Series AG35-QuecOpen Hardware Design 12 Appendix D EDGE Modulation and Coding Schemes Table 80: EDGE Modulation and Coding Schemes Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2: GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3: GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4: GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.
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LTE Module Series AG35-QuecOpen Hardware Design FCC Regulations: This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. This device has been tested and found to comply with the limits for a Class B digital device , pursuant to Part 15 of the FCC Rules.
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LTE Module Series AG35-QuecOpen Hardware Design This device complies with the Canadian ICES-003 Class B specifications. CAN ICES-3(B)/ NMB-3(B) ISED Radiation Exposure Statement This device complies with RSS-102 radiation exposure limits set forth for an uncontrolled environment. In order to avoid the possibility of exceeding the ISED radio frequency exposure limits, human proximity to the antenna shall not be less than 20cm (8 inches) during normal operation.
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LTE Module Series AG35-QuecOpen Hardware Design Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation.