EG61-NAHardware Design LTEModule Series Rev. EG61-NA_Hardware_Design_V1.0 Date: 2019-01-04 Status: Preliminary www.quectel.
LTE Module Series EG61-NA Hardware Design Our aim is to provide customers with timely and comprehensive service. For any assistance, please contact our company headquarters: Quectel Wireless Solutions Co., Ltd. 7th Floor, Hongye Building, No.1801 Hongmei Road, Xuhui District, Shanghai 200233, China Tel: +86 21 5108 6236 Email: info@quectel.com Or our local office. For more information, please visit: http://www.quectel.com/support/sales.
LTE Module Series EG61-NA Hardware Design About the Document History Revision Date Author Description 1.
LTE Module Series EG61-NA Hardware Design Contents About the Document ................................................................................................................................ 2 Contents .................................................................................................................................................... 3 Table Index ..........................................................................................................................................
LTE Module Series EG61-NA Hardware Design 3.15. 3.16. 3.17. STATUS ................................................................................................................................ 49 Behaviors of RI ..................................................................................................................... 49 USB_BOOT Interface............................................................................................................ 50 4 GNSS Receiver ..........................
LTE Module Series EG61-NA Hardware Design Table Index TABLE 1: FREQUENCY BANDS OF EG61-NA MODULE ................................................................................ 14 TABLE 2: KEY FEATURES OF EG61-NA MODULE......................................................................................... 15 TABLE 3: IO PARAMETERS DEFINITION ........................................................................................................ 20 TABLE 4: PIN DESCRIPTION ...............................
LTE Module Series EG61-NA Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 17 FIGURE 2: PIN ASSIGNMENT (TOP VIEW) .................................................................................................... 19 FIGURE 3: SLEEP MODE APPLICATION VIA UART .......................................................................................
LTE Module Series EG61-NA Hardware Design FIGURE 39: REFERENCED HEATSINK DESIGN (HEATSINK AT THE TOP OF THE MODULE) .................. 68 FIGURE 40: REFERENCED HEATSINK DESIGN (HEATSINK AT THE BOTTOM OF CUSTOMERS’ PCB) . 68 FIGURE 41: MODULE TOP AND SIDE DIMENSIONS..................................................................................... 70 FIGURE 42: MODULE BOTTOM DIMENSIONS (TOP VIEW) .........................................................................
LTE Module Series EG61-NA Hardware Design 1 Introduction This document defines the EG61-NAmodule and describes its air interface and hardware interface which are connected with customers’ applications. This document can help customers quickly understand module interface specifications, electrical andmechanical details, as well as other related information of EG61-NA module. Associated with application note and user guide, customers can use EG61-NA module to design and set up mobile applications easily.
LTE Module Series EG61-NA Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of operation, such as usage, service or repair of any cellular terminal or mobile incorporating EG61-NA module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel, and incorporate these guidelines into all manuals supplied with the product.
LTE Module Series EG61-NA Hardware Design 1.2. FCC Certification Requirements. According to the definition of mobile and fixed device is described in Part 2.1091(b), this device is a mobile device. And the following conditions must be met: 1. This Modular Approval is limited to OEM installation for mobile and fixed applications only.
LTE Module Series EG61-NA Hardware Design If the device is used for other equipment that separate approval is required for all other operating configurations, including portable configurations with respect to 2.1093 and different antenna configurations. For this device, OEM integrators must be provided with labeling instructions of finished products. Please refer to KDB784748 D01 v07, section 8.
LTE Module Series EG61-NA Hardware Design This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the manufacturer could void the user’s authority to operate the equipment.
LTE Module Series EG61-NA Hardware Design antenne ou un autre émetteur. To comply with IC regulations limiting both maximum RF output power and human exposure to RF radiation, maximum antenna gain (including cable loss) must not exceed: ❒WCDMA Band2/ LTE Band2:≤8dBi ❒WCDMA Band4/ LTE Band4/66:≤5dBi ❒WCDMA Band5/ LTE Band5:≤6.1dBi ❒LTE Band12:≤5.61dBi ❒LTE Band13:≤5.93dBi ❒LTE Band71:≤5.45dBi The host product shall be properly labelled to identify the modules within the host product.
LTE Module Series EG61-NA Hardware Design 2 Product Concept 2.1. General Description EG61-NAmodule is an embedded 4G wireless communication module with receive diversity. It supportsLTE-FDD/WCDMA wireless communication, andprovides data connectivity on LTE-FDD,HSPA+, HSDPA, HSUPA, WCDMAnetworks. It can also provide voice functionality1)to meet customers’ specific application demands. The following table shows the frequency bands of EG61-NA module.
LTE Module Series EG61-NA Hardware Design Table 2: Key Features of EG61-NA Module Feature Details Power Supply Supply voltage: 3.3V~4.3V Typical supply voltage: 3.8V Transmitting Power Class 3 (24dBm+1/-3dB) for WCDMA bands Class 3 (23dBm±2dB) for LTE-FDD bands LTE Features Support up to non-CA Cat 1 FDD Support 1.
LTE Module Series EG61-NA Hardware Design UART Interface Main UART: Used for AT command communication and data transmission Baud rate reach up to 921600bps, 115200bps by default Support RTS and CTS hardware flow control Debug UART: Used for Linux console and log output 115200bps baud rate Rx-diversity Support LTE/WCDMA Rx-diversity GNSS Features Gen8C Lite of Qualcomm Protocol: NMEA 0183 AT Commands Compliant with 3GPP TS 27.007, 27.
LTE Module Series EG61-NA Hardware Design 2.3. Functional Diagram The following figure shows a block diagram of EG61-NA and illustrates the major functional parts. Power management Baseband DDR+NAND flash Radio frequency Peripheral interfaces ANT_MAIN ANT_GNSS SWITCH SAW Duplexer ANT_DIV Switch LNA SAW VBAT_RF PA SAW PRx GPS DRx Tx NAND DDR2 SDRAM Transceiver IQ VBAT_BB PMIC Control Control PWRKEY Baseband RESET_N STATUS 19.
LTE Module Series EG61-NA Hardware Design 3 Application Interfaces 3.1. General Description EG61-NAis equipped with 62-pin 1.1mm pitch SMT pads plus 44-pin ground/reserved pads that can be connected to customers’ cellular application platforms.
LTE Module Series EG61-NA Hardware Design 3.2. Pin Assignment NC GND VBAT_RF VBAT_RF GND GND ANT_DIV NC GND GND ANT_MAIN GND GND The following figure shows the pin assignment of EG61-NA module.
LTE Module Series EG61-NA Hardware Design NOTES 1. 2. 3. 1) PWRKEY output voltage is 0.8V because of the diode drop in the Qualcomm chipset. Keep all RESERVEDpins and unused pins unconnected. GND pads should be connected to ground in the design. 3.3. Pin Description The following tables show the pin definition and description of EG61-NA.
LTE Module Series EG61-NA Hardware Design VDD_EXT 29 GND 3, 31, 48, 50, 54, 55, 58, 59, 61, 62, 67~74, 79~82, 89~91, 100~106 PO Provide 1.8V for external circuit Vnorm=1.8V IOmax=50mA Power supply for external GPIO’s pull up circuits. Ground Turn on/off Pin Name PWRKEY RESET_N Pin No. 15 17 I/O Description DC Characteristics Comment Turnon/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V The output voltage is 0.8V because of the diode drop in the Qualcomm chipset.
LTE Module Series EG61-NA Hardware Design specification. (U)SIMInterfaces Pin Name USIM_GND Pin No. I/O Description DC Characteristics Connect to ground of (U)SIM card connector. Specified ground for (U)SIM card 47 For 1.8V(U)SIM: Vmax=1.9V Vmin=1.7V USIM1_VDD USIM1_DATA USIM1_CLK USIM1_RST 43 45 46 44 PO IO DO DO EG61-NA_Hardware_Design Power supply for (U)SIMcard Data signal of (U)SIMcard Clock signal of (U)SIMcard Reset signal of (U)SIMcard Comment For 3.0V(U)SIM: Vmax=3.
LTE Module Series EG61-NA Hardware Design USIM1_ PRESENCE 42 DI (U)SIMcard insertion detection VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V For 1.8V(U)SIM: Vmax=1.9V Vmin=1.7V USIM2_VDD USIM2_DATA USIM2_CLK USIM2_RST USIM2_ PRESENCE 87 86 84 85 83 PO IO DO DO DI Power supply for (U)SIMcard For 3.0V(U)SIM: Vmax=3.05V Vmin=2.7V IOmax=50mA Either 1.8V or 3.0V is supported by the module automatically. For 1.8V (U)SIM: VILmax=0.6V VIHmin=1.2V VOLmax=0.45V VOHmin=1.
LTE Module Series EG61-NA Hardware Design Pin Name Pin No. I/O Description DC Characteristics Comment 1.8V power domain. If unused, keep it open. RI 39 DO Ring indicator VOLmax=0.45V VOHmin=1.35V DCD 38 DO Data carrier detection VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Clear to send VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Request to send VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain.
LTE Module Series EG61-NA Hardware Design VILmax=0.6V VIHmin=1.2V VIHmax=2.0V PCM_DOUT PCM_SYNC PCM_CLK 7 5 4 DO IO IO If unused, keep it open. PCM data output VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. PCM data frame synchronization signal VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. In master mode, it is an output signal. In slave mode, it is an input signal. If unused, keep it open. PCM clock VOLmax=0.
LTE Module Series EG61-NA Hardware Design SPI_MISO 28 DI Master input slave output of SPI interface Pin No. I/O Description VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. DC Characteristics Comment RF Interface Pin Name ANT_GNSS ANT_DIV ANT_MAIN 49 56 60 AI GNSS antenna pad 50Ω impedance. If unused, keep it open. AI Receive diversity antenna pad 50Ω impedance. If unused, keep it open. IO Main antenna pad 50Ω impedance.
LTE Module Series EG61-NA Hardware Design 3.4. Operating Modes The table below briefly summarizes the various operating modes referred in the following chapters. Table 5: Overview of Operating Modes Mode Normal Operation Details Idle Software is active. The module hasregistered on network, and it is ready to send and receive data. Talk/Data Network connection is ongoing. In this mode, the power consumption is decided by network settingand data transfer rate.
LTE Module Series EG61-NA Hardware Design Host Module RXD TXD TXD RXD RI EINT DTR GPIO AP_READY GPIO GND GND Figure 3: Sleep Mode Application via UART Driving the host DTR to low level will wake up the module. When EG61-NA has a URC to report, RI signal will wake up the host. Refer to Chapter 3.16 for details about RI behavior. AP_READY will detect the sleep state of host (can be configured to high level or low level detection). Please refer to AT+QCFG="apready"*commandfor details.
LTE Module Series EG61-NA Hardware Design Host Module VDD USB_VBUS USB_DP USB_DP USB_DM USB_DM AP_READY GPIO GND GND Figure 4: Sleep Mode Application with USB Remote Wakeup Sending data to EG61-NAthrough USB will wake up the module. When EG61-NAhas a URC to report, the module will send remote wake-up signals via USB busso as to wake up the host. 3.5.1.3.
LTE Module Series EG61-NA Hardware Design Sending data to EG61-NAthrough USB will wake up the module. When EG61-NAhas a URC to report, RI signal will wake up the host. 3.5.1.4. USB Application without USB Suspend Function If the host does not support USB suspend function, USB_VBUS should be disconnected with an externalcontrol circuit to let the module enter into sleep mode. Execute AT+QSCLK=1commandto enable the sleep mode. Ensure the DTR is held at high level or keep it open.
LTE Module Series EG61-NA Hardware Design Software: AT+CFUNcommandprovides the choice of functionality levels as shown below: AT+CFUN=0: Minimum functionality mode.Both (U)SIM and RF functions are disabled. AT+CFUN=1: Full functionality mode (by default). AT+CFUN=4: Airplane mode. RF function is disabled. NOTES 1. Airplane mode control via W_DISABLE# is disabled in firmware by default. It can be enabled by 2. AT+QCFG="airplanecontrol" command and this command is under development.
LTE Module Series EG61-NA Hardware Design 3.6.2. Decrease Voltage Drop The power supply range of the module is from 3.3Vto4.3V. Please make sure thatthe input voltage will never drop below 3.3V. The following figure shows the voltage drop during burst transmission in 2G network.The voltage drop will be less in 3G and 4G networks. Burst Transmission Burst Transmission VBAT Ripple Drop Min.3.
LTE Module Series EG61-NA Hardware Design 3.6.3. Reference Design for Power Supply Power design for the module is very important, asthe performance of the module largely depends on the power source. The power supply should be able to provide sufficient current up to 2A at least. If the voltage drop between the input and output is not too high, it is suggested that an LDO should be usedto supply power for the module.
LTE Module Series EG61-NA Hardware Design Table 7: Pin Definition of PWRKEY Pin Name PWRKEY Pin No. 15 Description DC Characteristics Comment Turn on/off the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V The output voltage is 0.8V because of the diode drop in the Qualcomm chipset. When EG61-NA is in powerdownmode, it can be turned on to normal mode by driving the PWRKEY pin to a low level for at least 500ms. It is recommended to use an open drain/collector driver to control the PWRKEY.
LTE Module Series EG61-NA Hardware Design NOTE VBA T ≥500ms VIH≥1.3V VIL≤0.5V PWRKEY Abo ut 100ms VDD_EXT ≥100ms, afte r this time, the BOOT_CONFIG pins ca n b e set h igh level b y exter nal circuit BOO T_CONFIG & USB_BOO T PINS RESET_N ≥2.5s STATUS (OD) ≥12s UART Inactive Active ≥13s USB Inactive Active Figure 12: Timing of Turning on Module NOTES 1. 2. Please make sure that VBAT is stable before pulling down PWRKEY pin, and the time between them is no less than 30ms.
LTE Module Series EG61-NA Hardware Design 3.7.2.1. Turn off Module Using the PWRKEY Pin Driving the PWRKEY pin to a low level voltage for at least 650ms, the module will execute power-down procedure after the PWRKEY is released. The power-down scenario is illustrated inthe following figure. VBAT ≥ 650ms ≥ 30s PWRKEY STATUS Module Status RUNNING Power-down procedure OFF Figure 13: Timing of Turning off Module 3.7.2.2.
LTE Module Series EG61-NA Hardware Design Table 8: Pin Definition of RESET_N Pin Name RESET_N Pin No. 17 Description DC Characteristics Reset the module VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Comment The recommended circuit is similar to the PWRKEY control circuit. An open drain/collector driver or button can be used to control the RESET_N. RESET_N 150ms~460ms 4.
LTE Module Series EG61-NA Hardware Design VBAT ≤ 460ms ≥ 150ms VIH ≥ 1.3V RESET_N VIL ≤ 0.5V Module Status Running Resetting Restart Figure 16: Timing of Resetting Module NOTES 1. 2. RESET_N is only used when the module fails to be shut down via AT+QPOWD command and the PWRKEY pin. Ensure that there is no large capacitance on PWRKEY and RESET_N pins. 3.9. (U)SIM Interfaces EG61-NAprovides two (U)SIMinterfaces, andonly one (U)SIMcard can work at a time.
LTE Module Series EG61-NA Hardware Design USIM_GND 47 Specified ground for (U)SIMcard USIM2_VDD 87 PO Power supply for (U)SIM2 card USIM2_DATA 86 IO Data signal of (U)SIM2 card USIM2_CLK 84 DO Clock signal of (U)SIM2 card USIM2_RST 85 DO Reset signal of (U)SIM2 card USIM2_ PRESENCE 83 DI (U)SIM2 card insertion detection Either 1.8V or 3.0V is supported by the module automatically. EG61-NA supports (U)SIMcard hot-plug via the USIM_PRESENCE (USIM1_PRESENCE/USIM2_PRESENCE) pin.
LTE Module Series EG61-NA Hardware Design USIM_VDD 15K 100nF USIM_GND Module USIM_VDD USIM_RST USIM_CLK USIM_DATA (U)SIM Card Connector VCC RST CLK 0R GND VPP IO 0R 0R 33pF 33pF 33pF GND GND Figure 18: Reference Circuitof (U)SIM Interface with a 6-Pin (U)SIM Card Connector In order to enhance the reliability and availability of the (U)SIM card in customers’ applications, please follow the criteria below in the (U)SIM circuit design: Keep placement of (U)SIM card connector as cl
LTE Module Series EG61-NA Hardware Design 3.10. USB Interface EG61-NA contains one integrated Universal Serial Bus (USB) interfacewhich complies with the USB 2.0 specification and supports high-speed (480Mbps) and full-speed (12Mbps) modes. The USB interface is used for AT command communication, data transmission, GNSS NMEA sentences output,software debugging, firmware upgrade and voice over USB*. The following table shows the pin definition of USB interface.
LTE Module Series EG61-NA Hardware Design A common mode choke L1 is recommended to be added in series between the module and customer’sMCU in order to suppress EMI spurious transmission. Meanwhile, the 0Ω resistors (R3 and R4) should beadded in series between the module and the test points so as to facilitate debugging, and the resistors are not mounted by default.
LTE Module Series EG61-NA Hardware Design Table 11: Pin Definition of Main UART Interface Pin Name Pin No. I/O Description Comment RI 39 DO Ring indicator DCD 38 DO Data carrier detection CTS 36 DO Clear to send RTS 37 DI Request to send DTR 30 DI Sleep mode control TXD 35 DO Transmit data RXD 34 DI Receive data 1.8V power domain Table 12: Pin Definition of Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_TXD 23 DO Transmit data 1.
LTE Module Series EG61-NA Hardware Design VDD_EXT VCCA VCCB VDD_MCU 0.1uF 0.1uF OE GND RI A1 B1 RI_MCU DCD A2 B2 DCD_MCU CTS A3 B3 CTS_MCU Translator RTS A4 B4 RTS_MCU DTR A5 B5 DTR_MCU TXD A6 B6 TXD_MCU A7 B7 A8 B8 RXD 51K RXD_MCU 51K Figure 20: Reference Circuit with Translator Chip Please visit http://www.ti.com formore information. Another example with transistor translation circuit is shown as below.
LTE Module Series EG61-NA Hardware Design 3.12. PCM and I2C Interfaces EG61-NA provides one Pulse Code Modulation (PCM) digital interface for audio design, which supports the following modes and one I2C interface: Primary mode (short frame synchronization, works as both master and slave) Auxiliary mode (long frame synchronization, works as master only) In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge.
LTE Module Series EG61-NA Hardware Design 125us 1 PCM_CLK 2 31 32 PCM_SYNC MSB LSB MSB LSB PCM_DOUT PCM_DIN Figure 23: Auxiliary Mode Timing The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio codec design. Table 14: Pin Definition of PCM and I2C Interfaces Pin Name Pin No. I/O Description Comment PCM_DIN 6 DI PCM data input 1.8V power domain PCM_DOUT 7 DO PCM data output 1.
LTE Module Series EG61-NA Hardware Design MICBIAS BCLK PCM_SYNC LRCK PCM_DOUT DAC PCM_DIN ADC I2C_SCL SCL I2C_SDA SDA INP INN BIAS PCM_CLK Module 4.7K 4.7K LOUTP LOUTN Codec 1.8V Figure 24: Reference Circuit of PCM Application with Audio Codec NOTES 1. 2. It is recommended to reserve RC (R=22Ω, C=22pF) circuit on the PCM lines, especially for PCM_CLK. EG61-NA works as a master device pertaining to I2C interface. 3.13. SPI Interface SPI interface of EG61-NAacts asthe master only.
LTE Module Series EG61-NA Hardware Design SPI_CLK SPI_CLK SPI_MOSI SPI_MISO SPI_MISO SPI_MOSI Peripherals Module Figure 25: Reference Circuit of SPI Interface with Peripherals 3.14. Network Status Indication The module provides one network indication pin: NETLIGHT. The pin is used to drive a network status indication LED. The following tables describe the pin definition and logic level changes of NETLIGHT in different network status.
LTE Module Series EG61-NA Hardware Design VBAT Module 2.2K NETLIGHT 4.7K 47K Figure 26: Reference Circuit of the Network Status Indicator 3.15. STATUS The STATUS pin is set as the module’s operation status indicator. It will output high level when the module is powered on. The following table describes the pin definition of STATUS. Table 18: Pin Definition of STATUS Pin Name Pin No. I/O Description Comment STATUS 20 DO Indicate the module’s operation status 1.
LTE Module Series EG61-NA Hardware Design No matter on which port URC is presented, URC will trigger the behavior ofRI pin. NOTE URC can be outputted from UART port, USB AT port and USB modem port through configuration via AT+QURCCFG command. The default port is USB AT port. In addition, RI behavior can be configured flexibly. The default behaviors of the RI are shown as below.
LTE Module Series EG61-NA Hardware Design Module VDD_EXT Test point USB_BOOT 4.7K Close to test point TVS Figure 28: Reference Circuit of USB_BOOT Interface NOTE VBA T PWRKEY ≥500ms VIH≥1.3V VIL≤0.5V Abo ut 100ms VDD_EXT S e tti n g US B_B O O T to hi g h l e ve l be t we e n VB AT ri sin g on and VDD_EX T rising o n can le t th e m od u le en te r i nto e me rg e ncy d o wn lo ad mode USB_BOO T RESET_N Figure 29: Timing Sequence for Entering into Emergency Download Mode NOTES 1. 2.
LTE Module Series EG61-NA Hardware Design 4 GNSS Receiver 4.1. General Description EG61-NA includes a fully integrated global navigation satellite system solution that supports Gen8C-Lite of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS). EG61-NA supports standard NMEA-0183 protocol, and outputs NMEA sentences at 1Hz data update rate via USB interface by default. By default, EG61-NA GNSS engine is switched off. It has to be switched on via AT command.
LTE Module Series EG61-NA Hardware Design Accuracy (GNSS) @open sky XTRA enabled 2.1 s CEP-50 Autonomous @open sky 4 m NOTES 1. 2. 3. Tracking sensitivity: the lowest GNSS signal value at the antenna port on which the module can keep on positioning for 3 minutes. Reacquisition sensitivity: the lowest GNSS signal value at the antenna port on which the module can fix position again within 3 minutes after loss of lock.
LTE Module Series EG61-NA Hardware Design 5 Antenna Interfaces EG61-NA antenna interfaces include a main antenna interface andanRx-diversity antennainterface which is used toresist the fall of signals caused by high speed movement and multipath effect, and a GNSS antenna interface which is only supported on EG61-NA.The impedance of the antenna port is 50Ω. 5.1. Main/Rx-diversityAntenna Interfaces 5.1.1. Pin Definition The pin definitionof main antenna and Rx-diversityantenna interfaces is shown below.
LTE Module Series EG61-NA Hardware Design LTE FDD B5 824~849 869~894 MHz LTE FDD B12 699~716 729~746 MHz LTE FDD B13 777~787 746~756 MHz LTE-FDDB66 1710~1780 2100~2200 MHz LTE-FDD B71 663~698 617~652 MHz 5.1.3. Reference Design of RF Antenna Interface Areference design of ANT_MAIN and ANT_DIVantenna pads is shown as below. Aπ-type matching circuit should be reserved for better RF performance. The capacitors are not mounted by default.
LTE Module Series EG61-NA Hardware Design impedance of the RF traces is usually determined by the trace width (W), the materials’ dielectric constant, the distance between signal layer and reference ground (H), and the clearance between RF trace and ground (S). Microstrip line or coplanar waveguide line is typically used in RF layout for characteristic impedance control. The following are reference designs of microstrip line or coplanar waveguide line with different PCB structures. .
LTE Module Series EG61-NA Hardware Design Figure 33: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 3 as Reference Ground) Figure 34: Coplanar Waveguide Line Design on a 4-layer PCB (Layer 4 as Reference Ground) In order to ensure RF performance and reliability, the following principles should be complied with in RF layout design: Use impedance simulation tool to control the characteristic impedanceof RF tracesas 50Ω.
LTE Module Series EG61-NA Hardware Design Table 25: GNSS Frequency Type Frequency Unit GPS 1575.42±1.023 MHz GLONASS 1597.5~1605.8 MHz Galileo 1575.42±2.046 MHz BeiDou 1561.098±2.046 MHz QZSS 1575.42 MHz A reference design of GNSS antenna is shown as below. VDD 0.1uF 10R Module GNSS Antenna 47nH 100pF 0R ANT_GNSS NM NM Figure 35: Reference Circuit of GNSS Antenna NOTES 1. 2. An external LDO can be selected to supply power according to the active antenna requirement.
LTE Module Series EG61-NA Hardware Design Table 26: Antenna Requirements Type Requirements GNSS1) Frequency range: 1559MHz~1609MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0dBi Active antenna noise figure: < 1.5dB Active antenna gain: > 0dBi Active antenna embedded LNA gain: < 17dB WCDMA/LTE VSWR: ≤2 Efficiency: > 30% Max Input Power: 50 W Input Impedance: 50Ω Cable insertion loss: <1dB (WCDMA B5 LTE B5/B12/B13/B71) Cable Insertion Loss: <1.
LTE Module Series EG61-NA Hardware Design Figure 36: Dimensions of the U.FL-R-SMT Connector (Unit: mm) U.FL-LP serial connectors listed in the following figure can be used to match the U.FL-R-SMT. Figure 37:Mechanicals of U.FL-LP Connectors The following figure describes the space factor of mated connector.
LTE Module Series EG61-NA Hardware Design Figure 38:Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
LTE Module Series EG61-NA Hardware Design 6 Electrical, Reliability and RadioCharacteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of the module are listed in the following table. Table 27: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 0.8 A Peak Current of VBAT_RF 0 TBD A Voltage at Digital Pins -0.3 2.3 V 6.2.
LTE Module Series EG61-NA Hardware Design Voltage drop during burst transmission Maximum power control level on LTE IVBAT Peak supply current (during transmissionslot) Maximum power control level on LTE USB_VBUS USB connection detection 400 mV A 3.0 5.0 5.25 V 6.3. Operation and Storage Temperatures The operation and storage temperaturesare listed in the following table. Table 29: Operation and Storage Temperatures Parameter Min. Typ. Max.
LTE Module Series EG61-NA Hardware Design 6.4. Current Consumption The values of current consumption are shown below. Table 30: EG61-NA Current Consumption Parameter Description Conditions Typ. Unit OFF state Power down 12 uA AT+CFUN=0 (USB disconnected) 0.646 mA WCDMA PF=64 (USB disconnected) 1.483 mA WCDMA PF=64 (USB suspend) 1.844 mA WCDMA PF=512 (USB disconnected) 0.912 mA LTE-FDD PF=64 (USB disconnected) 1.96 mA LTE-FDD PF=64 (USB suspend) 2.
LTE Module Series EG61-NA Hardware Design WCDMA voice call LTE-FDD B5 @23.2dBm 602.0 mA LTE-FDD B12 @23.0dBm 714.0 mA LTE-FDD B13 @23.16dBm 663.0 mA LTE-FDD B66 @22.90dBm 746.3 mA LTE-FDD B71 @22.93dBm 718.0 mA WCDMA B2 @22.96dBm 647.0 mA WCDMA B4 @23.35dBm 607.0 mA WCDMA B5 @23.36dBm 550.0 mA Conditions Typ. Unit Cold start @Passive Antenna 52.765 mA Lost state @Passive Antenna 52.306 mA Instrument Environment 34.
LTE Module Series EG61-NA Hardware Design 6.6. RF Receiving Sensitivity The following tables show the conducted RF receiving sensitivity of EG61-NA module. Table 33: EG61-NA Conducted RF Receiving Sensitivity Frequency Primary Diversity SIMO 3GPP WCDMA B2 -109dBm -110dBm / -104.7dBm WCDMA B4 -109dBm -110dBm / -106.7dBm WCDMA B5 -110.5dBm -110.5dBm / -104.7dBm LTE-FDD B2 (10M) -97.7 -98.7 -101.7 -94.3dBm LTE-FDD B4 (10M) -97.7 -98.2 -100.2 -96.3dBm LTE-FDD B5 (10M) -99.
LTE Module Series EG61-NA Hardware Design ANT_MAIN,ANT_DIV ±8 ±12 KV ANT_GNSS ±6 ±10 KV Other Interfaces TBD TBD KV 6.8. Thermal Consideration In order to achieve better performance of the module, it is recommended to comply with the following principles for thermal consideration: On customers’ PCB design, please keep placement of the module away from heating sources, especially high power components such as ARM processor, audio power amplifier, power supply, etc.
LTE Module Series EG61-NA Hardware Design EG61-NA Module Heatsink Heatsink Thermal Pad Shielding Cover Application Board Application Board Figure 39: Referenced Heatsink Design (Heatsink at the Top of the Module) Thermal Pad EG61-NA Module Thermal Pad Heatsink Heatsink Application Board Shielding Cover Application Board Figure 40: Referenced Heatsink Design (Heatsink at the Bottom of Customers’ PCB) NOTES 1. The module offers the best performance when the internal BB chip stays below 105°C.
LTE Module Series EG61-NA Hardware Design 2. maximum BB chip temperature from the first returned value. For more detailed guidelines on thermal design, please refer to document [5].
LTE Module Series EG61-NA Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module.All dimensions are measured in mm. The tolerances for dimensions without tolerance values are ±0.05mm. 7.1. Mechanical Dimensions of the Module 25±0.15 31±0.15 2.45±0.
LTE Module Series EG61-NA Hardware Design 25±0.15 7.45 2.75 1.10 7.15 1.10 1.95 3.90 1.50 0.50 0.33 1.58 4.85 2.93 1.63 1.00 1.70 5.10 31±0.15 1.70 0.20 0.85 1.10 8.50 1.90 5.95 4.25 1.10 0.85 1.00 1.70 0.70 1.00 1.70 0.50 3.90 1.15 0.55 1.15 1.50 62x0.7 62x1.15 40x1.0 1.70 1.70 40x1.0 2.75 1.70 0.40 1.70 0.
LTE Module Series EG61-NA Hardware Design 7.2. Recommended Footprint 25±0.15 7.45 2.75 1.10 7.15 1.10 1.95 3.90 1.50 0.50 5.10 1.00 1.70 31±0.15 1.70 0.20 0.85 1.10 8.50 1.90 5.95 4.25 1.10 0.85 1.00 1.70 0.70 1.00 1.70 0.50 3.90 1.15 0.55 1.15 2.75 1.50 62x0.7 62x1.15 40x1.0 1.70 1.70 40x1.0 1.70 0.40 1.70 0.
LTE Module Series EG61-NA Hardware Design 7.3. Design Effect Drawings of the Module Figure 44: Top View of the Module Figure 45: Bottom View of the Module NOTE These are design effect drawings of EG61-NA module. For more accurate pictures, please refer to the module that you get from Quectel.
LTE Module Series EG61-NA Hardware Design 8 Storage, Manufacturing and Packaging 8.1. Storage EG61-NAis stored in a vacuum-sealed bag. It is rated at MSL 3, and its storage restrictions are listed below. 1. Shelf life in vacuum-sealed bag: 12 months at <40ºC/90%RH. 2. After the vacuum-sealed bag is opened, devices that will be subjected to reflow soldering or other high temperature processes must be: Mounted within 168 hours at the factory environment of ≤30ºC/60%RH. Stored at <10% RH. 3.
LTE Module Series EG61-NA Hardware Design 8.2. Manufacturing and Soldering Push the squeegee to apply the solder paste on the surface of stencil, thus making the paste fill the stencil openings and then penetrate to the PCB. The force on the squeegee should be adjusted properlyso as to produce a clean stencil surface on a single pass. To ensure the module soldering quality, thethickness of stencil for the module is recommended to be 0.15mm~0.18mm. For more details, please refer todocument [3].
LTE Module Series EG61-NA Hardware Design Max slope 2 to 3°C/sec Reflow time (D: over 220°C) 40 to 60 sec Max temperature 240°C ~ 245°C Cooling down slope 1 to 4°C/sec Reflow Cycle Max reflow cycle 1 NOTES 1. During manufacturing and soldering, or any other processes that may contact the module directly, NEVER wipe the module’s shielding can with organic solvents, such as acetone, ethyl alcohol, isopropyl alcohol, trichloroethylene, etc. Otherwise, the shielding can may become rusted. 2.
LTE Module Series EG61-NA Hardware Design Figure 47: Tape Dimensions 48.5 Cover tape 13 100 Direction of feed 44.5+0.20 -0.
LTE Module Series EG61-NA Hardware Design 9 Appendix A References Table 36: Related Documents SN Document Name Remark [1] Quectel_EC2x&EG9x&EM05_Power_Management_ Application_Note Power Management Application Note for EC25, EC21, EC20 R2.0, EC20 R2.
LTE Module Series EG61-NA Hardware Design DTR Data Terminal Ready DTX Discontinuous Transmission EFR Enhanced Full Rate ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GSM Global System For Mobile Communications HR Half Rate HSPA High Speed Packet Access HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access I/O Input/Output Inorm Normal Current LED Light Emitting Diode LNA Low Noise Amplifier LTE Long Term Evolution MIMO Multip
LTE Module Series EG61-NA Hardware Design QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SMS Short Message Service TDD Time Division Duplexing TX Transmitting Direction UL Uplink UMTS Universal Mobile Telecommunications System URC Unsolicited Result Code (U)SIM (Universal) Subscriber Identity Module Vmax Maximum Voltage Value Vnorm Normal Voltage Value Vmin Minimum Voltage Value VIHmax
LTE Module Series EG61-NA Hardware Design VSWR Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access EG61-NA_Hardware_Design 81 / 77
