EC20 Hardware Design LTE Module Series Rev. EC20_Hardware_Design Date: 2015-10-23 www.quectel.
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LTE Module EC20 Hardware Design About the Document History Revision Date Author Description 1.0 2015-02-13 Mountain ZHOU/ Mike ZHANG Initial Mountain ZHOU 1. 2. 3. 4. 5. 6. 7. 8. Added UART interface pins Added FOTA upgrade mode Updated module dimension information Updated functional diagram Updated power supply reference circuit Updated description of UART interface Updated current consumption Updated GNSS sensitivity Mountain ZHOU 1. 2. 3. 4. 5. 6.
LTE Module EC20 Hardware Design Contents About the Document ................................................................................................................................... 2 Contents ....................................................................................................................................................... 3 Table Index ..............................................................................................................................................
LTE Module EC20 Hardware Design 3.13. ADC Function .......................................................................................................................... 42 3.14. Network Status Indication ........................................................................................................ 43 3.15. Operating Status Indication ..................................................................................................... 44 3.16. Behavior of the RI ..............................
LTE Module EC20 Hardware Design Table Index TABLE 1: EC20 FREQUENCY BANDS .............................................................................................................. 9 TABLE 2: EC20 KEY FEATURES ...................................................................................................................... 11 TABLE 3: IO PARAMETERS DEFINITION ........................................................................................................ 17 TABLE 4: PIN DESCRIPTION ........
LTE Module EC20 Hardware Design Figure Index FIGURE 1: FUNCTIONAL DIAGRAM ............................................................................................................... 14 FIGURE 2: PIN ASSIGNMENT (TOP VIEW)..................................................................................................... 16 FIGURE 3: UART SLEEP APPLICATION .........................................................................................................
LTE Module EC20 Hardware Design 1 Introduction This document defines the EC20 module and describes its air interface and hardware interface which are connected with your application. This document can help you quickly understand module interface specifications, electrical, mechanical details and related product information of EC20 module. Associated with application notes and user guide, you can use EC20 module to design and set up mobile applications easily.
LTE Module EC20 Hardware Design 1.1. Safety Information The following safety precautions must be observed during all phases of the operation, such as usage, service or repair of any cellular terminal or mobile incorporating EC20 module. Manufacturers of the cellular terminal should send the following safety information to users and operating personnel and to incorporate these guidelines into all manuals supplied with the product.
LTE Module EC20 Hardware Design 2 Product Concept 2.1. General Description EC20 is a series of LTE-FDD/WCDMA/GSM wireless communication module with receive diversity, which provides data connectivity on FDD-LTE, DC-HSPA+, HSPA+, HSDPA, HSUPA, WCDMA, EDGE and GPRS networks. It can also provide GPS/GLONASS1) and voice functionality for your specific application.
LTE Module EC20 Hardware Design 76 LCC signal pads and 64 other pads. 2.2. Directives and Standards The EC20 module is designed to comply with the FCC statements. FCC ID: XMR201603EC20 The Host system using EC20 should have label “contains modular’s FCC ID: XMR201603EC20”. 2.2.1. FCC Statement Changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate the equipment. 2.2.2.
LTE Module EC20 Hardware Design 2.3. Key Features The following table describes the detailed features of EC20 module. Table 2: EC20 Key Features Feature Details Power Supply Supply voltage: 3.3V~4.3V Transmitting Power Class 4 (33dBm±2dB) for GSM850 Class E2 (27dBm±3dB) for GSM850 8-PSK Class E2 (26dBm±3dB) for PCS1900 8-PSK Class 3 (24dBm+1/-3dB) for WCDMA bands Class 3 (23dBm±2dB) for LTE FDD bands LTE Features Support 3GPP R9 CAT3 FDD Support 1.
LTE Module EC20 Hardware Design USIM Interface Support USIM/SIM card: 1.8V, 3.
LTE Module EC20 Hardware Design NOTES 1. 2. 3. 1) Audio (PCM) function is only supported on Telematics version. This function is under development. 3) When the module works within this restricted temperature range, RF performance might degrade. For example, the frequency error or the phase error would increase. 2) 2.4. Functional Diagram The following figure shows a block diagram of EC20 and illustrates the major functional parts.
LTE Module EC20 Hardware Design Figure 1: Functional Diagram 2.5. Evaluation Board In order to help you to develop applications with EC20, Quectel supplies an evaluation board (EVB), USB data cable, earphone, antenna and other peripherals to control or test the module.
LTE Module EC20 Hardware Design 3 Application Interface 3.1. General Description EC20 is equipped with a 76-pin 1.3mm pitch SMT pads plus 64-pin ground pads and reserved pads that connect to cellular application platform.
LTE Module EC20 Hardware Design 3.2. Pin Assignment The following figure shows the pin assignment of the EC20 module.
LTE Module EC20 Hardware Design 3.3. Pin Description The following tables show the EC20’s pin definition. Table 3: IO Parameters Definition Type Description IO Bidirectional input/output DI Digital input DO Digital output PI Power input PO Power output AI Analog input AO Analog output OD Open drain Table 4: Pin Description Power Supply Pin Name VBAT_BB VBAT_RF Pin No.
LTE Module EC20 Hardware Design 56, 72, 85~112 Turn On/Off Pin Name PWRKEY RESET_N Pin No. I/O Description DC Characteristics Comment DI Turn on/off the module. VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Pull-up to 1.8V internally. DI Reset the module. VIHmax=2.1V VIHmin=1.3V VILmax=0.5V Pull-up to 1.8V internally. Active low. I/O Description DC Characteristics Comment OD Indicate the module operating status. The drive current should be less than 0.9mA. Require external pull-up.
LTE Module EC20 Hardware Design USIM card. Vmax=1.9V Vmin=1.7V supported by the module automatically. For 3.0V USIM: Vmax=3.05V Vmin=2.7V IOmax=50mA USIM_DATA USIM_CLK USIM_RST USIM_PRE SENCE 15 16 17 13 IO DO DO Data signal of USIM card. Clock signal of USIM card. Reset signal of USIM card. For 1.8V USIM: VILmax=0.6V VIHmin=1.2V VOLmax=0.45V VOHmin=1.35V For 3.0V USIM: VILmax=1.0V VIHmin=1.95V VOLmax=0.45V VOHmin=2.55V For 1.8V USIM: VOLmax=0.45V VOHmin=1.35V For 3.0V USIM: VOLmax=0.
LTE Module EC20 Hardware Design DCD CTS RTS DTR TXD RXD 63 64 65 66 67 68 Data carrier detection. VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Clear to send. VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. Request to send. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. Data terminal ready, sleep mode control. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain.
LTE Module EC20 Hardware Design PCM Interface Pin Name PCM_IN PCM_OUT PCM_SYNC PCM_CLK Pin No. 24 25 26 I/O DI DO IO Description DC Characteristics Comment PCM data input. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. If unused, keep it open. PCM data output. VOLmax=0.45V VOHmin=1.35V 1.8V power domain. If unused, keep it open. PCM data frame sync signal. VOLmax=0.45V VOHmin=1.35V VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain.
LTE Module EC20 Hardware Design GPIO Pins Pin Name WAKEUP_IN W_DISABLE# AP_READY Pin No. 1 4 2 I/O DI Description DC Characteristics Comment Sleep mode control. VILmin=-0.3V VILmax=0.6V VIHmin=1.2V VIHmax=2.0V 1.8V power domain. Pull-up by default. Low level wakes up the module. If unused, keep it open. 1.8V power domain. Pull-up by default. In low voltage level, module can enter into airplane mode. If unused, keep it open. DI Airplane mode control. VILmin=-0.3V VILmax=0.6V VIHmin=1.
LTE Module EC20 Hardware Design Functionality Mode without removing the power supply. In this case, both RF function and USIM card will be invalid. Airplane Mode AT+CFUN command and W_DISABLE# pin can set the module entering into airplane mode. In this case, RF function will be invalid. Sleep Mode In this mode, the current consumption of the module will be reduced to the minimal level.
LTE Module EC20 Hardware Design Driving host DTR to low level will wake up the module. When EC20 has URC to report, RI signal will wake up the host. Refer to Chapter 3.16 for details about RI behavior. AP_READY will detect the sleep state of host (can be configured to high level or low level detection). Refer to AT command AT+QCFG=“apready” for details. 3.5.1.2.
LTE Module EC20 Hardware Design 3.5.1.3. USB Application with USB Suspend/Resume and RI Function If host supports USB suspend/resume, but does not support remote wake-up function, the RI signal is needed to wake up the host. The following part will show the sleep application. There are three preconditions to let the module enter into the sleep mode. Execute AT command AT+QSCLK=1 to enable the sleep mode. Ensure the DTR is held in high level or keep it open.
LTE Module EC20 Hardware Design The following figure shows the connection between the module and host. Module Host GPIO USB_VBUS Power Switch VDD USB_DP USB_DP USB_DM USB_DM RI EINT AP_READY GPIO GND GND Figure 6: Sleep Application without Suspend Function Opening power switch to supply power to USB_VBUS will wake up the module. NOTE You should pay attention to the level match shown in dotted line between module and host.
LTE Module EC20 Hardware Design NOTES 1. The W_DISABLE# control function is disabled in firmware by default. It can be enabled by AT command AT+QCFG=“airplanecontrol”. Refer to document [2]. 2. The execution of AT+CFUN command will not affect GNSS function. 3.6. Power Supply 3.6.1. Power Supply Pins EC20 provides four VBAT pins dedicated to connect with the external power supply. There are two separate voltage domains for VBAT. VBAT_RF with two pins for module RF part.
LTE Module EC20 Hardware Design Transmit burst Transmit burst VBAT Ripple Drop Min.3.3V Figure 7: Power Supply Limits during Transmit Burst To decrease voltage drop, a bypass capacitor of about 100µF with low ESR should be used. Multi-layer ceramic chip (MLCC) capacitor can provide the best combination of low ESR. The main power supply from an external application has to be a single voltage source and expanded to two sub paths with star structure.
LTE Module EC20 Hardware Design use a LDO to supply power for module. If there is a big voltage difference between the input source and the desired output (VBAT), a buck converter is preferred to be used as a power supply. The following figure shows a reference design for +5V input power source. The designed output for the power supply is about 3.8V and the maximum load current is 3A. MIC29302WU DC_IN VBAT OUT 5 3 1 51K ADJ GND IN EN 2 4 100K 1% 470R 4.
LTE Module EC20 Hardware Design When EC20 is in power down mode, it can be turned on to normal mode by driving the PWRKEY pin to a low level for at least 100ms. It is recommended to use an open drain/collector driver to control the PWRKEY. After STATUS pin (require external pull-up) outputting a low level, PWRKEY pin can be released. A simple reference circuit is illustrated in the following figure. PWRKEY ≥ 100ms 4.
LTE Module EC20 Hardware Design The turn on scenarios is illustrated as the following figure. NOTE VBAT ≥ 100ms VIH ≥ 1.3V PWRKEY VIL ≤ 0.5V RESET_N ≤ 0.5s STATUS (OD) ≥ 7.5s UART Inactive Active ≥ 9s USB Inactive Active Figure 12: Timing of Turning on Module NOTE Make sure that VBAT is stable before pulling down PWRKEY pin. The time between them is no less than 30ms. 3.7.2.
LTE Module EC20 Hardware Design VBAT ≥ 0.6s Log off network about 1s to 60s PWRKEY STATUS (OD) Module Status Power-down procedure RUNNING OFF Figure 13: Timing of Turning off Module 3.7.2.2. Turn off Module Using AT Command It is also a safe way to use AT command AT+QPOWD to turn off the module, which is similar to turning off the module via PWRKEY Pin. Please refer to document [2] for details about the AT command of AT+QPOWD. 3.8. Reset the Module The RESET_N can be used to reset the module.
LTE Module EC20 Hardware Design RESET_N ≥ 150ms 4.7K Reset pulse 47K Figure 14: Reference Circuit of RESET_N by Using Driving Circuit S2 RESET_N TVS Close to S2 Figure 15: Reference Circuit of RESET_N by Using Button The reset scenario is illustrated as the following figure. VBAT ≥ 9s ≥150ms VIH ≥ 1.3V RESET_N VIL ≤ 0.5V Module Status RUNNING RESETTING RUNNING Figure 16: Timing of Resetting Module NOTES 1. 2.
LTE Module EC20 Hardware Design 3.9. USIM Card Interface The USIM card interface circuitry meets ETSI and IMT-2000 SIM interface requirements. Both 1.8V and 3.0V USIM cards are supported. Table 9: Pin Definition of the USIM Interface Pin Name Pin No. I/O Description Comment Either 1.8V or 3.0V is supported by the module automatically. USIM_VDD 14 PO Power supply for USIM card. USIM_DATA 15 IO Data signal of USIM card. USIM_CLK 16 DO Clock signal of USIM card.
LTE Module EC20 Hardware Design If you do not need the USIM card detection function, keep USIM_PRESENCE unconnected. The reference circuit for using a 6-pin USIM card connector is illustrated as the following figure.
LTE Module EC20 Hardware Design 3.10. USB Interface EC20 contains one integrated Universal Serial Bus (USB) transceiver which complies with the USB 2.0 specification and supports high-speed (480Mbps) and full-speed (12Mbps) mode. The USB interface is used for AT command, data transmission, GNSS NMEA sentences output, software debug and firmware upgrade. The following table shows the pin definition of USB interface. Table 10: USB Pin Description Pin Name Pin No.
LTE Module EC20 Hardware Design In order to ensure the USB interface design corresponding with the USB 2.0 specification, please comply with the following principles. It is important to route the USB signal traces as differential pairs with total grounding. The impedance of USB differential trace is 90ohm. Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces.
LTE Module EC20 Hardware Design RTS 65 DI Request to send 1.8V power domain DTR 66 DI Sleep mode control 1.8V power domain TXD 67 DO Transmit data 1.8V power domain RXD 68 DI Receive data 1.8V power domain Table 12: Pin Definition of the Debug UART Interface Pin Name Pin No. I/O Description Comment DBG_TXD 12 DO Transmit data 1.8V power domain DBG_RXD 11 DI Receive data 1.8V power domain The logic levels are described in the following table.
LTE Module EC20 Hardware Design VDD_EXT VCCA VCCB VDD_MCU 0.1uF 0.1uF OE GND RI A1 B1 RI_MCU DCD A2 B2 DCD_MCU CTS A3 B3 CTS_MCU RTS A4 B4 RTS_MCU DTR A5 B5 DTR_MCU TXD A6 B6 TXD_MCU A7 B7 RXD 51K Translator A8 RXD_MCU 51K B8 Figure 20: Reference Circuit with Translator Chip Please visit http://www.ti.com for more information. Another example with transistor translation circuit is shown as below. The circuit of dotted line can refer to the circuit of solid line.
LTE Module EC20 Hardware Design 3.12. PCM and I2C Interface EC20 provides one Pulse Code Modulation (PCM) digital interface for audio design, which supports the following modes: Primary mode (short sync, works as both master and slave) Auxiliary mode (long sync, works as master only) In primary mode, the data is sampled on the falling edge of the PCM_CLK and transmitted on the rising edge; the PCM_SYNC falling edge represents the MSB.
LTE Module EC20 Hardware Design 125us PCM_CLK 1 2 15 16 PCM_SYNC MSB LSB PCM_OUT MSB LSB PCM_IN Figure 23: Auxiliary Mode Timing The following table shows the pin definition of PCM and I2C interface which can be applied on audio codec design. Table 14: Pin Definition of PCM and I2C Interface Pin Name Pin No. I/O Description Comment PCM_IN 24 DI PCM data input 1.8V power domain PCM_OUT 25 DO PCM data output 1.8V power domain PCM_SYNC 26 IO PCM data frame sync signal 1.
LTE Module EC20 Hardware Design The following figure shows the reference design of PCM interface with external codec IC. PCM_CLK BCLK PCM_SYNC LRCK PCM_OUT DAC PCM_IN ADC I2C_SCL SCL I2C_SDA SDA INP INN BIAS MICBIAS 4.7K Module 4.7K LOUTP LOUTN ALC5616 1.8V Figure 24: Reference Circuit of PCM Application with Audio Codec NOTES 1. 2. It is recommended to reserved RC (R=22ohm, C=22pF) circuit on the PCM lines, especially for PCM_CLK.
LTE Module EC20 Hardware Design The following table describes the characteristic of the ADC function. Table 16: Characteristic of the ADC Parameter Min. ADC0 Voltage Range ADC1 Voltage Range Typ. Max. Unit 0.3 VBAT_BB V 0.3 VBAT_BB V ADC Resolution 15 bits 3.14. Network Status Indication The network indication pins can be used to drive a network status indicator LED. The module provides two pins which are NET_MODE and NET_STATUS.
LTE Module EC20 Hardware Design A reference circuit is shown in the following figure. VBAT Module 2.2K 4.7K Network Indicator 47K Figure 25: Reference Circuit of the Network Indicator 3.15. Operating Status Indication The STATUS pin is an open drain output for indicating the module operation status. You can connect it to a GPIO of DTE with pulled up, or as LED indication circuit as below. When the module is turned on normally, the STATUS will present the low state.
LTE Module EC20 Hardware Design 3.16. Behavior of the RI You can use command AT+QCFG=“risignaltype”,“physical” to configure RI behavior: No matter which port URC is presented on, URC will trigger the behavior on RI pin. NOTE URC can be output from UART port, USB AT port and USB modem port by command AT+QURCCFG. The default port is USB AT port. In addition, RI behavior can be configured flexible. The default behavior of the RI is shown as below.
LTE Module EC20 Hardware Design 4 GNSS Receiver 4.1. General Description EC20 includes a fully integrated global navigation satellite system solution that supports gpsOne Gen8A of Qualcomm (GPS and GLONASS). Compared with GPS only, dual systems increase usable constellation, reduce coverage gaps and TTFF, and increase positioning accuracy, especially in rough urban environments.
LTE Module EC20 Hardware Design 4.2. GNSS Performance The following table shows EC20 GNSS performance. Table 21: GNSS Performance Parameter Sensitivity (GNSS) Description Conditions Typ. Unit Cold start Autonomous -146 dBm Reacquisition Autonomous -156 dBm Tracking Autonomous -157 dBm Autonomous 35 s XTRA enabled 22 s Autonomous 30 s XTRA enabled 3.5 s Autonomous 2 s XTRA enabled 1.5 s Autonomous @open sky <1.
LTE Module EC20 Hardware Design 4.3. Layout Guideline The following layout guideline should be taken into account in your design. Maximize the distance between the GNSS antenna, the main antenna and Rx-diversity antenna. Noisy digital circuits such as the USIM card, USB interface, Camera module, Display connector and SD card should be away from the antenna. Use ground vias around the GNSS trace and sensitive analog signal traces to provide coplanar isolation and protection.
LTE Module EC20 Hardware Design 5 Antenna Interface EC20 antenna interface includes a main antenna, an Rx-diversity antenna, which is used to resist the fall of signals caused by high speed movement and multipath effect, and a GNSS antenna. The antenna interface has an impedance of 50ohm. 5.1. Main/Rx-diversity Antenna Interface 5.1.1. Pin Definition The main antenna and Rx-diversity antenna pins definition are shown below. Table 22: Pin Definition of the RF Antenna Pin Name Pin No.
LTE Module EC20 Hardware Design 5.1.3. Reference Design The reference design of ANT_MAIN and ANT_DIV antenna is shown as below. It should reserve a π-type matching circuit for better RF performance. The capacitors are not mounted by default. Main antenna Module R1 0R ANT_MAIN C1 C2 NM NM Diversity antenna R2 0R ANT_DIV C3 C4 NM NM Figure 27: Reference Circuit of Antenna Interface NOTE Keep a proper distance between main antenna and Rx-diversity antenna to improve the receiving sensitivity.
LTE Module EC20 Hardware Design Table 25: GNSS Frequency Type Frequency Unit GPS 1575.42 ± 1.023 MHz GLONASS 1597.5 ~ 1605.8 MHz The reference design of GNSS antenna is shown as below. VDD GNSS Antenna 10R 0.1uF Module 47nH 100pF ANT_GNSS NM NM Figure 28: Reference Circuit of GNSS Antenna NOTES 1. 2. You can choose an external LDO to supply power according to the active antenna. If you design it with passive antenna, the VDD circuit is not needed. 5.3. Antenna Installation 5.3.1.
LTE Module EC20 Hardware Design GNSS GSM/WCDMA/ LTE Frequency range: 1565 - 1607MHz Polarization: RHCP or linear VSWR: < 2 (Typ.) Passive antenna gain: > 0dBi Active antenna noise figure: < 1.5dB Active antenna gain: > -2dBi Active antenna embedded LNA gain: 20dB (Typ.) Active antenna total gain: > 18dBi (Typ.) VSWR: ≤ 2 Gain (dBi): 1 Max Input Power (W): 50 Input Impedance (ohm): 50 Polarization Type: Vertical Cable Insertion Loss: < 1dB (GSM850/900, WCDMA B5, LTE B5/B12/B17) Cable Insertion Loss: < 1.
LTE Module EC20 Hardware Design Figure 29: Dimensions of the UF.L-R-SMT Connector (Unit: mm) You can use U.FL-LP serial connector listed in the following figure to match the UF.L-R-SMT. Figure 30: Mechanicals of UF.L-LP Connectors The following figure describes the space factor of mated connector.
LTE Module EC20 Hardware Design Figure 31: Space Factor of Mated Connector (Unit: mm) For more details, please visit http://www.hirose.com.
LTE Module EC20 Hardware Design 6 Electrical, Reliability and Radio Characteristics 6.1. Absolute Maximum Ratings Absolute maximum ratings for power supply and voltage on digital and analog pins of module are listed in the following table. Table 27: Absolute Maximum Ratings Parameter Min. Max. Unit VBAT_RF/VBAT_BB -0.3 4.7 V USB_VBUS -0.3 5.5 V Peak Current of VBAT_BB 0 0.8 A Peak Current of VBAT_RF 0 1.8 A Voltage at Digital Pins -0.3 2.
LTE Module EC20 Hardware Design 6.2. Power Supply Ratings Table 28: The Module Power Supply Ratings Parameter Description Conditions Min. Typ. Max. Unit VBAT_BB and VBAT_RF Voltage must stay within the min/max values, including voltage drop, ripple and spikes. 3.3 3.8 4.3 V Voltage drop during transmitting burst Maximum power control level on GSM850 and EGSM900. 400 mV IVBAT Peak supply current (during transmission slot) Maximum power control level on GSM850 and EGSM900. 1.8 2.
LTE Module EC20 Hardware Design 6.4. Current Consumption The values of current consumption are shown below. Table 30: EC20 Current Consumption Parameter Description Conditions Typ. Unit OFF state Power down 20 uA AT+CFUN=0 (USB disconnected) 1.05 mA GSM DRX=2 (USB disconnected) 3.7 mA GSM DRX=9 (USB disconnected) 1.8 mA WCDMA DRX=6 (USB disconnected) 2.8 mA WCDMA DRX=9 (USB disconnected) 1.
LTE Module EC20 Hardware Design WCDMA data transfer (GNSS off) LTE data transfer (GNSS off) PCS1900 1DL/4UL PCL=2 413 mA WCDMA B2 HSDPA @max power 496 mA WCDMA B2 HSUPA @max power 498 mA WCDMA B4 HSDPA @max power 442 mA WCDMA B4 HSUPA @max power 465 mA WCDMA B5 HSDPA @max power 464 mA WCDMA B5 HSUPA @max power 445 mA LTE-FDD B2 @max power 584 mA LTE-FDD B4 @max power 564 mA LTE-TDD B5 @max power 521 mA LTE-TDD B12 @max power 432 mA LTE-TDD B17 @max power 431 mA GSM850
LTE Module EC20 Hardware Design Table 31: EC20 Conducted RF Receiving Sensitivity Frequency Receive Sensitivity (Typ.) GSM850 -111dBm PCS1900 -109dBm WCDMA B2 -111dBm WCDMA B4 -111dBm WCDMA B5 -112dBm LTE FDD B2 (20M) -96dBm LTE FDD B4 (20M) -96dBm LTE FDD B5 (10M) -98dBm LTE FDD B12 (10M) -99dBm LTE FDD B17 (10M) -99dBm 6.7. Electrostatic Discharge The module is not protected against electrostatics discharge (ESD) in general.
LTE Module EC20 Hardware Design 7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module. All dimensions are measured in mm. 7.1. Mechanical Dimensions of the Module 2.4+/-0.2 (29+/-0.15) (32+/-0.15) 0.
LTE Module EC20 Hardware Design 29.0 32.
LTE Module EC20 Hardware Design Keepout area 29 Keepout area 7.2. Footprint of Recommendation 32 Figure 35: Recommended Footprint (Top View) NOTE In order to maintain the module, keep about 3mm between the module and other components in the host PCB.
LTE Module EC20 Hardware Design Figure 36: Recommended Stencil NOTES 1. 2. 3. The thickness of stencil for the pads at the bottom of module is recommended as 0.18mm, and the thickness of LCC pins is recommended as 0.2mm. For better SMT solder, the GND pad at the bottom of the module is divided into four small pads. The red areas are recommended footprint shown in Figure 35.
LTE Module EC20 Hardware Design Keepout area 29.0 If you design with pins 117~140, the following footprint is recommended. 32.
LTE Module EC20 Hardware Design 7.3. Top View of the Module Figure 38: Top View of the Module 7.4.
LTE Module EC20 Hardware Design 8 Storage and Manufacturing 8.1. Storage EC20 is stored in the vacuum-sealed bag. The restriction of storage condition is shown as below. Shelf life in sealed bag is 12 months at < 40ºC/90%RH. After this bag is opened, devices that will be subjected to reflow solder or other high temperature process must be: Mounted within 72 hours at factory conditions of ≤ 30ºC/60%RH. Stored at <10% RH.
LTE Module EC20 Hardware Design It is suggested that peak reflow temperature is 235 ~ 245ºC (for SnAg3.0Cu0.5 alloy). Absolute max reflow temperature is 260ºC. To avoid damage to the module when it was repeatedly heated, it is suggested that the module should be mounted after the first panel has been reflowed. The following picture is the actual diagram which we have operated.
LTE Module EC20 Hardware Design 8.3. Packaging 29.3±0.15 0.35±0.05 30.3±0.15 1 1 0. 0± 5 . 44.00±0.3 20.20±0.15 44.00±0.1 2.00±0.1 4.00±0.1 30.3±0.15 1.75±0.1 EC20 is packaged in the tap and reel carriers. One reel is 11.53m length and contains 250pcs modules. The figure below shows the package details, measured in mm. 4.2±0.15 3.1±0.15 32.5±0.15 33.5±0.15 32.5±0.15 33.5±0.15 48.5 Cover tape 13 100 Direction of feed 44.5+0.20 -0.
LTE Module EC20 Hardware Design 9 Appendix A Reference Table 33: Related Documents SN Document Name Remark [1] Quectel_EC20_Power_Management_Application_ Note EC20 Power Management Application Note [2] Quectel_EC20_AT_Commands_Manual EC20 AT Commands Manual [3] Quectel_EC20_GNSS_AT_Commands_Manual EC20 GNSS AT Commands Manual [4] Quectel_Module_Secondary_SMT_User_Guide Module Secondary SMT User Guide Table 34: Terms and Abbreviations Abbreviation Description AMR Adaptive Multi-rate bps
LTE Module EC20 Hardware Design EFR Enhanced Full Rate EGSM Extended GSM900 band (includes standard GSM900 band) ESD Electrostatic Discharge FDD Frequency Division Duplex FR Full Rate GLONASS GLObalnaya NAvigatsionnaya Sputnikovaya Sistema, the Russian Global Navigation Satellite System GMSK Gaussian Minimum Shift Keying GNSS Global Navigation Satellite System GPS Global Positioning System GSM Global System for Mobile Communications HR Half Rate HSPA High Speed Packet Access HSDPA
LTE Module EC20 Hardware Design PDU Protocol Data Unit PPP Point-to-Point Protocol QAM Quadrature Amplitude Modulation QPSK Quadrature Phase Shift Keying RF Radio Frequency RHCP Right Hand Circularly Polarized Rx Receive SIM Subscriber Identification Module SMS Short Message Service TDD Time Division Duplexing TDMA Time Division Multiple Access TD-SCDMA Time Division-Synchronous Code Division Multiple Access TX Transmitting Direction UL Uplink UMTS Universal Mobile Telecommunic
LTE Module EC20 Hardware Design VImin Absolute Minimum Input Voltage Value VOHmax Maximum Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value VSWR Voltage Standing Wave Ratio WCDMA Wideband Code Division Multiple Access EC20_Hardware_Design Confidential / Released 72 / 83
LTE Module EC20 Hardware Design 10 Appendix B GPRS Coding Scheme Table 35: Description of Different Coding Schemes Scheme CS-1 CS-2 CS-3 CS-4 Code Rate 1/2 2/3 3/4 1 USF 3 3 3 3 Pre-coded USF 3 6 6 12 Radio Block excl.USF and BCS 181 268 312 428 BCS 40 16 16 16 Tail 4 4 4 - Coded Bits 456 588 676 456 Punctured Bits 0 132 220 - Data Rate Kb/s 9.05 13.4 15.6 21.
LTE Module EC20 Hardware Design 11 Appendix C GPRS Multi-slot Class Twenty-nine classes of GPRS multi-slot modes are defined for MS in GPRS specification. Multi-slot classes are product dependant, and determine the maximum achievable data rates in both the uplink and downlink directions. Written as 3+1 or 2+2, the first number indicates the amount of downlink timeslots, while the second number indicates the amount of uplink timeslots.
UMTS/HSPA Module EC20 Hardware Design 12 Appendix D EDGE Modulation and Coding Scheme Table 37: EDGE Modulation and Coding Scheme Coding Scheme Modulation Coding Family 1 Timeslot 2 Timeslot 4 Timeslot CS-1: GMSK / 9.05kbps 18.1kbps 36.2kbps CS-2: GMSK / 13.4kbps 26.8kbps 53.6kbps CS-3: GMSK / 15.6kbps 31.2kbps 62.4kbps CS-4: GMSK / 21.4kbps 42.8kbps 85.6kbps MCS-1 GMSK C 8.80kbps 17.60kbps 35.20kbps MCS-2 GMSK B 11.2kbps 22.4kbps 44.8kbps MCS-3 GMSK A 14.
