August 2013 ENW89841A3KF Bluetooth QD ID:B021246 (End Product Listing) FCC ID: T7VEBMU IC ID: 216QEBMU PAN1322-SPP Intel’s BlueMoonUniversal Platform Wireless Modules User’s Manual Hardware Description Revision 1.
Edition 2013-08-14 Published by Panasonic Industrial Devices Europe GmbH Zeppelinstrasse 19 D-21337 Lüneburg, Germany © 2013 Panasonic Industrial Devices Europe GmbH All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics.
PAN1322-SPP ENW89841A3KF ENW89841A3KF - Intel’s BlueMoonTM Universal Platform Revision History: 2013-08-14, Revision 1.3 Previous Version: 1.2 Revision Subjects (major changes since last revision) Rev1.0 Initial Version from 2013-02-01 Rev1.1 Delete chapter 4.3, Update module picture on page 8, delete antenna reference list in chapter 9.1, update chapter 9.8 Rev1.2 Refer in chapter 1.7 FW Version to Appendix [2] Rev1.
PAN1322-SPP ENW89841A3KF Table of Contents Table of Contents Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAN1322-SPP ENW89841A3KF Table of Contents 7.3.3 7.3.4 7.4 7.4.1 7.4.1.1 Protection Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RF Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAN1322-SPP ENW89841A3KF List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Simplified Block Diagram of PAN1322-SPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Configuration for PAN1322-SPP in Top View (footprint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAN1322-SPP ENW89841A3KF List of Tables List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAN1322-SPP ENW89841A3KF General Device Overview 1 General Device Overview 1.1 Features General • • • • • • • • • Complete Bluetooth 2.1 + EDR solution Implements a single point-to-point data link to other SPP capable Bluetooth devices Ultra low power design in 0.13 μm CMOS Temperature range from -40°C to 85°C Integrates ARM7TDMI, RAM and patchable ROM On-module voltage regulators. External supply 2.9 - 4.
PAN1322-SPP ENW89841A3KF General Device Overview 1.2 Block Diagram PAN1322-SPP EEPROM Ceramic Antenna VDD1 I2C VDD_UART UART PMB8754 BlueMoon UniCellular GPIO Vsupply Balun Filter / Matching Voltage Regulator Crystal 26 MHz Figure 1 Simplified Block Diagram of PAN1322-SPP 1.3 Pin Configuration LGA F1 VSS F2 P1.2 TDI F3 P0.11 F4 LPMin P0.14 E1 P0.12 SDA0 E2 P0.13 SCL0 E3 P1.3 TDO E4 LPMout P0.0 E5 P0.1 D1 P0.10 D2 P0.8 D3 P1.1 TCK D4 P0.3 D5 P0.2 C1 VREG C2 P0.
PAN1322-SPP ENW89841A3KF General Device Overview 1.4 Pin Description The non-shaded cells indicate pins that will be fixed for the product lifetime. Shaded cells indicate that the pin might be removed/changed in future variants. Pins not listed below shall not be connected. Table 1 Pin Description Pin No. Symbol Input / Output Supply Voltage During Reset After Reset Function A2 P1.6 I/O/OD Internal1 Z Z Port 1.
PAN1322-SPP ENW89841A3KF General Device Overview Table 1 Pin Description Pin No. Symbol Input / Output Supply Voltage During Reset After Reset Function F4 P0.14 LPmin I/O VDDUART Z Z Port 0.14 LPM wakup input F5 P0.7 / UARTCTS I/O/OD VDDUART Z Z Port 0.7 or UART CTS flow control F7 P0.4 / UARTTXD I/O/OD VDDUART PU PU Port 0.4 or UART transmit data F8 P0.6 / UARTRTS I/O/OD VDDUART PU PU Port 0.
PAN1322-SPP ENW89841A3KF General Device Overview Descriptions of acronyms used in the pin list: Acronym Description I Input O Output OD Output with open drain capability Z Tristate PU Pull-up PD Pull-down A Analog (e.g. AI means analog input) S Supply (e.g. SO means supply output) User’s Manual Hardware Description 12 Revision 1.
PAN1322-SPP ENW89841A3KF General Device Overview 1.5 System Integration PAN1322-SPP is optimized for a low bill of material (BOM) and a small PCB size. Figure 3 shows a typical application example. HOST Keys, Leds UART RESET AT command interface GPIO SPP(Serial Port Profile ) Loaded Oscillator from EEPROM API RFCOMM EEPROM I2 C BT Stack BT Baseband Voltage BT RF Regulator BALUN Antenna VSUPPLY Example _Application_ PAN1311 .
PAN1322-SPP ENW89841A3KF General Device Overview The UART interface is used for communication between the host and PAN1322-SPP. The lines UARTTXD and UARTRXD are used for commands, events and data. The lines UARTRTS and UARTCTS are used for hardware flow control. Low power mode control of PAN1322-SPP and the host can be implemented in by using the pins P0.14 and P0.0. P0.14 is used by the host to allow PAN1322-SPP to enter low power mode and P0.
PAN1322-SPP ENW89841A3KF Basic Operating Information 2 Basic Operating Information 2.1 Power Supply PAN1322-SPP is supplied from a single supply voltage VSUPPLY. This supply voltage must always be present. The PAN1322-SPP chip is supplied from an internally generated 2.5 V supply voltage. This voltage can be accessed from the VREG pin. This voltage may not be used for supplying other components in the host system but can be used for referencing the host interfaces.
PAN1322-SPP ENW89841A3KF PAN1322-SPP Interfaces 3 PAN1322-SPP Interfaces 3.1 UART Interface The UART interface is the main communication interface between the host and PAN1322-SPP. AT commands are desribed in detail in the AT Commands specification [1]. The interface consists of four UART signals and two LPM control signals as shown in Figure 4. Host UARTTXD UARTRXD UARTRTS UARTCTS UARTTXD UARTRXD UARTRTS UARTCTS WAKEUP_BT WAKEUP_HOST Figure 4 UART Interface 3.1.1 UART PAN1322 P0.
PAN1322-SPP ENW89841A3KF PAN1322-SPP Interfaces Table 2 UART Baud Rates (cont’d) Wanted Baud Rate Real Baud Rate Deviation Error (%) 1843200 1857142 0.76 3250000 3250000 0 3.1.1.2 Detailed UART Behavior After reset the UART interface is configured with one start bit, eight data bits, no parity bit and one stop bit. The least significant bit is transmitted first. The polarity of the UART signals can be changed with the BD_DATA parameter UART_Invert.
PAN1322-SPP ENW89841A3KF General Device Capabilities 4 General Device Capabilities This chapter describes features available in the PAN1322 (ENW89841A3KF) core. Actual feature set and how to access the features can be found in the AT Command document [1]. Release specific performance characteristics, like data speed, is related in the SW Release Notes [2]. 4.1 RF Test Application The PAN1322 module can be programmed over UART with a specific application for RF test purposes, e.g.
PAN1322-SPP ENW89841A3KF Bluetooth Capabilities 6 Bluetooth Capabilities 6.1 Supported Features • • • • • • • • • • Bluetooth V2.1 + EDR compliant Enhanced Data Rate 2 and 3 Mbit/s symbol rate on the air Secure Simple Pairing Device A (initiating link) or Device B (accepting link) role supported Single point-to-point data link, role switch supported Packet data mode and stream data mode supported Link in sniff mode supported. Device enters Low Power Mode in sniff intervals if permitted by the host.
PAN1322-SPP ENW89841A3KF Bluetooth Capabilities 6.2.6 Encryption Pause and Resume Encryption Pause Resume is supported making it possible to change connection link key on an encrypted link, pause the encryption and resume it with the new link key. This is handled automatically by PAN1322-SPP to make the link more secure. User’s Manual Hardware Description 20 Revision 1.
PAN1322-SPP ENW89841A3KF Electrical Characteristics 7 Electrical Characteristics 7.1 Absolute Maximum Ratings Table 5 Absolute Maximum Ratings Parameter Values Symbol Unit Note / Test Condition Min. Typ. Max. Storage temperature -40 – 125 °C – VSUPPLY supply voltage -0.3 – 6.0 V – VDDUART supply voltage -0.9 – 4.0 V – VDD1 supply voltage -0.9 – 4.0 V – VREG -0.3 – 4.0 V VSUPPLY > 4 V VREG -0.3 – VSUPPLY V VSUPPLY < 4 V ONOFF -0.3 – VSUPPLY+0.
PAN1322-SPP ENW89841A3KF Electrical Characteristics 7.3 DC Characteristics 7.3.1 Pad Driver and Input Stages For more information, see Chapter 1.4. Table 7 Internal1 (1.5 V) Supplied Pins Parameter Values Symbol Unit Note / Test Condition Min. Typ. Max. Input low voltage -0.3 – 0.27 V – Input high voltage 1.15 – 3.6 V – Output low voltage – – 0.25 V IOL = 1 mA Output high voltage 1.
PAN1322-SPP ENW89841A3KF Electrical Characteristics Table 9 VDDUART Supplied Pins (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. Output low voltage – – 0.25 V IOL = 5 mA VDDUART = 2.5 V Output low voltage – – 0.15 V IOL = 2 mA VDDUART = 2.5 V Output high voltage VDDUART -0.25 – – V IOH = -5 mA VDDUART = 2.5 V Output high voltage VDDUART -0.15 – – V IOH = -2 mA VDDUART = 2.
PAN1322-SPP ENW89841A3KF Electrical Characteristics 7.3.2 Pull-ups and Pull-downs Table 12 Pull-up and Pull-down Currents Pin Pull Up Current Pull Down Current Unit Conditions Pull-up current measured with pin voltage = 0 V Min. Typ. Max. Min. Typ. Max. P0.12 P0.13 260 740 1300 N/A N/A N/A μA P0.0 P0.1 P0.2 P0.3 22 130 350 23 150 380 μA P0.4 P0.5 P0.6 P0.7 P0.10 P0.8 P0.9 P0.11 P0.14 P0.15 4.2 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 1.1 7.3.3 24 68 3.
PAN1322-SPP ENW89841A3KF Electrical Characteristics 7.3.4 System Power Consumption Table 13 Max. Load at the Different Supply Voltages Parameter Values Symbol Vsupply Unit Note / Test Condition Min. Typ. Max. – – 100 mA Peak current Note: I/O currents are not included since they depend mainly on external loads. For more details see [2]. 7.4 RF Part 7.4.1 Characteristics RF Part The characteristics involve the spread of values to be within the specific temperature range.
PAN1322-SPP ENW89841A3KF Electrical Characteristics Table 14 BDR - Transmitter Part (cont’d) Parameter Symbol Values Unit Note / Test Condition – Min. Typ. Max.
PAN1322-SPP ENW89841A3KF Electrical Characteristics Table 16 EDR - Transmitter Part Parameter Values Symbol Unit Note / Test Condition Min. Typ. Max. Output power (high gain) -2.5 – 2 dBm Relative transmit power: PxPSK - PGFSK -4 -0.
PAN1322-SPP ENW89841A3KF Electrical Characteristics Table 17 EDR -Receiver Part (cont’d) Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. DQPSK - C/I-performance: +2nd adjacent channel – -44 -30 dB – DQPSK - C/I-performance: +3rd adjacent channel – -50 -40 dB – 8DPSK - C/I-performance: -4th adjacent channel – -48 -33 dB – 8DPSK - C/I-performance: -3rd adjacent channel (1st adj.
PAN1322-SPP ENW89841A3KF Package Information 8 Package Information 8.1 Package Marking Please refer to “Ordering Information” on Page 18 Ordering Code Date Code FCC ID PAN1322 HW/SW Version ENW89841A3KF YYWWDLL FCC ID:T7VEBMU HW ± Hardware Version SW ± Software Version Machine readable 2D bar code Panasonic usage only, could be changed without any notice Package Marking 8.
PAN1322-SPP ENW89841A3KF Package Information 8.2.1 Pin Mark Pin 1 (A1) is marked on bottom footprint and on the top of the shield on the module according to Figure 8. Diameter of pin 1 mark on the shield is 0.40mm.
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification 9 Bluetooth Qualification and Regulatory Certification 9.1 Reference Design Figure 9 Reference Design Schematics User’s Manual Hardware Description 31 Revision 1.
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification ENW89841A3KF is intended to be installed inside end user equipment. ENW89841A3KF is Bluetoooth-qualified and also FCC-certified and Industry Canada approved, and conforms to R&TTE (European) requirements and directives with the reference design described in Figure 9.
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification If possible place PAN1322 in the center of main PCB. 8.7 min. 15mm min. 15mm min. 40mm Top View 15.6 Restricted Area No copper any layer PAN1322 Place PAN1322 at the edge of mother PCB. 3.00 5.00 All dimensions are in mm. Use a Ground plane in the area surrounding the PAN1322 module wherever possible.
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification 2. This device must accept any interference received, including interference that may cause undesired operation. 9.5 FCC Identifier FCC ID: T7VEBMU 9.6 European R&TTE Declaration of Conformity Hereby, Panasonic Industrial Devices Europe GmbH, declares that the Bluetooth module ENW89841A3KF is in compliance with the essential requirements and other relevant provisions of Directive 1999/5/EC.
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification Figure 12 Declaration of Conformity User’s Manual Hardware Description 35 Revision 1.
PAN1322-SPP ENW89841A3KF Bluetooth Qualification and Regulatory Certification 9.7 Bluetooth Qualified Design ID Panasonic has submitted End Product Listing (EPL) for PAN1322, based on Intel eBMU plattform, in the Qualified Product List of the Bluetooth SIG. These EPL are referring the Bluetooth qualfication of the SPP-AT application running on the eBMU chip under QD ID B021246. Manufacturers of Bluetooth devices incorporating PAN1322 can reference the same QD ID number.
PAN1322-SPP ENW89841A3KF Assembly Guidelines 10 Assembly Guidelines The target of this chapter is to provide guidelines for customers to successfully introduce the PAN1322-SPP module in production. This includes general description, PCB-design, solder printing process, assembly, soldering process, rework and inspection. 10.1 General Description of the Module PAN1322-SPP is a Land Grid Array (LGA 8.7mm x 15.6mm) module made for surface mounting. The pad diameter is 0.6 mm and the pitch 1.2 mm.
PAN1322-SPP ENW89841A3KF Assembly Guidelines If possible place PAN1322 in the center of main PCB. min. 15mm 8.7 min. 15mm min. 40mm Top View 15.6 Restricted Area No copper any layer PAN1322 Place PAN1322 at the edge of mother PCB. 3.00 5.00 All dimensions are in mm. Use a Ground plane in the area surrounding the PAN1322 module wherever possible.
PAN1322-SPP ENW89841A3KF Assembly Guidelines 10.3 Solder Paste Printing The solder paste deposited on the PCB by stencil printing has to be of eutectic or near eutectic tin leadfree / lead composition. A no-clean solder paste is preferred, since cleaning of the solder joints is difficult because of the small gap between the module and the PCB. Preferred thickness of the solder paste stencil is 100 - 127 µm (4 - 5 mils).
PAN1322-SPP ENW89841A3KF Assembly Guidelines 10.4.3 Package PAN1322 is packed in tape on reel according to Figure 16. Figure 16 Tape on Reel User’s Manual Hardware Description 40 Revision 1.
PAN1322-SPP ENW89841A3KF Assembly Guidelines 10.5 Soldering Profile Generally all standard reflow soldering processes (vapour phase, convection, infrared) and typical temperature profiles used for surface mount devices are suitable for the PAN1322 module. Wave soldering is not possible. Figure 17 and Figure 18 shows example of a suitable solder reflow profile. One for leaded and one for leadfree solder. Recommended temp. profile for reflow soldering 10 ±1s 30 +20/-10s 235°C max. Temp.
PAN1322-SPP ENW89841A3KF Assembly Guidelines At the reflow process each solder joint has to be exposed to temperatures above solder liquids for a sufficient time to get the optimum solder joint quality, whereas overheating the board with its components has to be avoided.
PAN1322-SPP ENW89841A3KF Assembly Guidelines 10.6.2.2 Alternative 2: Printing Solder To print solder on the module a fixture must be used. The purpose of the fixture is to get a flat surface and fix the stencil and module for printing. An example of how this fixture can be designed is shown in Figure 19. S older paste stencil T ooling pins C avity of the module Vacuum hol es Fixture B ottom S older _P rint ing . v s d Figure 19 1. 2. 3. 4. 5. 6. 7. 8. 9.
PAN1322-SPP ENW89841A3KF Assembly Guidelines 10.9 Voids in the Solder Joints 10.9.1 Expected Void Content and Reliability The content of voids is larger on LGA modules than for modules with BGA or leads. At a LGA solder joint the outgassing flux has a longer way to the surface of the solder and it has a relatively small surface to the air. The void content of the PAN1322 module conforms to IPC-A-610D (25% or less voiding area/area).
PAN1322-SPP ENW89841A3KF Assembly Guidelines Stencil thickness A thick solder paste stencil means more surface area to the air and thereby easier for the outgassing flux to leave the solder. Temperature soldering profile Too short preheat time means that the flux does not get enough time to react and flux get entrapped in the solder and create voids. Too long reflow time gives larger voids Too short reflow time gives a fraction of voids User’s Manual Hardware Description 45 Revision 1.
PAN1322-SPP ENW89841A3KF Terminology 11 Terminology A ACK Acknowledgement ACL Asynchronous Connection-oriented (logical transport) AFH Adaptive Frequency Hopping AHS Adaptive Hop Sequence ARQ Automatic Repeat reQuest B b bit/bits (e.g. kb/s) B Byte/Bytes (e.g.
PAN1322-SPP ENW89841A3KF Terminology E EDR Enhanced Data Rate EEPROM Electrically Erasable Programmable Read Only Memory eSCO Extended Synchronous Connection-Oriented (logical transport) EV Extended Voice (packet type) F FEC Forward Error Correction FHS Frequency Hop Synchronization (packet) FIFO First In First Out (buffer) FM Frequency Modulation FW Firmware G GFSK Gaussian Frequency Shift Keying (modulation) GPIO General Purpose Input/Output GSM Global System for Mobile communic
PAN1322-SPP ENW89841A3KF Terminology LSB Least Significant Bit/Byte LT_ADDR Logical Transport Address M MSB Most Significant Bit/Byte MSRS Master-Slave Role Switch N NC No Connection NOP No OPeration NVM Non-Volatile Memory O OCF Opcode Command Field OGF Opcode Group Field P PA Power Amplifier PCB Printed Circuit Board PCM Pulse Coded Modulation PDU Protocol Data Unit PER Packet Error Rate PIN Personal Identification Number PLC Packet Loss Concealment PLL Phase Locked Lo
PAN1322-SPP ENW89841A3KF Terminology T TBD To Be Determined TCK Test Clock (JTAG signal) TDI Test Data In (JTAG signal) TDO Test Data Out (JTAG signal) TL Transport Layer TMS Test Mode Select (JTAG signal) TX Transmit TXD Transmit Data (UART signal) U UART Universal Asynchronous Receiver & Transmitter ULPM Ultra Low Power Mode V VCO Voltage Controlled Oscillator W WLAN Wireless LAN (Local Area Network) User’s Manual Hardware Description 49 Revision 1.
PAN1322-SPP ENW89841A3KF References 12 References [1] Intel AT Command Specification (eUniStone_1.00_UM_SD.pdf) Always the latest revisionwill be available under the link below (SPP-AT User’s Manual) [2] Release Notes for SPP AT application Software (SW) (eUniStone_1.00_SW_3.1_RN.pdf) Always the latest revision will be available under the link below, please refer also to Table 2 “Firmware Releases as of 2013-05-14” on Page 14.
PAN1322-SPP ENW89841A3KF References User’s Manual Hardware Description 51 Revision 1.
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