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DATA SHEET

Product specification

Supersedes data of 2000 Feb 09

2000 Jul 31

INTEGRATED CIRCUITS

UDA1334ATS

Low power audio DAC with PLL

Summary of content (22 pages)

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INTEGRATED CIRCUITS DATA SHEET UDA1334ATS Low power audio DAC with PLL Product specification Supersedes data of 2000 Feb 09 2000 Jul 31
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS CONTENTS 1 FEATURES 1.1 1.2 1.3 1.4 1.5 General Multiple format data interface DAC digital features Advanced audio configuration PLL system clock generation 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.1.1 8.1.2 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.
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NXP Semiconductors Product specification Low power audio DAC with PLL 1 UDA1334ATS FEATURES 1.1 General • 2.4 to 3.6 V power supply voltage • On-board PLL to generate the internal system clock: – Operates as an asynchronous DAC, regenerating the internal clock from the WS signal (called audio mode) – Generates audio related system clock (output) based on 32, 48 or 96 kHz sampling frequency (called video mode).
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NXP Semiconductors Product specification Low power audio DAC with PLL 5 UDA1334ATS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA DAC analog supply voltage VDDD digital supply voltage IDDA DAC analog supply current IDDD Tamb digital supply current 2.4 3.0 3.6 V 2.4 3.0 3.6 V audio mode − 3.5 − mA video mode − 3.5 − mA audio mode − 2.5 − mA video mode − 4.
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NXP Semiconductors Product specification Low power audio DAC with PLL 6 UDA1334ATS BLOCK DIAGRAM VSSD VDDD handbook, full pagewidth 4 BCK WS DATAI 1 2 3 5 DIGITAL INTERFACE MUTE DEEM/CLKOUT 10 PLL DE-EMPHASIS UDA1334ATS SYSCLK/PLL1 PLL0 6 7 8 11 INTERPOLATION FILTER 9 SFOR1 SFOR0 NOISE SHAPER VOUTL DAC DAC 14 13 15 VDDA VSSA Fig.1 Block diagram.
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NXP Semiconductors Product specification Low power audio DAC with PLL 7 UDA1334ATS PINNING SYMBOL PIN PAD TYPE DESCRIPTION BCK 1 5 V tolerant digital input pad bit clock input WS 2 5 V tolerant digital input pad word select input DATAI 3 5 V tolerant digital input pad serial data input VDDD 4 digital supply pad digital supply voltage VSSD 5 digital ground pad digital ground SYSCLK/PLL1 6 5 V tolerant digital input pad system clock input in video mode/PLL mode control 1 input i
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NXP Semiconductors Product specification Low power audio DAC with PLL 8 UDA1334ATS FUNCTIONAL DESCRIPTION 8.1 Table 2 System clock The UDA1334ATS incorporates a PLL capable of generating the system clock. The UDA1334ATS can operate in 2 modes: • It operates as an asynchronous DAC, which means the device regenerates the internal clocks using a PLL from the incoming WS signal. This mode is called audio mode. Clock output selection in video mode PLL0 SELECTION MID 12.
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NXP Semiconductors Product specification Low power audio DAC with PLL 8.4 UDA1334ATS Filter stream DAC 8.5 The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved.
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NXP Semiconductors Product specification Low power audio DAC with PLL 8.6 UDA1334ATS Feature settings 8.6.1 DE-EMPHASIS CONTROL 8.6.2 This function is only available in audio mode. In that case, pin DEEM/CLKOUT can be used to activate the digital de-emphasis for 44.1 kHz as given in Table 5. DIGITAL INTERFACE FORMAT SELECT The digital audio interface formats (see Fig.5) can be selected via pins SFOR1 and SFOR0 as shown in Table 4.
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2 >=8 3 1 2 3 MSB B2 >=8 DATA MSB B2 MSB I2S-BUS FORMAT WS LEFT RIGHT 16 15 1 16 B15 LSB MSB 2 15 2 1 BCK DATA MSB B2 B2 B15 LSB NXP Semiconductors 1 BCK Low power audio DAC with PLL handbook, full pagewidth 2000 Jul 31 RIGHT LEFT WS LSB-JUSTIFIED FORMAT 16 BITS 10 WS LEFT 20 RIGHT 19 18 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 2 1 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS WS LEFT 24 23 22
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT − 4.
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NXP Semiconductors Product specification Low power audio DAC with PLL SYMBOL PARAMETER UDA1334ATS CONDITIONS MIN. TYP. MAX. UNIT Digital input pins: TTL compatible VIH HIGH-level input voltage 2.0 − 5.0 V VIL LOW-level input voltage −0.5 − +0.8 V ⎪ILI⎪ input leakage current − − 1 μA Ci input capacitance − − 10 pF 3-level input: pin PLL0 VIH HIGH-level input voltage 0.9VDDD − VDDD + 0.5 V VIM MID-level input voltage 0.4VDDD − 0.
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NXP Semiconductors Product specification Low power audio DAC with PLL SYMBOL UDA1334ATS PARAMETER S/N signal-to-noise ratio αCS channel separation PSRR power supply rejection ratio CONDITIONS TYP. fs = 44.1 kHz; code = 0; A-weighted 100 fs = 96 kHz; code = 0; A-weighted fripple = 1 kHz; Vripple = 30 mV (p-p) UNIT dB 98 dB 100 dB 60 dB Note 1. The output voltage of the DAC scales proportionally to the analog power supply voltage. 14.2 Timing VDDD = VDDA = 2.4 to 3.
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS t CWH handbook, full pagewidth MGR984 t CWL Tsys Fig.6 Output clock timing. handbook, full pagewidth WS th(WS) tBCKH tr tsu(WS) tf BCK tsu(DATAI) tBCKL Tcy(BCK) th(DATAI) DATAI MGL880 Fig.7 Serial interface timing.
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 15 APPLICATION INFORMATION digital supply voltage analog supply voltage handbook, full pagewidth R7 1Ω C9 SYSCLK/PLL1 47 μF (16 V) 47 μF (16 V) C10 C6 100 nF (63 V) VSSA 100 nF (63 V) 15 VDDA 13 R6 1Ω C5 VSSD 5 VDDD 4 6 14 BCK WS DATAI SFOR1 SFOR0 MUTE DEEM/CLKOUT PLL0 VOUTL C3 47 μF (16 V) 1 2 R3 R1 220 kΩ C1 3 7 11 UDA1334ATS 16 8 9 VOUTR C4 47 μF (16 V) 12 left output 100 Ω 10 nF (63 V)
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS digital supply voltage analog supply voltage R7 1Ω C9 27 MHz clock R5 SYSCLK/PLL1 47 Ω 47 μF (16 V) 47 μF (16 V) C10 C6 100 nF (63 V) VSSA 100 nF (63 V) 15 R6 1Ω C5 VDDA VSSD 13 5 VDDD 4 6 14 BCK WS DATAI I2S-bus (master) SFOR1 SFOR0 VOUTL C3 47 μF (16 V) 1 2 MUTE audio clock PLL0 R1 220 kΩ C1 3 7 11 UDA1334ATS 16 VOUTR C4 47 μF (16 V) MPEG DECODER DEEM/CLKOUT R3 8 9 12 left output 10
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 16 PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.3 5.1 4.
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 17 SOLDERING 17.1 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology.
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NXP Semiconductors Product specification Low power audio DAC with PLL 17.5 UDA1334ATS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1.
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS 18 DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1.
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NXP Semiconductors Product specification Low power audio DAC with PLL UDA1334ATS Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted.
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NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version.