SC18IS602/602B/603 I2C-bus to SPI bridge Rev. 04 — 11 March 2008 Product data sheet 1. General description The SC18IS602/602B and SC18IS603 are designed to serve as an interface between a standard I2C-bus of a microcontroller and an SPI bus. This allows the microcontroller to communicate directly with SPI devices through its I2C-bus. The SC18IS602/602B/603 operates as an I2C-bus slave-transmitter or slave-receiver and an SPI master.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 4. Ordering information Table 1. Ordering information Type number Package Name Description Version SC18IS602IPW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 SC18IS602BIPW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 SC18IS603IPW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 5.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 6. Pinning information 6.1 Pinning SS0/GPIO0 1 16 A2 SS0/GPIO0 1 16 A2 SS1/GPIO1 2 15 A1 SS1/GPIO1 2 15 A1 RESET 3 14 A0 RESET 3 14 A0 VSS 4 13 SS3/GPIO3 VSS 4 MISO 5 MISO 5 MOSI 6 12 VDD 11 SPICLK MOSI 6 11 SPICLK SDA 7 10 SS2/GPIO2 SDA 7 10 SS2/GPIO2 SCL 8 SCL 8 SC18IS602IPW SC18IS602BIPW 9 INT 002aac441 12 VDD 9 INT 002aac442 a. SC18IS602/602B Fig 3. 13 CLKIN SC18IS603IPW b.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 7. Functional description The SC18IS602/602B/603 acts as a bridge between an I2C-bus and an SPI interface. It allows an I2C-bus master device to communicate with any SPI-enabled device. 7.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 7.1.1 Addressing R/W slave address 0 1 0 1 fixed A2 A1 A0 X programmable 002aac446 Fig 5. Slave address The first seven bits of the first byte sent after a START condition defines the slave address of the device being accessed on the bus. The eighth bit determines the direction of the message. A ‘0’ in the least significant position of the first byte means that the master will write information to a selected slave.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge the Function ID. There is no restriction on the number or combination of Slave Selects that can be enabled for an SPI message. If more than one SSn pin is enabled at one time, the user should be aware of possible contention on the data outputs of the SPI slave devices. Table 3. Function ID 01h to 0Fh 7 6 0 5 0 0 4 3 2 1 0 0 SS3[1] SS2[2] SS1 SS0 [1] SS3 does not exist in the SC18IS603.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 7.1.5 Configure SPI Interface - Function ID F0h The SPI hardware operating mode, data direction, and frequency can be changed by sending a ‘Configure SPI Interface’ command to the I2C-bus. S SLAVE ADDRESS W A A F0h A DATA P 002aac450 Fig 10.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 7.1.6 Clear Interrupt - Function ID F1h An interrupt is generated by the SC18IS602/602B/603 after any SPI transmission has been completed. This interrupt can be cleared (INT pin HIGH) by sending a ‘Clear Interrupt’ command. It is not necessary to clear the interrupt; when polling the device, this function may be ignored. S SLAVE ADDRESS W A F1h A P 002aac452 Fig 11. Clear Interrupt 7.1.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 7.1.9 GPIO Read - Function ID F5h The state of the pins defined as GPIO may be read into the SC18IS602/602B/603 data buffer using the GPIO Read function. S SLAVE ADDRESS W A A F5h DATA A P 002aac455 Fig 14. GPIO Read Note that this function does not return the value of the GPIO. To receive the GPIO contents, a one-byte Read Buffer command would be required. The value of the Read Buffer command will return the following byte. Table 7.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 7.1.11 GPIO Configuration - Function ID F7h The pins defined as GPIO may be configured by software to one of four types on a pin-by-pin basis. These are: quasi-bidirectional, push-pull, open-drain, and input-only. Two bits select the output type for each port pin. Table 9. GPIO Configuration (F7h) bit allocation 7 6 5 4 3 2 1 0 SS3.1[1] SS3.0[1] SS2.1 SS2.0 SS1.1 SS1.0 SS0.1 SS0.0 [1] SS3.1 and SS3.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled LOW by an external device, the weak pull-up turns off, and only the very weak pull-up remains on.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge GPIO pin pin latch data VSS input data glitch rejection 002aab883 Fig 17. Open-drain output configuration 7.1.11.3 Input-only configuration The input-only pin configuration is shown in Figure 18. It is a Schmitt-triggered input that also has a glitch suppression circuit. input data GPIO pin glitch rejection 002aab884 Fig 18. Input-only configuration 7.1.11.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 7.2 External clock input (SC18IS603) In this device, the processor clock is derived from an external source driving the CLKIN pin. The rate may be from 0 Hz up to 18 MHz. Using the external clock allows higher frequencies from the SPI interface, thus the SPI Master operating can be up to 4 Mbit/s.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 8. I2C-bus to SPI communications example The following example describes a typical sequence of events required to read the contents of an SPI-based EEPROM. This example assumes that the SC18IS602/602B/603 is configured to respond to address 50h. A START condition is shown as ‘ST’, while a STOP condition is ‘SP’. The data is presented in hexadecimal format. 1. The first message is used to configure the SPI port for mode and frequency.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge You can see that on the I2C-bus the first four bytes do not contain the data from the SPI bus. The first byte is the SC18IS60x address, followed by three dummy data bytes. These dummy data bytes correspond to the three bytes sent to the EEPROM before it actually places data on the bus (command 03h, subaddress 0030h). 9. Limiting values Table 11. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 10. Static characteristics Table 12. Static characteristics VDD = 2.4 V to 3.6 V; Tamb = −40 °C to +85 °C (industrial); unless otherwise specified. Symbol Parameter Conditions IDD(oper) operating supply current VDD = 3.6 V IDD(idle) Idle mode supply current Min Typ[1] Max Unit f = 7.3728 MHz - 5.6 6.7 mA f = 12 MHz - 7 13 mA f = 18 MHz - 11 16 mA VDD = 3.6 V f = 7.3728 MHz - 3.3 3.9 mA f = 12 MHz - 3.6 4.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 11. Dynamic characteristics Table 13. Dynamic characteristics VDD = 2.4 V to 3.6 V; Tamb = −40 °C to +85 °C (industrial); unless otherwise specified. Symbol fosc(RC) Parameter internal RC oscillator frequency Conditions Variable clock nominal f = 7.3728 MHz; trimmed to ±1 % at Tamb = 25 °C fosc = 12 MHz Min Max Min Max 7.189 7.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge TCLCL tSPIF SPICLK (CPOL = 0) (output) tSPIR tSPICLKH tSPICLKL tSPICLKL tSPICLKH tSPIF tSPIR SPICLK (CPOL = 1) (output) tSPIDSU MISO (input) tSPIDH MSB/LSB in LSB/MSB in tSPIDV tSPIOH tSPIDV tSPIR tSPIF MOSI (output) master MSB/LSB out master LSB/MSB out 002aac457 Fig 20.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 12. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 13.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 24. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 16.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 15. Revision history Table 17. Revision history Document ID Release date SC18IS602_602B_603_4 20080311 Modifications: • • • Data sheet status Change notice Supersedes Product data sheet - SC18IS602_603_3 added Type number SC18IS602BIPW Section 1 “General description”, 2nd paragraph: added second sentence.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
SC18IS602/602B/603 NXP Semiconductors I2C-bus to SPI bridge 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . .