Freescale Semiconductor Document Number: MC13892 Rev. 18.0, 10/2012 Power Management Integrated Circuit (PMIC) for i.MX35/51 13892 The MC13892 is a Power Management Integrated Circuit (PMIC) designed specifically for use with the Freescale i.MX35 and i.MX51 families. It is also compatible with the i.MX27, i.MX31, and i.MX37 application processors targeting netbooks, ebooks, smart mobile devices, smart phones, personal media players, and portable navigation devices.
DEVICE VARIATIONS DEVICE VARIATIONS Table 1. MC13892 Device Variations Part Number(1) Notes MC13892CJVK (2) MC13892AJVK (3) MC13892DJVK (2) (4) MC13892BJVK (3) MC13892VK (3) MC13892JVK (3) MC13892CJVL (2) MC13892AJVL (3) MC13892DJVL (2) (4) MC13892BJVL (3) MC13892VL (3) MC13892JVL (3) Notes 1. 2. 3. 4.
INTERNAL BLOCK DIAGRAM Charger Interface and Control: 4 bit DAC, Clamp, Protection, Trickle Generation Battery Interface & Protection GNDLED LEDR LEDG LEDB GNDBL LEDKP LEDAD LEDMD GNDCHRG CHRGSE1B CHRGLED CHRGRAW CHRGCTRL1 CHRGISNS CHRGCTRL2 BPSNS BP BATTFET BATT BATTISNS INTERNAL BLOCK DIAGRAM Tri-Color LED Drive Backlight LED Drive PWR Gate Drive & Chg Pump PWGTDRV1 PWGTDRV2 LICELL, UID, Die Temp, GPO4 GNDADC ADIN5 Voltage / Current Sensing & Translation SW1 1050 mA Buck ADIN6
PIN CONNECTIONS PIN CONNECTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 A VUSB2 VUSB2 VINUSB2 SWBSTIN GNDSWBST GNDBL NC MODE VCORE BATT CHRGRAW CHRGCTRL2 CHRGCTRL2 B VUSB2 GPO1 DVS2 SWBSTOUT LEDB LEDKP LEDR GNDCORE VCOREDIG BP CHRGCTRL1 BATTISNSCC CHRGCTRL2 Regulators C VINPLL VSDDRV CHRGISNS BATTISNS Switchers D VUSB VSD SWBSTFB LEDMD DVS1 REFCORE CHRGSE1B LICELL BATTFET BPSNS PWRON1 E UVBUS VPLL LEDG GNDLED UID PUMS2 GNDCHRG CHRGLED PWRON2 ADTRI
PIN CONNECTIONS 1 A 2 3 4 5 6 7 8 9 10 11 12 13 VUSB2 VINUSB2 SWBSTOUT SWBSTIN GNDSUB NC MODE VCORE BATT CHRGRAW CHRGCTRL2 CHRGISNS 14 Regulators B VSDDRV GPO1 GNDSUB GNDSUB LEDR UID DVS1 REFCORE GNDCORE CHRGSE1B BP GNDCHRG BATTISNSCC BATTISNS Switchers C VSD DVS2 SWBSTFB LEDB LEDG LEDKP LEDAD PUMS2 VCOREDIG LICELL BATTFET BPSNS GPO3 PUMS1 Backlights D VUSB VPLL GNDSUB GNDSUB GNDSWBST GNDLED LEDMD GNDBL CHRGCTRL1 CHRGLED PWRON1 PWRON3
PIN CONNECTIONS Table 2. MC13892 Pin Definitions A functional description of each pin can be found in the Functional Description. Pin Number Pin Number on on the the 13982VL 13982VK 12x12 mm 7x7 mm Pin Name Rating Pin Function (V) Formal Name Definition Output regulator for USB PHY A1, A2, B1 A2 VUSB2 3.6 Output USB 2 Supply A3 A3 VINUSB2 5.5 Power USB 2 Supply Input A4 A5 SWBSTIN 5.
PIN CONNECTIONS Table 2. MC13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description. Pin Number Pin Number on on the the 13982VL 13982VK 12x12 mm 7x7 mm Pin Name Rating Pin Function (V) Formal Name Definition USB transceiver regulator output D1 D1 VUSB 3.6 Output USB Supply D2 C1 VSD 3.6 Output SD Card Supply Output regulator SD card D4 C3 SWBSTFB 3.
PIN CONNECTIONS Table 2. MC13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description.
PIN CONNECTIONS Table 2. MC13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description. Pin Number Pin Number on on the the 13982VL 13982VK 12x12 mm 7x7 mm Pin Name Rating Pin Function (V) Formal Name Definition Switcher 1 feedback H10 G12 SW1FB 3.6 Input Switcher 1 Feedback H12 L12 STANDBYSEC 3.6 Input Secondary Standby Signal H13 J13, J14 SW2IN 5.5 Input Switcher 2 Input Input voltage for Switcher 2 J1 J1, J2 SW4IN 5.
PIN CONNECTIONS Table 2. MC13892 Pin Definitions (continued) A functional description of each pin can be found in the Functional Description. Pin Number Pin Number on on the the 13982VL 13982VK 12x12 mm 7x7 mm Pin Name Rating Pin Function (V) Formal Name Definition Output regulator for SRTC module on processor M4 M5 VSRTC 3.6 Output SRTC Supply M5 P6 GNDRTC – Ground Real Time Clock Ground M6 M7 VINCAMDRV 5.5 I/O M7 N8 PWGTDRV2 4.8 Output Power Gate Driver 2 M8 L9 VDIG 3.
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit Charger and USB Input Voltage(5) VCHRGR -0.3 to 20 V MODE pin Voltage VMODE -0.3 to 9.0 V VLEDMD, VLEDAD, VLEDKP -0.3 to 28 V VBATT -0.3 to 4.8 V VLICELL -0.3 to 3.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit 1.1 – 1.3 V 0.0 – 0.3* SPIVCC 0.7* SPIVCC – 3.1 0.0 – 0.2 VCORE- 0.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max 1.2 – 4.65 1.8 – 2.0 0.0 – 0.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max 3.0 2.8 UVDET – – – 4.65 4.65 4.65 0.6 0.6 – – 1.375 1.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max – 50 – – – – – – – 75 85 78 82 78 82 – – – – – – -20% -30% – -35% -35% 5.0 1.0 2.2 1.5 – 10 2x22 – 4.7 +20% +30% 0.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit 300 – – – – 500 SWBSTEFF – 80 – % LBST R_WBST ILSAT COBST ESRBST CBSTD IBSTDPK IBSTDPK -20% – 1.0 -60% 1.0 1.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VNOM -3% VNOM VNOM +3% IVIDEOLO 0.0 – 3.0 Operating Input Voltage Range VINMIN to VINMAX VAUDIO VNOM+0.25 – 4.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max VNOM -3% VNOM VNOM +3% – – 0.35 – 5.0 8.0 VNOM +0.25 – 4.65 0.0 0.0 – – 65 250 0.65 1.1 2.2 2.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit VNOM - 3% VNOM VNOM + 3% – – 0.25 – 5.0 8.0 ILMAX+20% – – VNOM -3% VNOM VNOM +3% 0.0 – 3.0 4.4 – 5.0 – 5.25 5.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max VNOM -3% VNOM VNOM + 3% – – 0.35 – 5.0 8.0 4.75 5.0 5.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max VNOM - 0.05 VNOM -3% VNOM VNOM VNOM + 0.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max VNOM -3% VNOM VNOM + 3% – – 0.40 – 5.0 9.
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions - 40 °C ≤ TA ≤ 85 °C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit 4.4 5.0 5.25 V 0.0 -1.2 – – 2.4 1.
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.65 V, -40 ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit – – 1.0 – – – – 22 11 High Z 44 – – – – – 22 – 45 – 55 – – – – 11 6.
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.65 V, -40 ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.65 V, -40 ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit 35 50 40 60 – – – – 20 1.0 – – – – 1.0 0.1 – 10 – 1.0 2.0 – 5.0 8.0 – – 10 – 1.0 2.
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.65 V, -40 ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted.
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.65 V, -40 ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit – – 100 – – 1.3 35 50 40 60 – – – – – -115 -126 -132 – – – – – 1.0 0.1 – 10 – – 1.0 – 3.
ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 3.1 V ≤ BATT ≤ 4.65 V, -40 ≤ TA ≤ 85 °C, GND = 0 V, unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25 °C under nominal conditions, unless otherwise noted. Characteristic Symbol Min Typ Max Unit – – 100 – 1.0 2.0 35 45 40 50 – – – – 20 1.0 – – – – 1.0 0.1 – 5.0 – – 1.0 – 2.
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CHARGER CHRGRAW 1. Charger input. The charger voltage is measured through an ADC at this pin. The UVBUS pin must be shorted to CHRGRAW in cases where the charger is being supplied from the USB cable. The minimum voltage for this pin depends on BATTMIN threshold value (see Battery Interface and Control). 2. Output to battery supplied accessories.
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CFP AND CFM Accumulated current filter cap plus and minus pins respectively. The coulomb counter will require a 10 µF output capacitor connected between these pins to perform a first order filtering of the signal across R1. CHRGSE1B An unregulated wall charger configuration can be built in which case this pin must be pulled low. When charging through USB, it can be left open since it is internally pulled up to VCORE.
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION SWITCHERS SW1IN, SW2IN, SW3IN AND SW4IN Switchers 1, 2, 3, and 4 input. Connect these pins to BP to supply Switchers 1, 2, 3, and 4. SW1FB, SW2FB, SW3FB AND SW4FB Switchers 1, 2, 3, and 4 feedback. Switchers 1, 2, 3, and 4 output voltage sense respectively. Connect these pins to the farther point of each of their respective SWxOUT pin, in order to sense and maintain voltage stability. SW1OUT Switcher 1 output. Buck regulator for processor core(s).
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION REGULATORS VINIOHI Input of VIOHI regulator. Connect this pin to BP in order to supply VIOHI regulator. VIOHI Output regulator for high voltage IO. Fixed 2.775 V output for high-voltage level interface. VINPLL AND VINDIG The input of the regulator for processor PLL and Digital regulators respectively. VINDIG and VINPLL can be connected to either BP or a 1.
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION VGEN1DRV Drive output for the VGEN1 external PNP transistor. VGEN1 Output of general purpose 1 regulator. VGEN2DRV Drive output for the VGEN2 external PNP transistor. VGEN2 Output of general purpose 2 regulator. VINGEN3DRV 1. Input for the VGEN3 regulator when no external PNP transistor used. Typically connected to BP. 2. Drive output for VGEN3 in case an external PNP transistor is used on the application.
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CONTROL LOGIC LICELL Coin cell supply input and charger output. The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e., during a power cut), the RTC system and coin cell maintained logic will switch over to the LICELL for backup power. This pin also works as a current-limited voltage source for battery charging.
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION PWRON1, 2 AND 3 A turn on event can be accomplished by connecting an open drain NMOS driver to the PWRONx pin of the MC13892, so that it is in effect a parallel path for the power key. In addition to the turn on event, the MC13892A/B/C/D versions include a global reset feature on the PWRON3 pin. On the A/B/C/D versions, the GLBRSTENB defaults to 0. In the MC13892A/C versions global reset is active low.
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CLK Primary SPI clock input. In I2C mode, this pin is the SCL signal (I2C bus clock). MOSI Primary SPI write input. In I2C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses (A0 address selection). MISO Primary SPI read output. In I2C mode, this pin is the SDA signal (bi-directional serial data line). GNDSPI Ground for SPI interface.
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION ADIN7 ADC generic input channel 7, group 1. ADIN7 may be used as a general purpose unscaled input or as a divide by 2 scaled input. In a typical application, an ambient light sensor is connected here. A second general purpose input ADIN7B is available on channel 7. This input is muxed on the GPO4 pin. In the application, a second ambient light sensor is supposed to be connected here.
FUNCTIONAL DEVICE OPERATION PROGRAMMABILITY FUNCTIONAL DEVICE OPERATION PROGRAMMABILITY INTERFACING OVERVIEW AND CONFIGURATION OPTIONS The MC13892 contains a number of programmable registers for control and communication. The majority of registers are accessed through a SPI interface in a typical application. The same register set may alternatively be accessed with an I2C interface that is muxed on SPI pins. The following table describes the muxed pin options for the SPI and I2C interfaces.
FUNCTIONAL DEVICE OPERATION PROGRAMMABILITY Table 8. Register Set Register Register Register Register 12 Unused 28 Switchers 4 44 ADC 1 60 Test 1 13 Power Control 0 29 Switchers 5 45 ADC 2 61 Test 2 14 Power Control 1 30 Regulator Setting 0 46 ADC 3 62 Test 3 15 Power Control 2 31 Regulator Setting 1 47 ADC4 63 Test 4 The SPI interface is comprised of the package pins listed in Table 9. Table 9.
FUNCTIONAL DEVICE OPERATION PROGRAMMABILITY Figure 6. SPI Transfer Protocol Multiple Read/Write Access SPI ELECTRICAL & TIMING REQUIREMENTS The following diagram and table summarize the SPI electrical and timing requirements. The SPI input and output levels are set independently via the SPIVCC pin by connecting it to the desired supply. This would typically be tied to SW4 programmed for 1.80 V. The strength of the MISO driver is programmable through the SPIDRV[1:0] bits. Figure 7.
FUNCTIONAL DEVICE OPERATION PROGRAMMABILITY Table 10.
FUNCTIONAL DEVICE OPERATION I2C INTERFACE I2C INTERFACE I2C CONFIGURATION When configured for I2C mode (see Table 7) the interface may be used to access the complete register map previously described for SPI access. The MC13892 can function only as an I2C slave device, not as a host. I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus.
FUNCTIONAL DEVICE OPERATION I2C INTERFACE increments separated by an ACK. Read operations also begin with the MSB, and 3 bytes will be sent out unless a STOP command or NACK is received prior to completion. The following examples show how to write and read data to the IC. The host initiates and terminates all communication. The host sends a master command packet after driving the start condition. The device will respond to the host if the master command packet contains the corresponding slave address.
FUNCTIONAL DEVICE OPERATION I2C INTERFACE INTERRUPT HANDLING CONTROL The MC13892 has interrupt generation capability to inform the system on important events occurring. An interrupt is signaled to the processor by driving the INT pin high. This is true whether the communication interface is configured for the SPI or I2C. Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared.
FUNCTIONAL DEVICE OPERATION I2C INTERFACE Table 12. Interrupt, Mask and Sense Bits Interrupt LOBATHI Mask LOBATHM Sense LOBATHS Purpose Low battery warning Sense is 1 if above LOBATH threshold. Trigger DebounceTi me Section Dual 30 μs page 54 page 111 VBUSVALIDI VBUSVALIDM VBUSVALIDS Detects A-Session Valid on VBUS Dual L2H: 2024 ms H2L: 812 ms IDFLOATI IDFLOATM IDFLOATS ID floating detect.
FUNCTIONAL DEVICE OPERATION I2C INTERFACE Table 13. Additional Sense Bits Sense Description Section MODES[1:0] 00 = MODE grounded 10 = MODE to VCOREDIG 11 = MODE to VCORE page 40 PUMSxS[1:0] 00 = PUMS grounded 01 = PUMS open 10 = PUMS to VCOREDIG 11 = PUMS to VCORE page 54 CHRGSSS 0 = Single path 1 = Serial path page 89 SPECIFIC REGISTERS IDENTIFICATION The MC13892 parts can be identified though identification bits which are hardwired on chip.
FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK CLOCK GENERATION AND REAL TIME CLOCK CLOCK GENERATION The MC13892 generates a 32.768 kHz clock as well as several 32.768 kHz derivative clocks that are used internally for control. Support is also provided for an external Secure Real Time Clock (SRTC) which may be integrated on a companion system processor IC.
FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK Table 16. Crystal Oscillator Main Characteristics Parameter Condition Min Typ Max Units Operating Voltage Oscillator and RTC Block from BP 1.2 – 4.65 Coin cell Disconnect Threshold At LICELL 1.8 – 2.0 V RTC oscillator startup time Upon application of power - – 1.0 sec XTAL1 Input Level External clock source 0.3 – - VPP XTAL1 Input Range External clock source -0.5 – 1.
FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK Figure 10. SRTC block diagram VSRTC The VSRTC regulator provides the CLK32KMCU output level. It is also used to bias the Low-power SRTC domain of the SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected. The VSRTC cannot be disabled. Table 17.
FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK TIME OF DAY ALARM A Time Of Day Alarm (TODA) function can be used to turn on the application and alert the processor. If the application is already on, the processor will be interrupted. The TODA and DAYA registers are used to set the alarm time. Only a single alarm can be programmed at a time. When the TOD counter is equal to the value in TODA, and the DAY counter is equal to the value in DAYA, the TODAI interrupt will be generated.
FUNCTIONAL DEVICE OPERATION CLOCK GENERATION AND REAL TIME CLOCK data that has been provided, so occasional refreshing is recommended to ensure that any drift influencing environmental factors have not skewed the clock beyond desired tolerances. COIN CELL BATTERY BACKUP The LICELL pin provides a connection for a coin cell backup battery or supercap. If the main battery is deeply discharged, removed, or contact-bounced (i.e.
FUNCTIONAL DEVICE OPERATION POWER CONTROL SYSTEM POWER CONTROL SYSTEM INTERFACE The power control system on the MC13892 interfaces with the processor via different IO signals and the SPI/I2C bus. It also uses on chip signals and detector outputs. Table 22 gives a listing of the principal elements of this interface. Table 22.
FUNCTIONAL DEVICE OPERATION POWER CONTROL SYSTEM Table 22.
FUNCTIONAL DEVICE OPERATION OPERATING MODES OPERATING MODES POWER CONTROL STATE MACHINE Figure 11 shows the flow of the power control state machine. This diagram serves as the basis for the description in the remainder of this chapter. Figure 11.
FUNCTIONAL DEVICE OPERATION OPERATING MODES POWER CONTROL MODES DESCRIPTION Following are text descriptions of the power states of the system, which give additional details of the state machine, and complement Figure 11. Note that the SPI control is only possible in the Watchdog, On, and User Off Wait states, and that the interrupt line INT is kept low in all states except for Watchdog and On.
FUNCTIONAL DEVICE OPERATION OPERATING MODES Any peripheral loading on SW4 should be isolated from the SW4 output node by the PWGT2 switch, which opens in both Lowpower off modes due to the RESETB transition. In this way, leakage is minimized from the power domain maintaining the memory subsystem. Upon a Turn On event, the Cold Start state is entered, the default power up values are loaded, and an the MEMHLDI interrupt bit is set.
FUNCTIONAL DEVICE OPERATION OPERATING MODES In order to distinguish a non-PCUT initiated Cold Start from a Cold Start after a PCUT, the PCI interrupt should be checked by software. The PCI interrupt is cleared by software or when cycling through the Off state. Because the PCUT system quickly disables all of the power tree, the battery voltage may recover to a level with the appearance of a valid supply once the battery is unloaded.
FUNCTIONAL DEVICE OPERATION OPERATING MODES GLOBAL SYSTEM RESTART A global system reset can be enabled through the GLBRSTENB SPI bit. The global reset on the MC13892A/C versions is active low so it is enabled when the GLBRSTENB = 0. In the MC13892B/D versions global reset is active high and it is enabled when the GLBRSTENB = 1.
FUNCTIONAL DEVICE OPERATION OPERATING MODES Charger Attach CHRGRAW is pulled high with corresponding interrupt and sense bits CHGDETI and CHGDETS. This is equivalent to plugging in a charger. BP should be above BPON. The charger turn on event is dependent on the charge mode selected. For details on the charger detection and turn on, see Battery Interface and Control. Battery Attach BP crossing the BPON threshold which corresponds to attaching a charged battery to the product.
FUNCTIONAL DEVICE OPERATION OPERATING MODES Table 25. Timer Main Characteristics Timer Duration Under-voltage Timer 4.0 ms Reset Timer 40 ms Watchdog Timer 128 ms Power Cut Timer Programmable 0 to 8 seconds in 31.25 ms steps TIMING DIAGRAMS A Turn On event timing diagram example shows in Figure 12. Figure 12. Power Up Timing Diagram POWER UP At power up, switchers and regulators are sequentially enabled in time slots of 2.0 ms steps to limit the inrush current after an initial delay of 8.
FUNCTIONAL DEVICE OPERATION OPERATING MODES Table 26. Power Up Defaults Table i.MX 37/51 37/51 37/51 37/51 35 27/31 PUMS1 GND Open VCOREDIG VCORE GND Open PUMS2 Open Open Open Open GND GND (49) 0.775 1.050 1.050 0.775 1.200 1.200 SW2 (49) 1.025 1.225 1.225 1.025 1.350 1.450 SW3 (49) 1.200 1.200 1.200 1.200 1.800 1.800 SW4 (49) 1.800 1.800 1.800 1.800 1.800 1.800 SWBST Off Off Off Off 5.000 5.000 VUSB 3.300 (50) 3.300 (50) 3.300 (50) 3.300 (50) 3.
FUNCTIONAL DEVICE OPERATION OPERATING MODES POWER MONITORING The voltage at BPSNS and BP is monitored by detectors as summarized in Table 28. Table 28. BP Detection Thresholds Threshold in V Bit setting BPSNS1 Falling Edge BPSNS0 UVDET Rising Edge LOBATL LOBATH BPON 0 0 2.55 2.8 3.0 3.2 0 1 2.55 2.9 3.1 3.2 1 0 2.55 3.0 3.3 3.2 1 1 2.55 3.1 3.4 3.2 Notes 57. Default setting for BPSNS[1:0] is 00. The above specified thresholds are ±50 mV accurate for the indicated edge.
FUNCTIONAL DEVICE OPERATION OPERATING MODES Table 30. Standby Pin and Polarity Control STANDBY (Pin) STANDBYINV (SPI bit) STANDBYSEC (Pin) STANDBY Control (58) STANDBYSECINV (SPI bit) 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 Notes 58. STANDBY = 0: System is not in Standby; STANDBY = 1: System is in Standby and Standby programmability is activated. When requesting standby, a programmable delay (STBYDLY) of 0 to 3 clock cycles of the 32 kHz clock is applied before actually going into standby (i.e.
FUNCTIONAL DEVICE OPERATION OPERATING MODES Table 33. LDO Regulator Control (Internal Pass Device LDOs) VxEN VxSTBY STANDBY Regulator Vx 0 X X Off 1 0 X On 1 1 0 On 1 1 1 Off Notes 61. This table is valid for regulators with an internal pass device 62.
FUNCTIONAL DEVICE OPERATION OPERATING MODES Table 35. Switcher Control In Memory Hold SWxMHMODE Memory Hold Operational Mode (64) 0 Off 1 PFM Notes 64. For Memory Hold mode, an activated SWx should use the Standby set point as programmed by SWxSTBY[4:0]. Table 36. Switcher Control In User Off SWxUOMODE User Off Operational Mode (65) 0 Off 1 PFM Notes 65. For User Off mode, an activated SWx should use the Standby set point as programmed by SWxSTBY[4:0].
FUNCTIONAL DEVICE OPERATION OPERATING MODES Figure 13. Power Gating Diagram MEMORY HOLD POWER GATING As with the User Off power gating strategy described previously, Memory Hold power gating is intended to allow isolation of the SW4 power domain, to selected circuitry in Low-power modes while cutting off the switcher domain from other peripheral loads.
FUNCTIONAL DEVICE OPERATION OPERATING MODES POWER GATING SPECIFICATIONS AND CONTROL Table 37. Power Gating Characteristics Parameter Condition Min Typ Max Units Output High 5.0 5.40 5.70 V Output Low – – 100 mV Turn-on Time (66), (67) Enable to VOUT = VOUTMIN -250 mV – 50 100 μs Turn Off Time Disable to VOUT < 1.0 V – – 1.0 μs Average Bias Current t > 500 μs after Enable – 1.0 5.0 μA PWGTx Input Voltage NMOS drain voltage 0.6 – 2.
FUNCTIONAL DEVICE OPERATION OPERATING MODES Table 40. GPO Control Bits SPI Bit GPO Control GPOxEN GPOx enable GPOxSTBY GPOx controlled by STANDBY x = 1, 2, 3, or 4 Table 41. GPO Control Scheme GPOxEN GPOxSTBY STANDBY Output GPOx 0 X X Low 1 0 X High 1 1 0 High 1 1 1 Low Notes 69. GPO1 is automatically made active high when a charger is detected, see Battery Interface and Control for more information. The GPO1 output is intended to be used for battery thermistor biasing.
FUNCTIONAL DEVICE OPERATION SUPPLIES SUPPLIES SUPPLY FLOW The switched mode power supplies and the linear regulators are dimensioned to support a supply flow based upon Figure 15. Charger and USB Cable Interface Accessory Battery Voltage & Current Control Protect Detect Power Audio CC Charge RTC, MEMA/B BP Coincell Peripherals SWBST 5.0V UVBUS PGATE VUSB USB PHY VUSB2 SW1 0.6 to 1.15V Coin Cell Serial Backlight Drivers Vcoredig SW2 0.6 to 1.25V SW3 1.
FUNCTIONAL DEVICE OPERATION SUPPLIES Table 43. Power Tree Summary Supply Purpose (Typical Application) Output Voltage (in V) Load Capability (in mA) Camera supply, internal PMOS 2.5/2.6/2.75/3.0 65 Camera supply, external PNP 2.5/2.6/2.75/3.0 250 VGEN1 General peripherals supply #1, external PNP 1.2/1.5/2.775/3.15 200 VGEN2 General peripherals supply #2, external PNP 1.2/1.5/1.6/1.8/2.7/2.8/3.0/3.15 350 General peripherals supply #3, internal PMOS 1.8/2.
FUNCTIONAL DEVICE OPERATION SUPPLIES The Buck regulator topology includes an integrated synchronous rectifier, meaning that the rectifying diode is implemented on the chip as a low ohmic FET. The placement of an external diode is therefore not required, but overall switcher efficiency may benefit from this. The buck regulators permit a 100% duty cycle operation. During normal operation, several power modes are possible depending on the loading.
FUNCTIONAL DEVICE OPERATION SUPPLIES Table 45. PLL Main Characteristics Condition (70) Parameter Min Typ Max Units – – 100 ppm PLLEN = 1 – 50 80 μA 1 Buck Regulator active – 100 150 μA 2 Buck Regulators active – 115 170 μA 3 Buck Regulators active – 130 190 μA 4 Buck Regulators active – 145 210 μA Cold Start – – 700 ns PFM to PWM – – 600 ns Frequency Accuracy Bias Current Start up Time Notes 70. Clock input to PLL is 32.768 kHz Table 46.
FUNCTIONAL DEVICE OPERATION SUPPLIES Table 47. Buck Regulators (SW1, 2, 3, 4) Output Voltage Programmability Set point SWx[4:0] SWx Output, SWxHI = 0 (Volts) SWx Output (71), SWxHI = 1 (Volts) 28 11100 1.300 1.800 29 11101 1.325 1.825 30 11110 1.350 1.850 31 11111 1.375 1.850 71. Output range not available for SW1. SW1 output range is 0.600-1.375, therefore SW1HI = 1 does not apply to SW1. The SW1HI bit should always be set to 0.
FUNCTIONAL DEVICE OPERATION SUPPLIES SW1 PFM mode Efficiency Vout = 0,7 25 V 100% 90% 80% E ffi ciency (%) 70% 60% Vin = 2, 800 V 50% Vin = 3, 600 V 40% Vin = 4, 650 V 30% 20% 10% 0% 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 Il oad (m A) SW2 PFM mode Efficiency Vout = 1.
FUNCTIONAL DEVICE OPERATION SUPPLIES S W1 P WM No P ulse Ski pp ing mode Efficien cy V out = 0,725 V S W4 P WM No P ul se S kipp ing mode Efficien cy V out = 1.
FUNCTIONAL DEVICE OPERATION SUPPLIES S W1 PWM P ulse Ski ppi ng mo de E ffi ciency Vo ut = 0, 725 V S W1 P WM Pu lse S kip pi ng mo de E ffi ciency Vo ut = 0, 725 V 100 % 100 % 90 % 90 % 80 % 80 % Ef fic ien cy (% ) 60 % Vin = 3 ,00 0 V 50 % Vin = 3 ,60 0 V 40 % Vin = 4 ,65 0 V Ef fic ien cy (% ) 70 % 70 % 60 % Vin = 3,0 00 V 50 % Vin = 3,6 00 V 40 % Vin = 4,6 50 V 30 % 30 % 20 % 20 % 10 % 10 % 0% 0% 0 0 10 20 30 40 50 60 70 80 90 50 1 00 150 200 25 0 300 35 0 4 00 4
FUNCTIONAL DEVICE OPERATION SUPPLIES Table 49. DVS Control Logic Table for SW1 and SW2 STANDBY (72) DVSx Pin Set Point Selected by 0 0 SWx[4:0] 0 1 SWxDVS[4:0] 1 X SWxSTBY[4:0] Notes 72. STANDBY is the logical anding of STANDBY and STANDBYSEC Table 50. DVS Speed Selection for SW1 and SW2 SWxDVSSPEED[1:0] Function 00 25 mV step each 2.0 μs 01 (default) 25 mV step each 4.0 μs 10 25 mV step each 8.
FUNCTIONAL DEVICE OPERATION SUPPLIES stepping. If a switcher runs out of programmable range (in either direction), as constrained by programmable stops, then the increment or decrement command shall be ignored. The Switcher Increment / Decrement (SID) function is enabled with SIDEN = 1. This will reassign the function of the DVS1 and DVS2 pins, from the default toggling between Normal and DVS operating modes, to a jog control mode for the switcher which DVSx is assigned.
FUNCTIONAL DEVICE OPERATION SUPPLIES SID Panic Mode Example Starting Value SW1 output DVS step all the way back to 1.250V (SW1[4:0] programmed value = 1.250V) 1.050 Up DVS1 SPICLK DVS Up 1 Panic 2 3 SPICLK shut down when not used Figure 22. SID Control Example for Panic Mode Recovery The system will not respond to a new jog command until it has completed a DVS step that may be in progress. Any missed jog requests will not be stored.
FUNCTIONAL DEVICE OPERATION SUPPLIES Figure 23. Boost Regulator Architecture Enabling of SWBST is accomplished through the SWBSTEN SPI control bit. Table 52. Switch Mode Supply SWBST Control Function Summary Parameter Value SWBSTEN Function 0 SWBST OFF 1 SWBST ON 5V Boost Effic ie ncy (Vin = 3 .6 V, Vou t = 5V) Efficiency (%) 100.00 95.00 90.00 85.00 80.00 0 1 00 2 00 300 Boost Load Current (mA) Figure 24.
FUNCTIONAL DEVICE OPERATION SUPPLIES All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at REFCORE. The bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on the performance of VCOREDIG and the bandgap. No external DC loading is allowed on VCOREDIG or REFCORE. VCOREDIG is kept powered as long as there is a valid supply and/or coin cell.
FUNCTIONAL DEVICE OPERATION SUPPLIES • Short-circuit protection (SCP) is included on certain LDOs (see the SCP section later in this chapter). Exceeding the SCP threshold will disable the regulator and generate a system interrupt. The output voltage will not sag below the specified voltage for the rated current being drawn. For the lower current LDOs without SCP, they are less accessible to the user environment and essentially self-limiting.
FUNCTIONAL DEVICE OPERATION SUPPLIES product damage. If a short-circuit condition is detected, the LDO will be disabled by resetting its VxEN bit while at the same time an interrupt SCPI will be generated to flag the fault to the system processor. The SCPI interrupt is maskable through the SCPM mask bit. The SCP feature is enabled by setting the REGSCPEN bit.
FUNCTIONAL DEVICE OPERATION SUPPLIES PERIPHERAL INTERFACING IC interfaces in the lineups generally fall in two categories: low voltage IO primarily associated with the AP IC and certain peripherals at SPIVCC level (powered from SW4), and a higher voltage interface level associated with other peripherals not compatible with the 1.8 V SPIVCC. VIOHI is provided at a fixed 2.775 V level for such interfaces, and may also be applied to other system needs within the guidelines of the regulator specifications.
FUNCTIONAL DEVICE OPERATION SUPPLIES Table 57. VSD Voltage Control Parameter Value VSD[2:0] Output Voltage ILoad max Input Supply 000 1.80 V 250 mA BP or External Switcher 001 2.00 V 250 mA BP 010 2.60 V 250 mA BP 011 2.70 V 250 mA BP 100 2.80 V 250 mA BP 101 2.90 V 250 mA BP 110 3.00 V 250 mA BP 111 3.
FUNCTIONAL DEVICE OPERATION SUPPLIES continuous dissipation at minimum footprint and 75 °C of ambient. For use cases where up to 500 mW of dissipation is required, the recommended PNP device is the ON Semiconductor NSS12100UW3TCG. For stability reasons a small minimum ESR may be required. A short circuit condition will shut down the VGEN3 regulator and generate an interrupt for SCPI. Table 60.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL BATTERY INTERFACE AND CONTROL The battery management interface is optimized for applications with a single charger connector to which a standard wall charger or a USB host can be connected. It can also support dead battery operation and unregulated chargers. CHARGE PATH CHARGER LINE UP The charge path is depicted in the following diagram. Figure 26.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL Table 61.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL BUILDING BLOCKS AND FUNCTIONS The battery management interface consists of several building blocks and functions as depicted in the block diagram shown in the previous paragraph. These building blocks and functions are described below while the charger operation is described in the next section.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL Table 64. Charge Path Regulator Characteristics Parameter Condition Typ Max BATTMIN – 5.6 V – – 0.35 % Charge current 1.0 to 100 mA -1.5 – 1.5 % Charge current > 100 mA and above -3.0 – 1.5 % ICHRG[3:0] =0 001 68 80 92 mA ICHRG[3:0] = 0100 360 400 440 mA ICHRG[3:0] = 0110 500 560 620 mA All other settings – – 15 % Unloaded – – 2.0 % CHRGRAW (78) – 2.2 – μF 10 – 4.7 μF - – 3.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL POWER DISSIPATION Since the charge path operates in a linear fashion, the dissipation can be significant and care must be taken to ensure that the external pass FETs M1 and M2 are not over dissipating when charging. By default, the charge system will protect against this by a built-in power limitation circuit.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL Table 69. Internal Trickle Charger Control BATT Trickle Charge Current (mA) 0 < BATT < BATTMIN 40 BATTMIN < BATT < BATTON 80 Table 70. Internal Trickle Charger Characteristics Parameter Condition Trickle Charge Current Accuracy Operating Voltage Extended Operating Range (80) Min Typ Max Units – – 30 % BATTISNS 0.0 – – V BP-BATTISNS 1.0 – – V BP-BATTISNS 0.3 – – V Notes 80.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL Table 72. Charger Detectors Main Characteristics (continued) Parameter Condition Debounce Period Min Typ Max Units BATTMIN, BATTON rising edge (normal – 32 – ms BATTMIN, BATTON rising edge (slow) – 1.0 – s BATTMIN falling edge (slow) – 1.0 – s BATTMIN falling edge (fast) – 1.0 – s BATTCYCL dual edge – 100 – ms CHGCURR – 1.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL CHARGER OPERATION USB CHARGING The USB VBUS line in this case, is used to provide a supply within the USB voltage limits and with at least 500 mA of current drive capability. When trickle charging from the USB cable, it is important not to exceed the 100 mA, in case of a legacy USB bus. The appropriate charge current level ICHRG[2:0] = (0001) is 80 mA typical which accounts for the additional current through the charge LED indicator.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL The precharge will timeout and stop charging, in case it did not succeed in raising the battery to a high enough level: BATTON for internal precharge, external precharge in the case of USB, and BPON for the external precharge, in case of a charger. This is a fault condition and is flagged to the processor by the CHGFAULTI interrupt, and the CHGFAULTS[1:0] bits are set to 10.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL FACTORY MODE In factory mode, power is provided to the application with no battery present. It is not a situation which should occur in the field. The factory mode is differentiated from a USB Host by, in addition to a valid VBUS, a UID being pulled high to the VBUS level during the attach, see Connectivity. In case of a serial path (M3 present), the application will be powered up with M1M2 fully on.
FUNCTIONAL DEVICE OPERATION BATTERY INTERFACE AND CONTROL f) If the enumeration is successful to get the stepped up current the processor will hold WDI high and continues with the booting procedure. • When the SPI is activated, the LPB interrupt LPBI can be cleared; other unmasked interrupts may now become active. When leaving watchdog phase for the On mode, the interrupts will work 'normally' even if LPBI is not cleared. • The SPI bit ACKLPB bit is set to enable the internal trickle charger.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM ADC SUBSYSTEM CONVERTER CORE The ADC core is a 10-bit converter. The ADC core and logic run on 2/3 of the switcher PLL generated frequency, so approximately 2.0 MHz. If an ADC conversion is requested while the PLL was not active, it will automatically be enabled by the ADC. A 32.768 kHz equivalent time base is derived from this to the ADC time events. The ADC is supplied from VCORE.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 82. ADC Input Specification Parameter Source Impedance Condition Min Typ Max Units No bypass capacitor at input – – 5.0 kOhm Bypass capacitor at input 10 nF – – 30 kOhm Input Buffer Offset BUFFEN = 1 -5.0 – 5.0 mV Input Buffer Input Range BUFFEN = 1 0.02 – 2.4 V When considerably exceeding the maximum input of the ADC at the scaled or unscaled inputs, the reading result will return a full scale.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM DEDICATED READINGS CHANNEL 0 BATTERY VOLTAGE The battery voltage is read at the BATT pin at channel 0. The battery voltage is first scaled as V(BATT)/2 in order to fit the input range of the ADC. Table 83. Battery Voltage Reading Coding Conversion Code ADDn[9:0] Voltage at input ADC in V Voltage at BATT in V 1 111 111 111 2.400 4.800 1 000 010 100 1.250 2.500 0 000 000 000 0.000 0.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM The value of the sense resistor used, determines the accuracy of the result as well as the available conversion range. Note that excessively high values can impact the operating life of the device due to extra voltage drop across the sense resistor. Table 86. Battery Current Reading Specification Parameter Condition Min Typ Max Units Amplifier Gain 19 20 21 Amplifier Offset -2.0 – 2.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM CHANNEL 5 ADIN5 AND BATTERY THERMISTOR AND BATTERY DETECT On channel 5, ADIN5 may be used as a general purpose unscaled input, but in a typical application, ADIN5 is used to read out the battery pack thermistor. The thermistor will have to be biased with an external pull-up to a voltage rail greater than the ADC input range. In order to save current when the thermistor reading is not required, it can be biased from one of the general purpose IO's such as GPO1.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Table 93. Die Temperature Voltage Reading Parameter Minimum Typical Maximum Unit Die Temperature Read Out Code at 25 °C – 680 – Decimal Temperature change per LSB – +0.4244 °C – °C/LSB Slope error – – 5.0 % Table 94.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM 8 Bit Address Header 24 B it Data Location 43 ADC Control Register 0 R/W Bi t Address Bits Nul l ADC Bi t BIS0 ADC Control Bits Location 44 ADC Control Register 1 R/W Bi t Address Bits Nul l ADC Bi t BIS1 ADC Control Bits Location 45 ADC Result Register ADC0 R/W Bi t Address Bits Nul l Bi t Location 46 ADC Control Register 2 R/W Bi t Address Bits Nul l ADC Bi t BIS2 Location 47 ADC Result Register ADC1 R/W Bi t Address Bits Nul l Bi t A
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM TOUCH SCREEN INTERFACE The touch screen interface provides all circuitry required for the readout of a 4-wire resistive touch screen. The touch screen X plate is connected to TSX1 and TSX2 while the Y plate is connected to TSY1 and TSY2. A local supply TSREF will serve as a reference. Several readout possibilities are offered. In order to use the ADC inputs and properly convert and readout the values, the bit ADSEL should be set to a 1.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM Figure 30 shows how the ATO and ATOX settings determine the readout sequence. The ATO should be set long enough so that the touch screen can be biased properly before conversions start.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM a first order filtering of the signal across R1. Due to the sampling of the A to D converter and the filtering applied, the longer the software waits before retrieving the information from the CC, the higher the accuracy. The capacitor will be connected between the pins CFP and CFM, see Figure 31. Figure 31. Coulomb Counter Block Diagram The CC results are available in the 2's complement CCOUT[15:0] counter. This counter is preferably reflecting 1 Coulomb per LSB.
FUNCTIONAL DEVICE OPERATION ADC SUBSYSTEM As follows from the previous description, using the CC requires a number of programming steps. A typical programming example is given below. 1. SPI Access 1: Initialize • Reg 9: Write STARTCC = 1, RSTCC = 1, CCCALA = 1, CCDITHER = 1, CCCALDB = 0 • RSTCC will be self clearing • Register 10 is NOT to be programmed since by default the ONEC[14:0] scaler is set to 1 2. Wait for analog calibration period 3.
FUNCTIONAL DEVICE OPERATION CONNECTIVITY CONNECTIVITY USB INTERFACE The MC13892 contains the regulators required to supply the PHY contained in the i.MX51, i.MX37, i.MX35, and i.MX27 processors. The regulators used to power the external PHY in the i.MX51 and i.MX37 are VUSB, VUSB2, and VUSB for the i.MX35 and i.MX27 processors. The MC13892 also provides the 5.0 V supply for USB OTG operation.
FUNCTIONAL DEVICE OPERATION CONNECTIVITY Table 99. VUSB Input Source Control Parameter VUSBIN Value Function 0 Powered by Host: UVBUS powers VUSB 1 OTG mode: SWBST internally switched to supply the VUSB regulator, and SWBST will drive VBUS from the VUSBIN pin as long as VBUSEN pin is logic high = 1 Notes 86. Note that (VUSBIN = 1 and VBUSEN = 1) only closes the switch between the VINUSB and UVBUS pins, but does not enable the SWBST boost regulator (which should be enabled with OTGSWBSTEN = 1). 87.
FUNCTIONAL DEVICE OPERATION CONNECTIVITY DETECTION COMPARATORS VBUS detection and qualification is accomplished with two comparators, detailed in Table 101. Comparator results are used to generate associated interrupts, and sense and masking bits are available through SPI (refer to SPI Bitmap). Comparator thresholds are specified for the minimum detect levels, and bits can be used in combination to qualify a VBUS window.
FUNCTIONAL DEVICE OPERATION LIGHTING SYSTEM Table 103. USB OTG Specifications Parameter Condition Min Typ Max Units VBUS Input Impedance As A_device 40 - 100 kΩ UID 220K Pull-up (89) IDPUCNTRL = 0, Resistor to VCORE 132 220 308 kΩ UID Pull-up (89) IDPUCNTRL = 1, Current source from VCORE 4.75 5.0 5.25 μA UID Parallel Pull-up (89) ID100KPU = 1, Resistor to VCORE 60 100 140 kΩ Notes 89.
FUNCTIONAL DEVICE OPERATION LIGHTING SYSTEM Table 105. Backlight Drivers Duty Cycle Programming LEDxDC[5:0](91) Duty Cycle 000000 0/32, Off 000001 1/32 … … 010000 16/32 … … 011111 31/32 100000 to 111111 32/32, Continuously On Notes 91. “x” represents MD, AD, or KP Ramp up and ramp down patterns are implemented in hardware to reduce the burden of real time software control via the SPI to orchestrate dimming and soft start lighting effects.
FUNCTIONAL DEVICE OPERATION LIGHTING SYSTEM Table 106. Serial LED Driver Characteristics Parameter(92) Condition Output Current Setting Current Programming Granularity Min Typ Max Units Low Range Mode 0.0 – 15 mA High Range Mode 0.0 – 30 Low Range Mode – 3.0 – High Range Mode – 6.0 – – 1/32 – – 256 – Hz PWM Granularity Repetition Rate Not blinking Absolute Accuracy mA – – 15 % Matching At 400 mV, 21 mA – – 3.
FUNCTIONAL DEVICE OPERATION LIGHTING SYSTEM Table 107. Signaling LED Drivers Current Programming LEDx[2:0](93) LEDx Current Level (mA) 000 0.0 001 3.0 010 6.0 011 9.0 100 12 101 15 110 18 111 21 Notes 93. “x” represents for R, G and B Table 108. Signaling LED Drivers Duty Cycle Programming LEDxDC[5:0](94) Duty Cycle 000000 0/32, Off 000001 1/32 … … 010000 16/32 … … 011111 31/32 1xxxxx 32/32, Continuously On Notes 94.
FUNCTIONAL DEVICE OPERATION LIGHTING SYSTEM Table 110. Signaling LED Driver Characteristics Parameter Condition Absolute Accuracy Min Typ Max Units – – 15 % Matching At 400 mV, 21 mA – – 10 % Leakage LEDxDC[5:0] = 000000 – – 1.0 μA Apart from using the signal LED drivers for driving LEDs they can also be used as general purpose open drain outputs for logic signaling or as generic PWM generator outputs. For the maximum voltage ratings.
Analog Integrated Circuit Device Data Freescale Semiconductor SPI BITMAP The complete SPI bitmap is given in Table 111 with one register per row for a general overview. A color coding is applied which indicates the type of reset for the bits. Table 111.
MC13892 Bitmap Color Coding: 31 30 29 28 27 26 25 24 23 22 Bits Reset by RESETB 21 20 19 18 Bits Reset by RTCPORB 17 16 15 Bits Reset by OFFB 14 13 Bits Without Reset 12 11 10 Bits Reloaded at Cold Start 9 8 7 6 5 4 Not Available Bits 3 2 Analog Integrated Circuit Device Data Freescale Semiconductor 15 Power R/W 0 Control 2 0 1 1 1 1 0 16 Unused R/W 0 1 0 0 0 0 0 17 Unused R/W 0 1 0 0 0 1 0 18 Memory A R/W 0 1 0 0 1 0 0 MEMA[23:0] 19 Memory B R/W
Analog Integrated Circuit Device Data Freescale Semiconductor Table 111.
MC13892 Bitmap Color Coding: 31 30 29 28 27 26 25 24 55 Unused R/W 1 1 0 1 1 1 0 56 Unused R/W 1 1 1 0 0 0 0 57 FSL Use R/W 1 Only 1 1 0 0 1 0 58 FSL Use R/W 1 Only 1 1 0 1 0 0 59 FSL Use R/W 1 Only 1 1 0 1 1 0 60 FSL Use R/W 1 Only 1 1 1 0 0 0 61 FSL Use R/W 1 Only 1 1 1 0 1 0 62 FSL Use R/W 1 Only 1 1 1 1 0 0 63 FSL Use R/W 1 Only 1 1 1 1 1 0 23 22 Bits Reset by RESETB 21 20 19 18 Bits Reset by RTCPORB 17 16 15 Bits Reset b
SPI BITMAP The 24 bit wide registers are numbered from 0 to 63, and are referenced throughout this document by register number, or representative name as given in the corresponding captions. The contents of all registers are given in the tables defined in this chapter; each table includes the following information: Name: Name of the bit. Spare bits are implemented in the design for future use, but are not assigned. Unused bits are not available in the design.
SPI BITMAP Table 112. Register 0, Interrupt Status 0 Name Bit # R/W Reset CHRGSE1BI 21 RW1C RESETB Default Reserved 22 Reserved 23 Description 0 Wall Charger detect R 0 For future use R 0 For future use Table 113.
SPI BITMAP Table 114. Register 2, Interrupt Sense 0 Name Bit # R/W Reset Default Description Reserved BVALIDS 15 16 R R NONE 0 S For future use USB B-session valid sense Reserved 17 R 0 For future use Reserved 18 R 0 For future use IDFLOATS 19 R NONE S ID float sense bit IDGNDS 20 R NONE S ID ground sense bit Reserved 21 R 0 For future use Reserved 22 R 0 For future use Reserved 23 R 0 For future use Table 115.
SPI BITMAP Table 116.
SPI BITMAP Table 118.
SPI BITMAP Table 119. Register 7, Identification Bit # R/W Unused Name 22 R Reset Default 0 Not available Description Unused 23 R 0 Not available Table 120. Register 8, Unused Name Bit # Unused 23-0 R/W Reset R Default 0 Description Not available Table 121.
SPI BITMAP Table 122.
SPI BITMAP Table 125.
SPI BITMAP Table 127.
SPI BITMAP Table 130.
SPI BITMAP Table 131.
SPI BITMAP Table 132. Register 20, RTC Time Name Bit # R/W Reset Default RTCCALMODE0 22 R/W RTCPORB 0 RTCCALMODE1 23 R/W RTCPORB 0 Description RTC calibration mode Table 133.
SPI BITMAP Table 134. Register 22, RTC Day Bit # R/W Unused Name 15 R Reset Default 0 Unused 16 R 0 Unused 17 R 0 Unused 18 R 0 Unused 19 R 0 Unused 20 R 0 Unused 21 R 0 Unused 22 R 0 Unused 23 R 0 Description Not available Table 135.
SPI BITMAP Table 136.
SPI BITMAP Table 138.
SPI BITMAP Table 139. Register 27, Switchers 3 Bit # R/W Unused Name 15 R Reset Default 0 Unused 16 R 0 Unused 17 R 0 Unused 18 R 0 Unused 19 R 0 Unused 20 R 0 Unused 21 R 0 Unused 22 R SW4HI 23 R/W Description Not available 0 NONE * SW4 output range selection Table 140.
SPI BITMAP Table 141.
SPI BITMAP Table 143.
SPI BITMAP Table 144. Register 32, Regulator Mode 0 Bit # R/W Unused Name 21 R Reset Default 0 Unused 22 R 0 Unused 23 R 0 Description Not available Table 145.
SPI BITMAP Table 146. Register 34, Power Miscellaneous Name Bit # R/W Reset Default Description PWGT1SPIEN 15 R/W RESETB 1 Power Gate 1 enable PWGT2SPIEN 16 R/W RESETB 1 Power Gate 2 enable Spare 17 R/W RESETB 0 For future use Unused 18 R 0 Unused 19 R 0 Unused 20 R 0 GPO4ADIN 21 R/W Unused 22 R 0 Unused 23 R 0 RESETB 1 Not available GPO4 configured as ADC input (GPO drive tri-stated) Not available Table 147.
SPI BITMAP Table 155.
SPI BITMAP Table 156. Register 44, ADC 1 Name Bit # R/W Reset Default Description ADONESHOT 22 R/W RESETB 0 Single trigger event only ADCBIS1 23 W RESETB 0 Access to the ADCBIS control Table 157.
SPI BITMAP Table 158. Register 46, ADC 3 Name Bit # R/W Reset Default Unused 9 R 0 Unused 10 R 0 Unused 11 R 0 Unused 12 R 0 Unused 13 R 0 Unused 14 R 0 Unused 15 R 0 Unused 16 R 0 Unused 17 R 0 Unused 18 R 0 Unused 19 R 0 Unused 20 R 0 Unused 21 R 0 Unused 22 R 0 Reserved 23 R 0 Description Not available For future use Table 159.
SPI BITMAP Table 160.
SPI BITMAP Table 161. Register 49, USB 0 Name Bit # R/W IDPUCNTRL 22 R/W Reserved 23 R Reset Default RESETB Description 0 UID pin pull up source select 0 For future use Table 162.
SPI BITMAP Table 163. Register 51, LED Control 0 Name Bit # R/W Reset Default LEDADDC0 15 R/W RESETB 0 LEDADDC1 16 R/W RESETB 0 LEDADDC2 17 R/W RESETB 0 LEDADDC3 18 R/W RESETB 0 LEDADDC4 19 R/W RESETB 0 LEDADDC5 20 R/W RESETB 0 LEDAD0 21 R/W RESETB 0 LEDAD1 22 R/W RESETB 0 LEDAD2 23 R/W RESETB 0 Description Auxiliary display driver duty cycle Auxiliary display driver current setting Table 164.
SPI BITMAP Table 165.
SPI BITMAP Table 168. Register 56, Not Used Name Unused Bit # 23-0 R/W Reset R Default 0 Description Not available Table 169. Register 57, FSL Use Only Name FSL Use Only Bit # 23-0 R/W R/W Reset RTCPORB Default Description FSL Table 170. Register 58, FSL Use Only Name FSL Use Only Bit # 23-0 R/W Reset R/W RTCPORB Default Description FSL Table 171. Register 59, FSL Use Only Name FSL Use Only Bit # 23-0 R/W Reset R/W RTCPORB Default Description FSL Table 172.
TYPICAL APPLICATIONS TYPICAL APPLICATIONS Figure 35 contains a typical application of the MC13892. For convenience, components for use with the MC13892 are cited within this document. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
PACKAGING PACKAGE DIMENSIONS PACKAGING PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.
PACKAGING PACKAGE DIMENSIONS VK SUFFIX 139-PIN 98ASA10820D REVISION 0 MC13892 Analog Integrated Circuit Device Data Freescale Semiconductor 153
PACKAGING PACKAGE DIMENSIONS VL SUFFIX 186-PIN 98ASA10849D REVISION 0 MC13892 154 Analog Integrated Circuit Device Data Freescale Semiconductor
PACKAGING PACKAGE DIMENSIONS VL SUFFIX 186-PIN 98ASA10849D REVISION 0 MC13892 Analog Integrated Circuit Device Data Freescale Semiconductor 155
ADDITIONAL DOCUMENTATION ADDITIONAL DOCUMENTATION Table 176.
REVISION HISTORY REVISION HISTORY REVISION DATE 14.0 11/2011 DESCRIPTION • • • • Added MC13892CJVK and MC13892CJVL to the ordering information Changed RT from 45 k to 4.5 k in Table 73 for THIGH In the Static Electrical Characteristics table, changed Input Operating Voltage - CHRGRAW from 17 V to 5.6 V on page 24. Changed Input Operating Voltage - CHRGRAW from 17 V to 5.6 V in Table 64. 15.0 4/2012 • Added MC13892DJVK and MC13892DJVL to Table 1, MC13892 Device Variations. 16.
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