Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 69 of 547
6.1 How to read this chapter
The C_CAN controller interrupt is available on parts LPC11Cxx only.
6.2 Introduction
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
6.3 Features
• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0
• Tightly coupled interrupt controller provides low interrupt latency
• Controls system exceptions and peripheral interrupts
• The NVIC supports 32 vectored interrupts
• 4 programmable interrupt priority levels with hardware priority level masking
• Software interrupt generation
6.4 Interrupt sources
Table 55 lists the interrupt sources for each peripheral function. Each peripheral device
may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may
represent more than one interrupt source. There is no significance or priority about what
line is connected where, except for certain standards from ARM.
See Section 28.6.2
for the NVIC register bit descriptions.
UM10398
Chapter 6: LPC111x/LPC11Cxx Nested Vectored Interrupt
Controller (NVIC)
Rev. 12.3 — 10 June 2014 User manual
Table 55. Connection of interrupt sources to the Vectored Interrupt Controller
Exception
Number
Vector
Offset
Function Flag(s)
12 to 0 start logic wake-up
interrupts
Each interrupt is connected to a PIO input pin serving
as wake-up pin from Deep-sleep mode; Interrupt 0 to
11 correspond to PIO0_0 to PIO0_11 and interrupt
12 corresponds to PIO1_0; see Section 3.5.30.
13 C_CAN C_CAN interrupt
14 SPI/SSP1 Tx FIFO half empty
Rx FIFO half full
Rx Timeout
Rx Overrun
15 I
2
C SI (state change)