Datasheet
UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 391 of 547
22.1 How to read this chapter
This chapter describes the Windowed WDT available on all parts of the LPC1100L and
LPC1100XL series.
22.2 Basic configuration
The WDT is configured using the following registers:
1. Pins: The WDT uses no external pins.
2. Power: In the SYSAHBCLKCTRL register, set bit 15 (Table 21
).
3. Peripheral clock: Select the WDT clock source (Table 25
) and enable the WDT
peripheral clock by writing to the WDTCLKDIV register (Table 27
).
Remark: The frequency of the watchdog oscillator is undefined after reset. The
watchdog oscillator frequency must be programmed by writing to the WDTOSCCTRL
register (see Table 13
) before using the watchdog oscillator for the WDT.
4. Lock features: Once the watchdog timer is enabled by setting the WDEN bit in the
WDMOD register, the following lock features are in effect:
a. The WDEN bit cannot be changed to 0, that is the WDT cannot be disabled.
b. The watch dog clock source cannot be changed. If the WDT is needed in
Deep-sleep mode, select the watch dog oscillator as the clock source before
setting the WDEN bit.
22.3 Features
• Internally resets chip if not reloaded during the programmable time-out period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time-out period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Programmable 24-bit timer with internal fixed pre-scaler.
• Selectable time period from 1,024 watchdog clocks (T
WDCLK
256 4) to over 67
million watchdog clocks (T
WDCLK
2
24
4) in increments of 4 watchdog clocks.
• “Safe” watchdog operation. Once enabled, requires a hardware reset or a Watchdog
reset to be disabled.
• A dedicated on-chip watchdog oscillator provides a reliable clock source that cannot
be turned off when the Watchdog Timer is running.
• Incorrect feed sequence causes immediate watchdog reset if the watchdog is
enabled.
• The watchdog reload value can optionally be protected such that it can only be
changed after the “warning interrupt” time is reached.
UM10398
Chapter 22: LPC111x/LPC11Cxx Windowed WatchDog Timer
(WDT)
Rev. 12.3 — 10 June 2014 User manual