Datasheet

UM10398 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
User manual Rev. 12.3 — 10 June 2014 255 of 547
NXP Semiconductors
UM10398
Chapter 15: LPC111x/LPC11Cxx I2C-bus controller
The synchronization logic will synchronize the serial clock generator with the clock pulses
on the SCL line from another device. If two or more master devices generate clock pulses,
the “mark” duration is determined by the device that generates the shortest “marks,” and
the “space” duration is determined by the device that generates the longest “spaces”.
Figure 53
shows the synchronization procedure.
A slave may stretch the space duration to slow down the bus master. The space duration
may also be stretched for handshaking purposes. This can be done after each bit or after
a complete byte transfer. the I
2
C block will stretch the SCL space duration after a byte has
been transmitted or received and the acknowledge bit has been transferred. The serial
interrupt flag (SI) is set, and the stretching continues until the serial interrupt flag is
cleared.
15.9.7 Serial clock generator
This programmable clock pulse generator provides the SCL clock pulses when the I
2
C
block is in the master transmitter or master receiver mode. It is switched off when the I
2
C
block is in slave mode. The I
2
C output clock frequency and duty cycle is programmable
(1) Another device transmits serial data.
(2) Another device overrules a logic (dotted line) transmitted this I
2
C master by pulling the SDA line
low. Arbitration is lost, and this I
2
C enters Slave Receiver mode.
(3) This I
2
C is in Slave Receiver mode but still generates clock pulses until the current byte has been
transmitted. This I
2
C will not generate clock pulses for the next byte. Data on SDA originates from
the new master once it has won arbitration.
Fig 52. Arbitration procedure
(1) Another device pulls the SCL line low before this I
2
C has timed a complete high time. The other
device effectively determines the (shorter) HIGH period.
(2) Another device continues to pull the SCL line low after this I
2
C has timed a complete low time and
released SCL. The I
2
C clock generator is forced to wait until SCL goes HIGH. The other device
effectively determines the (longer) LOW period.
(3) The SCL line is released , and the clock generator begins timing the HIGH time.
Fig 53. Serial clock synchronization
SDA line
SCL line
1234 89
ACK
(1) (2)(1)
(3)
SDA line
SCL line
(2)
(1)(3)
high
period
low
period
(1)