Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller WLCSP 16 32-Bit 50 MHz I/O number 11

1. General description

The LPC1102/1104 are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for

8/16-bit microcontroller applications, offering performance, low power, simple instruction

set and memory addressing together with reduced code size compared to existing 8/16-bit

architectures.

The LPC1102/1104 operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC1102/1104 includes 32 kB of flash memory, 8 kB of

data memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four

general purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.

Remark: The LPC1104 has a revised pinout and contains several features not found in

the LPC1102:

• Two extra GPIO pins (PIO0_1 and PIO0_6).

• Extra match output (CT32B0_MAT2).

• CLKOUT feature.

• Easier re-entry to ISP via PIO0_1.

• SSP0_CLK available on two pins (A1 and A2) to support debugging of SSP

communication.

• Better positioning of the XTALIN pin for easier PCB layout.

2. Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Serial Wire Debug.

 System tick timer.

 Memory:

 32 kB on-chip flash programming memory.

 8 kB SRAM.

 In-Application Programming (IAP) and In-System Programming (ISP) support via

on-chip bootloader software.

 Digital peripherals:

 11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors

and programmable open-drain mode.

LPC1102/1104

32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB

SRAM

Rev. 7 — 26 September 2013 Product data sheet

Summary of content (43 pages)

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LPC1102/1104 32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM Rev. 7 — 26 September 2013 Product data sheet 1. General description The LPC1102/1104 are an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC1102/1104 operate at CPU frequencies of up to 50 MHz.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller         GPIO pins can be used as edge and level sensitive interrupt sources.  Four general purpose counter/timers with a total of one capture input and 10 match outputs.  Programmable windowed WatchDog Timer (WDT). Analog peripherals:  10-bit ADC with input multiplexing among five pins. Serial interfaces:  UART with fractional baud rate generation, internal FIFO, and RS-485 support.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC1102UK WLCSP16 wafer level chip-size package; 16 bumps; 2.17  2.32  0.6 mm - LPC1104UK WLCSP16 wafer level chip-size package; 16 bumps; 2.17  2.32  0.6 mm - 4.1 Ordering options Table 2.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 6.1 Pinning LPC1102/1104UK D C B A ball A1 index area 1 2 3 4 002aaf525 Fig 2. LPC1102_1104 Product data sheet Pin configuration WLCSP16 package All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 September 2013 © NXP B.V. 2013. All rights reserved.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3. LPC1102/1104 pin description table Symbol LPC1102 LPC1104 Start logic input Type Reset Description state[1] RESET/PIO0_0 C1[2] B2[2] I I; PU RESET — External reset input with 20 ns glitch filter. A LOW -going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC1102/1104 pin description table …continued Symbol LPC1102 LPC1104 Start logic input Type Reset Description state[1] R/PIO1_2/ AD3/CT32B1_MAT1 C3[4] - I; PU R — Reserved. I/O - PIO1_2 — General purpose digital input/output pin. I - AD3 — A/D converter, input 3. O - CT32B1_MAT1 — Match output 1 for 32-bit timer 1. I/O I; PU SWDIO — Serial wire debug input/output.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC1102/1104 contain 32 kB of on-chip flash memory. Remark: The LPC1102 supports In-Application Programming (IAP) and In-System Programming (ISP).
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller AHB peripherals LPC1102/1104 4 GB 0x5020 0000 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 127 - 16 reserved 0xE000 0000 0x5004 0000 reserved 0x5020 0000 AHB peripherals 0x5000 0000 15-12 reserved 11-8 reserved 7-4 GPIO PIO1 3-0 GPIO PIO0 reserved APB peripherals 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 31 - 23 reserved 0x4005 C000 0x4008 0000 APB peripherals 1 GB reserved 22 0x400
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.8.1 Features • • • • • Maximum UART data bit rate of 3.125 Mbit/s. 16 Byte Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • • • • • • • Input multiplexing among 5 pins. Power-down mode. Measurement range 0 V to VDD. 10-bit conversion time  2.44 s (up to 400 kSamples/s). Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or timer match signal. Individual result registers for each ADC channel to reduce interrupt overhead. 7.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller SYSTEM CLOCK DIVIDER AHB clock 0 (system) system clock 18 AHB clocks 1 to 18 (memories and peripherals) AHBCLKCTRL[1:18] (AHB clock enable) IRC oscillator SPI0 PERIPHERAL CLOCK DIVIDER SPI0 UART PERIPHERAL CLOCK DIVIDER UART WDT CLOCK DIVIDER WDT main clock watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator IRC oscillator watchdog oscillator SYSTEM PLL external clock WDTUEN (WDT clock update enable) SYS
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller its frequency range while the PLL is providing the desired output frequency. The PLL output frequency must be lower than 100 MHz. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.14.5.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.15.4 Code security (Code Read Protection - CRP) This feature of the LPC1102/1104 allow user to enable different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of Code Read Protection: 1.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit [2] 0.5 +4.6 V [2][3] 0.5 +5.5 V 0.5 +3.6 V 0.5 +4.6 V 100 mA supply voltage (core and external rail) VDD input voltage VI 5 V tolerant I/O pins; VDD  1.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 5. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) IDD supply current Conditions Min Typ[1] Max Unit 1.8 3.3 3.6 V - 2 - mA - 7 - mA - 1 - mA - 2 - A Active mode; code while(1){} executed from flash system clock = 12 MHz VDD = 3.3 V system clock = 50 MHz VDD = 3.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 5. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOH HIGH-level output current VOH = VDD  0.4 V; 4 - - mA 3 - - mA 4 - - mA 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.5 V LOW-level output current IOL VOL = 0.4 V 2.5 V  VDD  3.6 V 1.8 V  VDD < 2.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V. Symbol Parameter VIA analog input voltage 0 - VDD V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2] - - 1 LSB integral non-linearity [3] - - 1.5 LSB EO offset error [4] - - 3.5 LSB EG gain error [5] - - 0.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.1 BOD static characteristics Table 7. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 1 Min Typ Max Unit assertion - 2.22 - V de-assertion - 2.35 - V assertion - 2.52 - V de-assertion - 2.66 - V assertion - 2.80 - V de-assertion - 2.90 - V assertion - 1.46 - V de-assertion - 1.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf980 10 IDD (mA) 8 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System PLL disabled; IRC enabled.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf982 6 IDD (mA) 48 MHz(2) 4 36 MHz(2) 24 MHz(2) 2 12 MHz(1) 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. (1) System PLL disabled; IRC enabled. (2) System PLL enabled; IRC disabled. Fig 8.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.3 CoreMark data 002aah163 14 IDD (mA) 11.2 mode 0 mode 1 mode 2 mode 3 8.4 5.6 2.8 0 0 10 20 30 40 50 frequency (MHz) External signal generator providing 1 MHz to 20 MHz signal drives the XTALIN input; when testing 1 MHz to 19 MHz the system PLL is OFF, SYSAHBCLKDIV = 1; when testing 20 MHz to 50 MHz the system PLL is configured so that SYSAHBCLKDIV = 1. Fig 10.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae992 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 12. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH 002aae988 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 13.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae989 80 T = 85 °C 25 °C −40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 14. Typical pull-down current Ipd versus input voltage VI LPC1102_1104 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 September 2013 © NXP B.V. 2013. All rights reserved.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Power-up ramp conditions Table 8. Power-up characteristics Tamb = 40 C to +85 C. Symbol Parameter Conditions Min at t = t1: 0 < VI 400 mV tr rise time twait wait time VI input voltage [1] [1][2] at t = t1 on pin VDD Typ Max Unit 0 - 500 ms 12 - - s 0 - 400 mV [1] See Figure 15.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.3 External clock Table 10. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD over specified ranges.[1] Min Typ[2] Max Unit oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.4 Internal oscillators Table 11. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V.[1] Symbol Parameter Conditions fosc(RC) internal RC oscillator frequency - Min Typ[2] Max Unit 11.88 12 12.12 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.5 I/O pins Table 13. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 10.6 SPI interfaces Table 14.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tv(Q) th(Q) DATA VALID MOSI DATA VALID tDS DATA VALID MISO tDH DATA VALID tv(Q) MOSI DATA VALID th(Q) DATA VALID tDH tDS MISO DATA VALID CPHA = 1 CPHA = 0 DATA VALID 002aae829 Fig 18. SPI master timing in SPI mode LPC1102_1104 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 September 2013 © NXP B.V. 2013.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 19. SPI slave timing in SPI mode LPC1102_1104 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 September 2013 © NXP B.V. 2013.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 6: • The ADC input trace must be short and as close as possible to the LPC1102/1104 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller VDD VDD open-drain enable pin configured as digital output driver strong pull-up output enable ESD data output PIN strong pull-down ESD VSS VDD weak pull-up pull-up enable weak pull-down repeater mode enable pin configured as digital input pull-down enable data input select analog input pin configured as analog input analog input 002aah159 Fig 21. Standard I/O pad configuration 11.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.5 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source. See Figure 23. ADC Block Source ADC COMPARATOR Rmux Rsw <2 kΩ <1.3 kΩ Cia Rs Rin Cio VEXT VSS 002aah615 Fig 23.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Package outline WLCSP16: wafer level chip-size package; 16 bumps; body 2.17 x 2.32 x 0.6 mm A B D LPC1102UK ball A1 index area A2 E A A1 detail X e1 1/2 e e ∅v ∅w b C C A B C y D e C 1/2 e e2 B A ball A1 index area 1 2 3 4 X 0 1 Dimensions Unit mm 2 mm scale A A1 A2 b D E max 0.65 0.27 0.38 0.35 2.21 2.36 nom 0.60 0.24 0.36 0.32 2.17 2.32 min 0.55 0.21 0.34 0.29 2.13 2.28 e e1 e2 0.5 1.5 1.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Abbreviations Table 15.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Revision history Table 16. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC1102_1104 v.7 20130926 Product data sheet - LPC1102_1104 v.6 Modifications: LPC1102_1104 v.6 Modifications: LPC1102_1104 v.5 Modifications: LPC1102 v.4 Modifications: LPC1102 v.3 Modifications: LPC1102 v.2 Modifications: LPC1102 v.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC1102/1104 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 17. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.7.1 7.8 7.8.1 7.9 7.9.1 7.10 7.10.1 7.11 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . .