DISCRETE SEMICONDUCTORS DATA SHEET BUJ105A Silicon Diffused Power Transistor Product specification February 1999
NXP Semiconductors Product specification Silicon Diffused Power Transistor BUJ105A GENERAL DESCRIPTION High-voltage, high-speed planar-passivated npn power switching transistor in TO220AB envelope intended for use in high frequency electronic lighting ballast applications, converters, inverters, switching regulators, motor control systems, etc.
NXP Semiconductors Product specification Silicon Diffused Power Transistor BUJ105A STATIC CHARACTERISTICS Tmb = 25 ˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS ICES,ICBO ICES Collector cut-off current 1 VBE = 0 V; VCE = VCESMmax VBE = 0 V; VCE = VCESMmax; Tj = 125 ˚C ICEO IEBO VCEOsust Collector cut-off current Emitter cut-off current Collector-emitter sustaining voltage VCEsat VBEsat hFE hFE hFEsat Collector-emitter saturation voltage Base-emitter saturation voltage DC current gai
NXP Semiconductors Product specification Silicon Diffused Power Transistor BUJ105A ICon 90 % + 50v 100-200R 90 % IC 10 % ts Horizontal ton tf toff Oscilloscope IBon IB Vertical 10 % 300R 1R tr 30ns 6V 30-60 Hz -IBoff Fig.1. Test circuit for VCEOsust. Fig.4. Switching times waveforms with resistive load. VCC IC / mA LC 250 IBon 100 LB T.U.T. 10 0 -VBB min VCE / V VCEOsust Fig.2. Oscilloscope display for VCEOsust. VCC Fig.5. Test circuit inductive load.
NXP Semiconductors Product specification Silicon Diffused Power Transistor 120 BUJ105A Normalised Power Derating PD% VCEsat/V 110 2.0 100 90 1.6 80 IC=1A 70 2A 3A 4A 1.2 60 50 0.8 40 30 0.4 20 10 0 0 20 40 60 80 Tmb / C 100 120 0.0 0.01 140 0.10 1.00 10.00 IB/A Fig.7. Normalised power dissipation. PD% = 100⋅PD/PD 25˚C = f (Tmb) Fig.10. Collector-Emitter saturation voltage. Solid lines = typ values, VCEsat = f(IB); Tj=25˚C. VBESAT/V 1.4 HFE 50 1.3 30 Tj=100C 1.
NXP Semiconductors Product specification Silicon Diffused Power Transistor 10 BUJ105A IC/A 11 Zth / (K/W) 10 9 8 1 7 D= 0.5 6 0.1 0.2 0.1 0.05 0.02 0 5 tp PD D= 4 T -3V 3 t T 0.01 1E-06 -5V tp 2 -1V 1 1E-04 1E-02 t/s 1E+00 0 0 Fig.13. Transient thermal impedance. Zth j-mb = f(t); parameter D = tp/T 100 200 300 400 500 VCEclamp/V 600 700 800 Fig.15. Reverse bias safe operating area (Tj < Tjmax) for -VBE = 5V,3V & 1V. VCC LC IBon -VBB VCL LB T.U.T. Fig.14.
NXP Semiconductors Product specification Silicon Diffused Power Transistor BUJ105A MECHANICAL DATA Dimensions in mm 4,5 max Net Mass: 2 g 10,3 max 1,3 3,7 2,8 5,9 min 15,8 max 3,0 max not tinned 3,0 13,5 min 1,3 max 1 2 3 (2x) 0,9 max (3x) 2,54 2,54 0,6 2,4 Fig.16. TO220AB; pin 2 connected to mounting base. Notes 1. Refer to mounting instructions for TO220 envelopes. 2. Epoxy meets UL94 V0 at 1/8". February 1999 6 Rev 1.
NXP Semiconductors Legal information DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1.
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