Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal HVQFN 40

1. General description

The ADC1010S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performance and low power consumption at sample rates up to 125 Msps.

Pipelined architecture and output error correction ensure the ADC1010S is accurate

enough to guarantee zero missing codes over the entire operating range. Supplied from a

single 3 V source, it can handle output logic levels from 1.8 V to 3.3 V in CMOS mode,

because of a separate digital output supply. It supports the Low Voltage Differential

Signaling (LVDS) Double Data Rate (DDR) output standard. An integrated Serial

Peripheral Interface (SPI) allows the user to easily configure the ADC. The device also

includes a programmable full-scale SPI to allow a flexible input voltage range from

1 V to 2 V (peak-to-peak). With excellent dynamic performance from the baseband to

input frequencies of 170 MHz or more, the ADC1010S is ideal for use in communications,

imaging and medical applications.

2. Features and benefits

3. Applications

ADC1010S series

Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;

CMOS or LVDS DDR digital outputs

Rev. 2 — 28 December 2010 Product data sheet

 SNR, 62 dBFS; SFDR, 86 dBc  Input bandwidth, 600 MHz

 Sample rate up to 125 Msps  Power dissipation, 430 mW at 80 Msps

 10-bit pipelined ADC core  Serial Peripheral Interface (SPI)

 Clock input divided by 2 for less jitter  Duty cycle stabilizer

 Single 3 V supply  Fast OuT-of-Range (OTR) detection

 Flexible input voltage range: 1 V (p-p) to

2V (p-p)

 Offset binary, two’s complement, gray

code

 CMOS or LVDS DDR digital outputs  Power-down and Sleep modes

 Pin compatible with the ADC1410S

series and the ADC1210S series

 HVQFN40 package

 Wireless and wired broadband

communications

 Portable instrumentation

 Spectral analysis  Imaging systems

 Ultrasound equipment  Software defined radio

Summary of content (39 pages)

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ADC1010S series Single 10-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; CMOS or LVDS DDR digital outputs Rev. 2 — 28 December 2010 Product data sheet 1. General description The ADC1010S is a single-channel 10-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performance and low power consumption at sample rates up to 125 Msps. Pipelined architecture and output error correction ensure the ADC1010S is accurate enough to guarantee zero missing codes over the entire operating range.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 4. Ordering information Table 1. Ordering information Type number fs (Msps) Package Name Description Version ADC1010S125HN/C1 125 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.85 mm SOT618-1 ADC1010S105HN/C1 105 HVQFN40 plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 × 6 × 0.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 6. Pinning information 5 AGND 6 INM 7 INP 8 23 D3 AGND 9 22 D4 VDDA 10 21 D5 26 D0 D6 20 D7 19 D8 18 D9 17 PWD 16 OE 15 DEC 14 CLKM 13 CLKP 12 VDDA 11 31 DAVM 32 DAVP 33 VDDO INM 7 24 D2_D3_P INP 8 23 D2_D3_M AGND 9 22 D4_D5_P VDDA 10 21 D4_D5_M 005aaa135 Transparent top view Fig 2. 34 OGND 6 25 D1 24 D2 35 OTR AGND 27 n.c.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 2.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 3. Pin description (LVDS DDR) digital outputs) …continued Symbol Pin [1] Type [2] Description n.c. 30 - not connected DAVM 31 O data valid output clock, complement DAVP 32 O data valid output clock, true [1] Pins 1 to 16 and pins 33 to 40 are the same for both CMOS and LVDS DDR outputs (see Table 2). [2] P: power supply; G: ground; I: input; O: output; I/O: input/output. 7.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 9. Static characteristics Table 6. Symbol Static characteristics[1] Parameter Conditions Min Typ Max Unit 2.85 3.0 3.4 V Supplies VDDA analog supply voltage VDDO output supply voltage CMOS mode 1.65 1.8 3.6 V LVDS DDR mode 2.85 3.0 3.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 6. Symbol Static characteristics[1] …continued Parameter Conditions Min Typ Max Unit OGND - 0.2VDDO V 0.8VDDO - VDDO V - 3 - pF Digital outputs, CMOS mode: pins D9 to D0, OTR, DAV Output levels, VDDO = 3 V VOL LOW-level output voltage VOH HIGH-level output voltage CO output capacitance high impedance; OE = HIGH Output levels, VDDO = 1.8 V VOL LOW-level output voltage OGND - 0.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors ADC1010S_SER Product data sheet 10. Dynamic characteristics 10.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) DATA tsu tPD th DAV tclk 005aaa060 Fig 4. CMOS mode and clock timing N+1 N td(s) N+2 tclk CLKP CLKM tPD (N − 14) (N − 13) (N − 12) (N − 11) Dx_Dx + 1_P Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx Dx + 1 Dx_Dx + 1_M tsu th tsu th tPD DAVP DAVM tclk Fig 5.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 10.3 SPI timings Table 9.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 10.4 Typical characteristics 001aam619 3.2 C (pF) 001aam614 16 R (kΩ) 3.0 12 2.8 8 2.6 4 2.4 0 50 Fig 7. 150 250 350 450 550 f (MHz) Capacitance as a function of frequency 001aam616 100 SFDR (dBc) 50 Fig 8.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 001aam617 92 SFDR (dBc) 88 001aam618 80 (1) SNR (dBFS) (2) 60 (1) (2) (3) (3) 84 40 80 20 10 30 50 70 90 δ (%) (1) Tamb = −40 °C/typical supply voltages 10 30 50 70 δ (%) (1) Tamb = −40 °C/typical supply voltages (2) Tamb = +25 °C/typical supply voltages (2) Tamb = +25 °C/typical supply voltages (3) Tamb = +90 °C/typical supply voltages (3) Tamb = +90 °C/typical supply voltages Fig 11.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 11. Application information 11.1 Device control The ADC1010S can be controlled via SPI or directly via the I/O pins (Pin control mode). 11.1.1 SPI and Pin control modes The device enters Pin control mode at power-up, and remains in this mode as long as pin CS is held HIGH. In Pin control mode, the SPI pins SDIO, CS and SCLK are used as static control pins. SPI control mode is enabled by forcing pin CS LOW.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 11.1.4 Selecting the output data format The output data format can be selected via the SPI interface (offset binary, two’s complement or gray code; see Table 23) or by using pin DFS in Pin control mode (offset binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is HIGH, two’s complement is selected. 11.2 Analog inputs 11.2.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs R INP C R INM 005aaa073 Fig 17. Anti-kickback circuit The component values are determined by the input frequency and should be selected so as not to affect the input bandwidth. Table 11. RC coupling versus input frequency - typical values Input frequency R C 3 MHz 25 Ω 12 pF 70 MHz 12 Ω 8 pF 170 MHz 12 Ω 8 pF 11.2.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs ADT1-1WT analog input 100 nF ADT1-1WT 50 Ω 12 Ω INP 50 Ω 8.2 pF 50 Ω 100 nF 50 Ω 12 Ω INM VCM 100 nF 100 nF 005aaa045 Fig 19. Dual transformer configuration suitable for a high intermediate frequency application 11.3 System reference and power management 11.3.1 Internal/external references The ADC1010S has a stable and accurate built-in internal reference voltage to adjust the ADC full-scale.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs REFT REFERENCE AMP REFB VREF EXT_ref EXT_ref BUFFER BANDGAP REFERENCE ADC CORE SENSE SELECTION LOGIC 005aaa164 Fig 20. Reference equivalent schematic If bit INTREF_EN is set to logic 0, the reference voltage is determined either internally or externally as detailed in Table 12. Table 12.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs VREF VREF 330 pF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE 005aaa117 005aaa116 Fig 21. Internal reference, 2 V (p-p) full-scale Fig 22. Internal reference, 1 V (p-p) full-scale VREF VREF V 0.1 μF 330 pF REFERENCE EQUIVALENT SCHEMATIC REFERENCE EQUIVALENT SCHEMATIC SENSE SENSE VDDA 005aaa118 005aaa119 Fig 23.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 11.3.3 Common-mode output voltage (VO(cm)) A 0.1 μF filter capacitor should be connected between pin VCM and ground to ensure a low-noise common-mode output voltage. When AC-coupled, pin VCM can then be used to set the common-mode reference for the analog inputs, for instance via a transformer middle point. package ESD parasitics COMMON-MODE REFERENCE 1.5 V VCM 0.1 μF ADC core 005aaa051 Fig 25.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Sine clock input CLKP Sine clock input CLKP CLKM CLKM 005aaa173 005aaa054 a. Sine clock input b. Sine clock input (with transformer) CLKP LVPECL clock input CLKM 005aaa172 c. LVPECL clock input Fig 27. Differential clock input 11.4.2 Equivalent input circuit The equivalent circuit of the input clock buffer is shown in Figure 28.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Single-ended or differential clock inputs can be selected via the SPI interface (see Table 21). If single-ended is enabled, the input pin (CLKM or CLKP) is selected via control bit SE_SEL. If single-ended is implemented without setting bit SE_SEL to the appropriate value, the unused pin should be connected to ground via a capacitor. 11.4.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs The output resistance is 50 Ω and is the combination of an internal resistor and the equivalent output resistance of the buffer. There is no need for an external damping resistor. The drive strength of both data and DAV buffers can be programmed via the SPI in order to adjust the rise and fall times of the output digital signals (see Table 30): 11.5.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 14. LVDS DDR output register 2 LVDS_INT_TER[2:0] Resistor value (Ω) 000 no internal termination 001 300 010 180 011 110 100 150 101 100 110 81 111 60 11.5.3 DAta Valid (DAV) output clock A data valid output clock signal (DAV) can be used to capture the data delivered by the ADC1010S. Detailed timing diagrams for CMOS and LVDS DDR modes are shown in Figure 4 and Figure 5 respectively. 11.5.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 11.5.7 Output codes versus input voltage Table 16. Output codes VINP − VINM Offset binary Two’s complement OTR pin < −1 00 0000 0000 10 0000 0000 1 −1.0000000 00 0000 0000 10 0000 0000 0 −0.9980469 00 0000 0001 10 0000 0001 0 −0.9960938 00 0000 0010 10 0000 0010 0 −0.9941406 00 0000 0011 10 0000 0011 0 −0.9921875 00 0000 0100 10 0000 0100 0 .... .... .... 0 −0.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 18. Number of data bytes to be transferred after the instruction bytes W1 W0 Number of bytes transmitted 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes or more Bits A12 to A0 indicate the address of the register being accessed. In the case of a multiple byte transfer, this address is the first register to be accessed. An address counter is increased to access subsequent addresses.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs CS SCLK (Data format) SDIO (CMOS LVDS DDR) Offset binary, LVDS DDR default mode at start-up 005aaa063 Fig 33. Default mode at start-up: SCLK LOW = offset binary; SDIO HIGH = LVDS DDR CS SCLK (Data format) SDIO (CMOS LVDS DDR) two's complement, CMOS default mode at start-up 005aaa064 Fig 34.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 19. NXP Semiconductors ADC1010S_SER Product data sheet 11.6.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 20. Reset and operating mode control register (address 0005h) bit description Default values are highlighted.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 22. Internal reference control register (address 0008h) bit description Default values are highlighted. Bit Symbol 7 to 4 - 3 INTREF_EN 2 to 0 INTREF[2:0] Access Value Description 0000 not used R/W programmable internal reference enable 0 disable 1 active R/W programmable internal reference 000 FS = 2 V 001 FS = 1.78 V 010 FS = 1.59 V 011 FS = 1.42 V 100 FS = 1.26 V 101 FS = 1.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 24. Output clock register (address 0012h) bit description Default values are highlighted.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 27. Test pattern register 2 (address 0015h) bit description Default values are highlighted. Bit Symbol Access Value Description 7 to 0 TESTPAT_USER[9:2] R/W 00000000 custom digital test pattern (bits 9 to 2) Table 28. Test pattern register 3 (address 0016h) bit description Default values are highlighted.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Table 31. LVDS DDR output register 1 (address 0021h) bit description Default values are highlighted. Bit Symbol 7 to 6 - 5 DAVI_x2_EN 4 to 3 DAVI[1:0] Access Value 00 Description not used R/W double LVDS current for DAV LVDS buffer 0 disabled 1 enabled R/W LVDS current for DAV LVDS buffer 00 3.5 mA 01 4.5 mA 10 1.25 mA 11 2 1 to 0 DATAI_x2_EN DATAI[1:0] 2.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 12. Package outline HVQFN40: plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6 x 6 x 0.85 mm A B D SOT618-1 terminal 1 index area A E A1 c detail X C e1 e 1/2 e 20 y y1 C v M C A B w M C b 11 L 21 10 e e2 Eh 1/2 1 e 30 terminal 1 index area 40 31 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 13. Revision history Table 33. Revision history Document ID Release date Data sheet status Change notice Supersedes ADC1010S_SER v.2 20101228 Product data sheet - ADC1010S_SER_1 Modifications: ADC1010S_SER_1 ADC1010S_SER Product data sheet • • • Data sheet status changed from Preliminary to Product. • Section 10.4 “Typical characteristics” added to the data sheet.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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ADC1010S series NXP Semiconductors Single 10-bit ADC; CMOS or LVDS DDR digital outputs 16. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.1.1 11.1.2 11.1.3 11.1.4 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.5 11.5.1 11.5.2 11.5.3 11.5.4 11.5.5 11.5.6 11.5.7 11.6 11.6.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . .