Datasheet

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Revision history

Rev Date Description

0.1 20081006 Initial version.

Quick Start

Demonstration Board for ADC0808S

Rev. 0.1 — 06 October 2008

Quick Start

Document information

Info Content

Keywords PCB2050-1, Demonstration board, ADC, Converter, ADC0808S

Abstract This document describes how to use the demonstration board for the

analog-to-digital converter ADC0808S.

Overview

Summary of content (7 pages)

PAGE 1
Quick Start Demonstration Board for ADC0808S Rev. 0.1 — 06 October 2008 Quick Start Document information Info Content Keywords PCB2050-1, Demonstration board, ADC, Converter, ADC0808S Abstract This document describes how to use the demonstration board for the analog-to-digital converter ADC0808S. Overview Revision history Rev Date Description 0.1 20081006 Initial version.
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1. Quick start 1.1 Setup overview Figure Fig 1 presents the connections to measure ADC0808S. POWER SUPPLY . GND . I = 80 mA . 3.3V OPTIONAL, DO NOT CONNECT . 1.8V Regulator on PCB SYNTHESIZED SIGNAL GENERATOR INPUT SIGNAL . 2Vpp sine wave . AC FILTER . High-order . Band pass PULSE GENERATOR CLOCK SIGNAL . Square wave . 1.8V CMOS Fig 1. ADC0808S setup LOGIC ANALYZER Output data . CCS for synchro . DO (LSB) to D7 (MSB) PRESENTED CONFIGURATION . 2Vpp input full scale . Square wave clock signal .
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1.2 Power supply The board is powered with a single 3.3 VDC power supply. A power supply regulator is used to supply all the circuitry on the board. Table 1. General power supply Name Function View J4 +3.3V green connector – Power supply 3.3 VDC / 100 mA. J7 Do not connect, optional. Internal 1.8V regulator. J4 J7 +1.8V green connector – Power supply 1.8 VDC / 50 mA TP1 DGND test point – Digital ground TP2 AGND test point – Analog ground TP2 TP1 1.
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Table 2. Input signals, CMOS Clock Name Function J1 IN connector – Analog input signal (50Ω matching) J2 CLKP connector – Single ended 1.8V CMOS clock input signal J3 CLKN connector – Grounded on that demo board ST7 Clock input format selection. 0: 1.8V CMOS View J1 J2 Table 3. J3 Input signals, LVDS Clock Name Function J1 IN connector – Analog input signal (50Ω matching) J2 CLKP connector – LVDS Clock input, 50 ohms must be soldered on R7 footprint.
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1.4 Output signals (D0 to D7, IR, CCS) The digital output signal is available in binary, 2’s complement. A Complete Conversion Signal output (CCS) is provided by the device for the data acquisition. Table 4.
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1.5 Configuration The ADC0808S reference, output coding, timing and frequency of complete conversion signal can be adjusted thanks to PCB jumpers. Table 5.
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Notes