Data Sheet: JN5142 IEEE802.15.4 Wireless Microcontroller Features: Transceiver Overview The JN5142 is an ultra low power, high performance wireless microcontroller suitable for Remote Control, IEEE802.15.4 and Active RFID applications. There is also a ROM variant that supports JenNet-IP Smart Devices.
Contents 1 Introduction 6 1.1 Wireless Transceiver 1.2 RISC CPU and Memory 1.3 Peripherals 1.4 Block Diagram 6 6 7 8 2 Pin Configurations 9 2.1 Pin Assignment 2.2 Pin Descriptions 2.2.1 Power Supplies 2.2.2 Reset 2.2.3 32MHz Oscillator 2.2.4 Radio 2.2.5 Analogue Peripherals 2.2.6 Digital Input/Output 10 12 12 12 12 12 13 13 3 CPU 15 4 Memory Organisation 16 4.1 ROM 4.2 RAM 4.3 OTP eFuse Memory 4.4 External Memory 4.4.1 External Memory Encryption 4.5 Peripherals 4.
8 Wireless Transceiver 27 8.1 Radio 8.1.1 Radio External Components 8.1.2 Antenna Diversity 8.2 Modem 8.3 Baseband Processor 8.3.1 Transmit 8.3.2 Reception 8.3.3 Auto Acknowledge 8.3.4 Beacon Generation 8.3.5 Security 8.4 Security Coprocessor 27 28 28 30 31 31 31 32 32 32 32 9 Digital Input/Output 33 10 Serial Peripheral Interface 35 11 Timers 38 11.1 Peripheral Timer/Counters 11.1.1 Pulse Width Modulation Mode 11.1.2 Capture Mode 11.1.3 Counter/Timer Mode 11.1.4 Delta-Sigma Mode 11.1.
18.2 Active Processing Mode 18.2.1 CPU Doze 18.3 Sleep Mode 18.3.1 Wakeup Timer Event 18.3.2 DIO Event 18.3.3 Comparator Event 18.3.4 Pulse Counter 18.4 Deep Sleep Mode 57 57 57 58 58 58 58 58 19 Electrical Characteristics 59 19.1 Maximum Ratings 19.2 DC Electrical Characteristics 19.2.1 Operating Conditions 19.2.2 DC Current Consumption 19.2.3 I/O Characteristics 19.3 AC Characteristics 19.3.1 Reset and Supply Voltage Monitor 19.3.2 SPI Master Timing 19.3.3 Two-wire Serial Interface 19.3.
Related Documents RoHS Compliance Status Information Disclaimers Version Control Contact Details © NXP Laboratories UK 2012 93 93 93 94 94 95 JN-DS-JN5142 1v0 5
1 Introduction The JN5142 is an IEEE802.15.4 wireless microcontroller that provides a fully integrated solution for applications using the IEEE802.15.4 standard in the 2.4 - 2.5GHz ISM frequency band [1], including RF4CE. A ROM variant provides support for JenNet-IP “Smart Device” applications such as lighting and building automation. Applications that transfer data wirelessly tend to be more complex than wired ones.
1.3 Peripherals The following peripherals are available on chip: Master SPI port with three select outputs UART with support for hardware or software flow control One programmable Timer/Counter which supports Pulse Width Modulation (PWM) and capture/compare, plus three PWM timers which support PWM and Timer modes only.
1.
VSS2 DIO14/SIF_CLK/TXD0*/SPISEL1 DIO13/ADE/PWM3/RTS0* DIO12/ADO/PWM2/CTS0* VB_DIG DIO11/PWM1 DIO10/TIM0OUT/32KXTALOUT DIO9/TIM0CAP/32KXTALIN/32KIN 40 39 38 37 36 35 34 33 32 DIO8/TIM0CK_GT/PC1 DIO15/SIF_D/RXD0*/SPISEL2 2 Pin Configurations DIO16/COMP1P/SIF_CLK 1 31 30 DIO17/COMP1M/SIF_D 2 29 DIO7/RXD0*/PWM3 RESETN 3 28 DIO6/TXD0*/PWM2 XTAL_OUT 4 27 DIO5/RTS0*/PWM1/PC1 XTAL_IN 5 26 DIO4/CTS0*/TIM0OUT VB_SYNTH 6 25 VB_RAM VCOTUNE 7 24 SPISELO VB_VCO 8 23 SPIMO
2.1 Pin Assignment Pin No Power supplies Signal Type Description 6, 8, 12, 14, 25, 35 VB_SYNTH, VB_VCO, VB_RF2, VB_RF1, VB_RAM, VB_DIG 1.8V Regulated supply voltage 9, 30 VDD1, VDD2 3.3V Supplies: VDD1 for analogue, VDD2 for digital 21, 39, Paddle VSS1, VSS2, VSSA 0V Grounds (see appendix A.2 for paddle details) 3 RESETN 4,5 XTAL_OUT, XTAL_IN General CMOS Reset input 1.8V System crystal oscillator Radio 7 VCOTUNE 1.8V VCO tuning RC network 10 IBIAS 1.
Digital Peripheral I/O Primary Alternate Functions 33 DIO10 TIM0OUT 34 DIO11 PWM1 36 DIO12 PWM2 CTS0 JTAG_TCK ADO 37 DIO13 PWM3 RTS0 JTAG_TMS 38 DIO14 SIF_CLK TXD0 40 DIO15 SIF_D RXD0 1 DIO16 COMP1P 2 DIO17 COMP1M 32KXTALOUT CMOS DIO10, Timer0 PWM Output or 32K External Crystal Output CMOS DIO11 or PWM1 Output CMOS DIO12, PWM2 Output, UART 0 Clear To Send Input, JTAG CLK or Antenna Diversity Odd ADE CMOS DIO13, PWM3 Output, UART 0 Request To Send Output, JTAG Mod
2.2 Pin Descriptions 2.2.1 Power Supplies The device is powered from the VDD1 and VDD2 pins, each being decoupled with a 100nF ceramic capacitor. VDD1 is the power supply to the analogue circuitry; it should be decoupled to ground. VDD2 is the power supply for the digital circuitry; and should also be decoupled to ground. In addition, a common 10µF tantalum capacitor is required for low frequencies. Decoupling pins for the internal 1.
2.2.5 Analogue Peripherals The ADC requires a reference voltage to use as part of its operation. It can use either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to analogue ground and the performance of the analogue peripherals is dependent on the quality of this reference. There are four ADC inputs and a pair of comparator inputs.
VDD2 ADC or COMP1 Input Pu IE RPU RESD RPROT I DIO[x] Pin VSS VSS O OE Figure 4: DIO Pin Equivalent Schematic In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and output level that was set as sleep commences. If the DIO pins were enabled as inputs and the interrupts were enabled then these pins may be used to wake up the JN5142 from sleep.
3 CPU The CPU of the JN5142 is a 32-bit load and store RISC processor.
4 Memory Organisation This section describes the different memories found within the JN5142. The device contains ROM, RAM, OTP eFuse memory, the wireless transceiver and peripherals all within the same linear address space. 0xFFFFFFFF 0xF0008000 RAM (32KB) 0xF0000000 Unpopulated RAM Echo 0x04000000 Peripherals 0x02000000 0x00020000 ROM (128KB) 0x00000000 Figure 5: JN5142 Memory Map 4.1 ROM The ROM is 128k bytes in size, and can be accessed by the processor in a single CPU clock cycle.
4.2 RAM The JN5142 contains 32KBytes of high speed RAM. It can be used for both code and data storage and is accessed by the CPU in a single clock cycle. At reset, a boot loader controls the loading of segments of code and data from an external memory connected to the SPI port, into RAM. Software can control the power supply to the RAM allowing the contents to be maintained during a sleep period when other parts of the device are un-powered. Typical RAM contents are shown in Figure 7.
At reset, the contents of this memory are copied into RAM by the software boot loader. The Flash and EEPROM memory devices that are supported as standard through the JN5142 bootloader are given in Table 1. NXP recommends that where possible one of these devices should be selected.
5 System Clocks Two system clocks are used to provide timing references into the on-chip subsystems of the JN5142. A 16MHz clock, generated by a crystal-controlled 32MHz oscillator, is used by the transceiver, processor, memory and digital and analogue peripherals. A 32kHz clock is used by the sleep timer and is generated by one of two on-chip oscillators or can be supplied externally. 5.1 16MHz System Clock The 16MHz system clock is used by the digital and analogue peripherals and the transceiver.
5.1.2 High-Speed RC Oscillator An on-chip High-Speed RC oscillator is provided, capable of running at either 27MHz typical or 32MHz typical once calibrated, using the software API function. No external components are required for this oscillator. The electrical specification of the oscillator can be found in Section 19.3.11. 5.2 32kHz System Clock The 32kHz system clock is used for timing the length of a sleep period (see Section 18).
5.2.3 32kHz External Clock An externally supplied 32kHz reference clock on the 32KIN input (DIO9) may be provided to the JN5142. This would allow the 32kHz system clock to be sourced from a very stable external oscillator module, allowing more accurate sleep cycle timings compared to the internal RC oscillator. (See Section 19.2.
6 Reset A system reset initialises the device to a pre-defined state and forces the CPU to start program execution from the reset vector. The reset process that the JN5142 goes through is as follows. When power is first applied or when the external reset is released, the High-Speed RC oscillator and 32MHz crystal oscillator are activated.
VDD JN5142 R1 18k RESETN C1 470nF Figure 12: External Reset Generation The external resistor and capacitor provide a simple reset operation when connected to the RESETN pin. 6.2 External Reset An external reset is generated by a low level on the RESETN pin. Reset pulses longer than the minimum pulse width will generate a reset during active or sleep modes. Shorter pulses are not guaranteed to generate a reset. The JN5142 is held in reset while the RESETN pin is low.
set by eFuse settings and the default chip configuration is for the 2.3V threshold. It is recommended that the threshold is set so that, as a minimum, the chip is held in reset until the voltage reaches the level required by the external memory device on the SPI interface. 6.5 Watchdog Timer A watchdog timer is provided to guard against software lockups. It operates by counting cycles of the high-speed RC system clock.
7 Interrupt System The interrupt system on the JN5142 is a hardware-vectored interrupt system. The JN5142 provides several interrupt sources, some associated with CPU operations (CPU exceptions) and others which are used by hardware in the device. When an interrupt occurs, the CPU stops executing the current program and loads its program counter with a fixed hardware address specific to that interrupt.
7.3 Hardware Interrupts Hardware interrupts generated from the transceiver, analogue or digital peripherals and DIO pins are individually masked using the Programmable Interrupt Controller (PIC). Management of interrupts is provided in the peripherals library [5]. For details of the interrupts generated from each peripheral see the respective section in this datasheet. Interrupts can be used to wake the JN5142 from sleep.
8 Wireless Transceiver The wireless transceiver comprises a 2.45GHz radio, modem, a baseband processor, a security coprocessor and PHY controller. These blocks, with protocol software provided as a library, implement an IEEE802.15.4 standardsbased wireless transceiver that transmits and receives data over the air in the unlicensed 2.4GHz band. 8.1 Radio Figure 14 shows the single ended radio architecture.
8.1.1 Radio External Components In order to realise the full performance of the radio it is essential that the reference PCB layout and BOM are carefully followed. See Appendix B.4. The radio is powered from a number of internal 1.8V regulators fed from the analogue supply VDD1, in order to provide good noise isolation between the digital logic of the JN5142 and the analogue blocks. These regulators are also controlled by the baseband controller and protocol software to minimise power consumption.
Antenna A Antenna B A B SEL ADO (DIO[12]) RF Switch: Single-Pole, Double-Throw (SPDT) ADE (DIO[13]) SELB COM Device RF Port Figure 16: Simple Antenna Diversity Implementation using External RF Switch ADE (DIO[13]) ADO (DIO[12]) TX Active RX Active 1st TX-RX Cycle 2nd TX-RX Cycle (1st Retry) Figure 17: Antenna Diversity ADO Signal for TX with Acknowledgement If two DIO pins cannot be spared, DIO13 can be configured to be a normal DIO pin, and the inverse of ADO generated with an inverter on
8.2 Modem The modem performs all the necessary modulation and spreading functions required for digital transmission and reception of data at 250kbps in the 2450MHz radio frequency band in compliance with the IEEE802.15.4 standard.
8.3 Baseband Processor The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware guarantees air interface timing is precise. The MAC layer hardware/software partitioning, enables software to implement the sequencing of events required by the protocol and to schedule timed events with millisecond resolution, and the hardware to implement specific events with microsecond timing resolution.
8.3.3 Auto Acknowledge Part of the protocol allows for transmitted frames to be acknowledged by the destination sending an acknowledge packet within a very short window after the transmitted frame has been received. The JN5142 baseband processor can automatically construct and send the acknowledgement packet without processor intervention and hence avoid the protocol software being involved in time-critical processing within the acknowledge sequence.
9 Digital Input/Output There are 18 Digital I/O (DIO) pins, which can be configured as either an input or an output, and each has a selectable internal pull-up resistor. Most DIO pins are multiplexed with alternate peripheral features of the device, see Section 2.1. Once a peripheral is enabled it takes precedence over the device pins. Refer to the individual module Sections for a full description of the alternate peripherals functions.
SPI Master SPICLK SPIMOSI SPIMISO SPISEL0 SPISEL1 DIO0/SPISEL1/ADC3 SPISEL2 DIO1/SPISEL2/PC0/ADC4 UART0 Timer0 PWMs 2-wire Interface TXD0 RXD0 RTS0 CTS0 DIO2/RFRX/TIM0CK_GT DIO3/RFTX/TIM0CAP TIM0CK_GT TIM0OUT TIM0CAP DIO4/CTS0/JTAG_TCK/TIM0OUT DIO5/RTS0/JTAG_TMS/PWM1/PC1 PWM1 PWM2 PWM3 DIO6/TXD0/JTAG_TDO/PWM2 DIO7/RXD0/JTAG_TDI/PWM3 SIF_D DIO8/TIM0CK_GT/PC1 SIF_CLK MUX DIO9/TIM0CAP/32KXTALIN Pulse Counters PC0 DIO10/TIM0OUT/32KXTALOUT PC1 DIO11/PWM1 JTAG Debug JTAG_TDI JTAG_TMS JTAG_TC
10 Serial Peripheral Interface The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the JN5142 and peripheral devices. The JN5142 operates as a master on the SPI bus and all other devices connected to the SPI are expected to be slave devices under the control of the JN5142 CPU.
SI SO C SPISEL2 SPISEL1 SPISEL0 SI SO JN5142 SS SO User Defined C User Defined SS Flash/ EEPROM Memory SS Slave 2 C Slave 1 SI Slave 0 SPIMOSI SPICLK SPIMISO Figure 24: Typical JN5142 SPI Peripheral Connection The data transfer rate on the SPI bus is determined by the SPICLK signal. The JN5142 supports transfers at selectable data rates from 16MHz to 125kHz selected by a clock divider. Both SPICLK clock phase and polarity are configurable.
sent from a slave, it should perform transmit using dummy data. An interrupt can be generated when the transaction has completed or alternatively the interface can be polled. If a slave device wishes to signal the JN5142 indicating that it has data to provide, it may be connected to one of the DIO pins that can be enabled as an interrupt. Figure 25 shows a complex SPI transfer, reading data from a FLASH device, that can be achieved using the SPI master interface.
11 Timers 11.1 Peripheral Timer/Counters A general-purpose timer/counter unit, Timer0, is available that can be configured to operate in one of five possible modes. This has: 5-bit prescaler, divides system clock by 2 Clocked from internal system clock (16MHz) 16-bit counter, 16-bit Rise and Fall (period) registers Timer: can generate interrupts off Rise and Fall counts. Can be gated by external signal Counter: counts number of transitions on external event signal.
The clock source for the Timer0 unit is fed from the 16MHz system clock. This clock passes to a 5-bit prescaler prescale where a value of 0 leaves the clock unmodified and other values divide it by 2 value. For example, a prescale value of 2 applied to the 16MHz system clock source results in a timer clock of 4MHz. The counter is optionally gated by a signal on the clock/gate input (TIM0CK_GT). If the gate function is selected, then the counter is frozen when the clock/gate input is high.
mode was started. Therefore, if multiple pulses are seen on TIM0CAP before the counter is stopped only the last pulse width will be stored. 9 5 3 4 CLK CAPT tRISE tRISE tFALL tFALL Capture Mode Enabled Rise x Fall 3 9 x 14 7 Figure 28: Capture Mode 11.1.3 Counter/Timer Mode The counter/timer can be used to generate interrupts, based on the timers or event counting, for software to use. As a timer the clock source is from the system clock, prescaled if required.
1 2 3 N 1 2 3 N 217 Conversion cycle 1 Conversion cycle 2 Figure 29: Return To Zero Mode in Operation 1 2 3 N Conversion cycle 1 1 216 2 3 N Conversion cycle 2 Figure 30: Non-Return to Zero Mode 11.1.5 Example Timer/Counter Application Figure 31 shows an application of the JN5142 timers to provide closed loop speed control. Timer 0 is configured in PWM mode to provide a variable mark-space ratio switching waveform to the gate of the NFET.
28-bit match value Maskable timer interrupt Single-shot, Restartable or Continuous modes of operation Match Value = Match Tick Timer Interrupt & SysClk & Counter Reset Int Enable Run Mode Control Mode Figure 32: Tick Timer The Tick Timer is clocked from a continuous 16MHz clock, which is fed to a 32-bit wide resettable up-counter, gated by a signal from the mode control block. A match register allows comparison between the counter and a programmed value.
A wakeup timer consists of a 35-bit down counter clocked from the selected 32 kHz clock. An interrupt or wakeup event can be generated when the counter reaches zero. On reaching zero the counter will continue to count down until stopped, which allows the latency in responding to the interrupt to be measured. If an interrupt or wakeup event is required, the timer interrupt should be enabled before loading the count value for the period.
12 Pulse Counters Two 16-bit counters are provided that can increment during all modes of operation (including sleep). The first, PC0, increments from pulses received on DIO1. The other pulse counter, PC1, can also be accessed on DIO5 or DIO8 depending upon the configuration. This is enabled under software control. The pulses can be de-bounced using the 32kHz clock to guard against false counting on slow or noisy edges. Increments occur from a configurable rising or falling edge on the respective DIO input.
13 Serial Communications The JN5142 has a Universal Asynchronous Receiver/Transmitter (UART) serial communication interface. It provides similar operating features to the industry standard 16550A device operating in FIFO mode. The interface performs serial-to-parallel conversion on incoming serial data and parallel-to-serial conversion on outgoing data from the CPU to external devices. In both directions, a 16-byte deep FIFO buffer allows the CPU to read and write multiple characters on each transaction.
where the hardware controls the value of the generated RTS (negated if the receive FIFO fill level is greater than a programmable threshold of 8, 11, 13 or 15 bytes), and only transmits data when the incoming CTS is asserted. Software can read characters, one byte at a time, from the Receive FIFO and can also write to the Transmit FIFO, one byte at a time. The Transmit and Receive FIFOs can be cleared and reset independently of each other.
PC COM Port 5 1 6 9 JN5142 TXD CTS UART0 RXD RS232 Level Shifter RTS Pin Signal 1 2 3 4 5 6 7 8 9 CD RD TD DTR SG DSR RTS CTS RI Figure 34: JN5142 Serial Communication Link © NXP Laboratories UK 2012 JN-DS-JN5142 1v0 47
14 JTAG Debug Interface The JN5142 includes an IEEE1149.1 compliant JTAG port for the sole purpose of software code debug with the Software Development Kit. The JTAG interface is disabled by default and is enabled under software control. Therefore, debugging is only possible if enabled by the application. Once enabled, the application executes as normal until the external debugger controller initiates debug activity.
15 Two-Wire Serial Interface (I2C) 2 The JN5142 includes industry standard I C two-wire synchronous Serial Interface operates as a Master (MSIF) or Slave (SSIF) that provides a simple and efficient method of data exchange between devices.
VDD JN5142 RP DIO14 SIF Pullup Resistors RP SIF_CLK SIF_D DIO15 D1_IN D1_OUT CLK1_IN D2_IN CLK2_IN CLK1_OUT D2_OUT CLK2_OUT DEVICE 1 DEVICE 2 Figure 35: Connection Details 15.2 Clock Stretching Slave devices can use clock stretching to slow down the transfer bit rate. After the master has driven SIF_CLK low, the slave can drive SIF_CLK low for the required period and then release it.
Start counting low period Start counting high period Wait State SIF_CLK1 Master1 SIF_CLK SIF_CLK2 Master2 SIF_CLK SIF_CLK Wired-AND SIF_CLK Figure 37: Multi-Master Clock Synchronisation After each transfer has completed, the status of the device must be checked to ensure that the data has been acknowledged correctly, and that there has been no loss of arbitration. (N.B. Loss of arbitration may occur at any point during the transfer, including data cycles).
15.4 Slave Two-wire Serial Interface When operating as a slave device, the interface does not provide a clock signal, although it may drive the clock signal low if it is required to apply clock stretching. Only transfers whose address matches the value programmed into the interface‟s address register are accepted. The interface allows both 7 and 10 bit addresses to be programmed, but only responds with an acknowledge to a single address.
16 Random Number Generator A random number generator is provided which creates a 16-bit random number each time it is invoked. Consecutive calls can be made to build up any length of random number required. Each call takes approximately 0.25msec to complete. Alternatively, continuous generation mode can be used where a new number is generated approximately every 0.25msec. In either mode of operation an interrupt can be generated to indicate when the number is available, or a status bit can be polled.
17 Analogue Peripherals The JN5142 contains a number of analogue peripherals allowing the direct connection of a wide range of external sensors and switches.
17.1.1 Operation The input range of the ADC can be set between 0V to either the reference voltage or twice the reference voltage. The reference can be either taken from the internal voltage reference or from the external voltage applied to the VREF pin. For example, an external reference of 1.2V supplied to VREF may be used to set the ADC range between 0V and 2.4V. VREF Gain Setting Maximum Input Range Supply Voltage Range (VDD) 1.2V 1.6V 1.2V 1.6V 0 0 1 1 1.2V 1.6V 2.4V 3.2V 2.2V - 3.6V 2.2V - 3.
17.1.2 Supply Monitor The internal supply monitor allows the voltage on the analogue supply pin VDD1 to be measured. This is achieved with a potential divider that reduces the voltage by a factor of 0.666, allowing it to fall inside the input range of the ADC when set with an input range twice the internal voltage reference. The resistor chain that performs the voltage reduction is disabled until the measurement is made to avoid a continuous drain on the supply. 17.1.
18 Power Management and Sleep Modes 18.1 Operating Modes Three operating modes are provided in the JN5142 that enable the system power consumption to be controlled carefully to maximise battery life. Active Processing Mode Sleep Mode Deep Sleep Mode The variation in power consumption of the three modes is a result of having a series of power domains within the chip that may be controllably powered on or off. 18.1.
When entering into sleep mode, there is an option to retain the RAM contents throughout the sleep period. If the wakeup timers are not to be used for a wakeup event and the application does not require them to run continually, then power can be saved by switching off the 32kHz oscillator if selected as the 32kHz system clock through software control. The oscillator will be restarted when a wakeup event occurs.
19 Electrical Characteristics 19.1 Maximum Ratings Exceeding these conditions may result in damage to the device. Parameter Min Max Device supply voltage VDD1, VDD2 -0.3V 3.6V Supply voltage at voltage regulator bypass pins VB_xxx -0.3V 1.98V Voltage on analogue pins XTALOUT, XTALIN, VCOTUNE, RF_IN. -0.3V VB_xxx + 0.3V Voltage on analogue pins VREF, ADC1, IBIAS -0.3V VDD1 + 0.3V Voltage on 5v tolerant digital pins SPICLK, SPIMOSI, SPIMISO, SPISEL0, DIO2-8 & DIO11-14, RESETN -0.
19.2.2 DC Current Consumption VDD = 2.0 to 3.6V, -40 to +125º C 19.2.2.1 Active Processing Mode: Min CPU processing 32,16,8,4,2 or 1MHz Typ Max Unit Notes 2100 + 220/MHz µA SPI, GPIOs enabled. When in CPU doze the current related to CPU speed is not consumed. Radio transmit 14.8 mA CPU in software doze – radio transmitting Radio receive 16.
19.2.3 I/O Characteristics VDD = 2.0 to 3.6V, -40 to +125º C, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Internal DIO pullup resistors 22 26 39 45 33 40 61 71 48, 51 59, 63 93, 97 109, 113 k VDD2 = 3.6V VDD2 = 3.0V VDD2 = 2.2V VDD2 = 2.0V Internal RESETN pullup resistor 158 189 287 338 231 287 450 531 335. 353 425, 448 680, 705 803, 825 k VDD2 = 3.6V VDD2 = 3.0V VDD2 = 2.2V VDD2 = 2.0V Digital I/O High Input (DIO0,1, 9,10, 15 - 17) (Remaining digital pins) VDD2 x 0.
tRST VRST RESETN Internal RESET tSTAB Figure 41: Externally Applied Reset VDD = 2.0 to 3.6V, -40 to +125º C Parameter External Reset pulse width to initiate reset sequence (tRST) External Reset threshold voltage (VRST) Typ Max Unit Notes 1 µs Assumes internal pullup resistor value of 100K worst case and ~5pF external capacitance VDD2 x 0.7 V Minimum voltage to avoid being reset Internal Power-on Reset threshold voltage (VPOT) Rise/fall time > 10mS 1.47 1.
DVDD VTH + VHYS VTH VPOT Internal BOReset Internal POR Figure 42: Power-on Reset Followed By Brown-out Detect 19.3.2 SPI Master Timing SS CLK (mode=0,1) tSSH tSSS tCK CLK (mode=2,3) tHI MISO (mode=0,2) tSI tHI MISO (mode=1,3) tSI tVO MOSI (mode=1,3) tVO MOSI (mode=0,2) Figure 43: SPI Timing (Master) Parameter Symbol Min Max Unit Clock period tCK 62.5 - ns Data setup time tSI 16.7 @ 3.3V 18.2 @ 2.7V 21.0 @ 2.
19.3.3 Two-wire Serial Interface SIF_D tF tLOW tSU;DAT tR tSP tHD;STA tR tBUF SIF_CLK S tHD;STA tF tHD;DAT tSU;STA tSU;STO Sr P S tHIGH Figure 44: Two-wire Serial Interface Timing Standard Mode Parameter Fast Mode Symbol SIF_CLK clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SIF_CLK clock HIGH period of the SIF_CLK clock Unit Min Max Min Max fSCL 0 100 0 400 kHz tHD:STA 4 - 0.
19.3.5 Bandgap Reference VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Voltage Min Typ Max Unit 1.156, 1.154 1.192 1.216 V DC power supply rejection 58 dB Temperature coefficient -30 +35 -60 +5 ppm/ºC Point of inflexion +15 ºC Notes at 25ºC 20 to 85ºC -40ºC to 20ºC 20 to 125 ºC -40ºC to 85ºC 19.3.6 Analogue to Digital Converters VDD = 3.0V, VREF = 1.
19.3.7 Comparator VDD = 2.0 to 3.6V -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Analogue response time (normal) Typ Max Unit 85 125,130 ns +/- 250mV overdrive 10pF load 105 + 125,130 ns Digital delay can be up to a max. of two 16MHz clock periods 2.4 2.
19.3.9 32kHz Crystal Oscillator VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Notes Current consumption of cell and counter logic 1.5 1.75, 2.0 µA This is sensitive to the ESR of the crystal, Vdd and total capacitance at each pin Start – up time 0.8 s Assuming xtal with ESR of less than 40kohms and CL= 9pF External caps = 15pF (Vdd/2mV pk-pk) see Appendix B Input capacitance 1.
19.3.11 High-Speed RC Oscillator VDD = 2.0 to 3.6V, -40 to +125ºC, italic +85 ºC Bold +125 ºC Parameter Min Typ Max Unit Current consumption of cell 81 145 250, 275 µA Clock native accuracy -20% 27MHz +26% Calibrated centre frequency accuracy -7% 32.1MHz +7.5% Variation with temperature -0.035, -0.025 Variation with VDD2 -0.65 -0.35 -0.015, 0.010 %/°C -0.2, +0.1 %/V 2.4 us Startup time Notes 19.3.12 Temperature Sensor VDD = 2.0 to 3.
19.3.13 Radio Transceiver This JN5142 meets all the requirements of the IEEE802.15.4 standard over 2.0 - 3.6V and offers the following improved RF characteristics. All RF characteristics are measured single ended. This part also meets the following regulatory body approvals, when used with NXP‟s Module Reference Designs. Compliant with FCC part 15, rules, IC Canada, ETSI ETS 300-328 and Japan ARIB STD-T66 The PCB schematic and layout rules detailed in Appendix B.4 must be followed.
Radio Parameters: 2.0-3.6V, +25ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -92 -95 dBm Nominal for 1% PER, as per 802.15.4 Section 6.5.3.3 +10 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) 19/34 dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) [CW Interferer] [27/49] Alternate channel rejection (-2/+2 ch) 40/45 dBc For 1% PER, with wanted signal 3dB, above sensitivity.
Radio Parameters: 2.0-3.6V, -40ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -93.5 -96.5 dBm Nominal for 1% PER, as per 802.15.4 Section 6.5.3.3 +10 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) 19/34 dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) [CW Interferer] [TBC] Alternate channel rejection (-2/+2 ch) 40/45 dBc For 1% PER, with wanted signal 3dB, above sensitivity.
Radio Parameters: 2.0-3.6V, +85ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -90 -93 dBm Nominal for 1% PER, as per 802.15.4 Section 6.5.3.3 +5 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) 19/34 dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) [CW Interferer] [TBC] Alternate channel rejection (-2/+2 ch) 40/45 dBc For 1% PER, with wanted signal 3dB, above sensitivity.
Radio Parameters: 2.0-3.6V, +125ºC Parameter Min Typical Max Unit Notes Receiver Characteristics Receive sensitivity -88 -91 dBm Nominal for 1% PER, as per 802.15.4 Section 6.5.3.3 0 dBm For 1% PER, measured as sensitivity Adjacent channel rejection (-1/+1 ch) 20/34 dBc For 1% PER, with wanted signal 3dB, above sensitivity. (Note1,2) (modulated interferer) [CW Interferer] [TBC] Alternate channel rejection (-2/+2 ch) 40/45 dBc For 1% PER, with wanted signal 3dB, above sensitivity.
Note1: Blocker rejection is defined as the value, when 1% PER is seen with the wanted signal 3dB above sensitivity, as per 802.15.4 Section 6.5.3.4 Note2: Channels 11,17,24 low/high values reversed. Note3: Up to an extra 2.5dB of attenuation is available if required.
Appendix A Mechanical and Ordering Information A.1 SOT618-1 HVQFN40 40-pin QFN Package Drawing Figure 45: 40-pin QFN Package Drawings UNIT mm A A1 b c max. 0.05 0.30 1 0.2 0.00 0.18 D Dh E Eh e 6.1 4.75 6.1 4.75 0.5 5.9 4.45 5.9 4.45 e1 e2 4.5 4.5 L v w y y1 0.5 0.1 0.05 0.05 0.1 0.3 Table 11: Package Dimensions © NXP Laboratories UK 2012 Plastic or metal protrusions of 0.075 mm maximum per side are not included.
A.2 Footprint information Information for reflow soldering. All dimensions are given in the table underneath. Figure 46: PCB Decal P Ax Ay Bx By C D SLx Sly SPx tot Spy tot SPx Spy Gx Gy Hx Hy 0.500 7.000 7.000 5.200 5.200 0.900 0.290 4.100 4.100 2.400 2.400 0.600 0.600 6.300 6.300 7.250 7.
The PCB schematic and layout rules detailed in Appendix B.4 must be followed. Failure to do so will likely result in the JN5142 failing to meet the performance specification detailed herein and worst case may result in device not functioning in the end application.
A.3 Ordering Information The standard qualification for the JN5142 is extended industrial temperature range: -40ºC to +125ºC, packaged in a 40-pin QFN package. Ordering code format: JN5142N / XXX XXX: ROM Variant: 001 IEEE802.15.
A.4 Device Package Marking The diagram below shows the package markings for JN5142. The package on the left along with the legend information below it, shows the general format of package marking. The package on the right shows the specific markings for a JN5142 device, with revision B ROM software, that came from assembly build number 01 and was manufactured week 25 of 2011.
A.5 Tape and Reel Information A.5.1 Tape Orientation and Dimensions The general orientation of the 40QFN package in the tape is as shown in Figure 48. Figure 48: Tape and Reel Orientation Figure 49 shows the detailed dimensions of the tape used for 6x6mm 40QFN devices. Reference Ao Bo Ko F P1 W Dimensions (mm) 6.30 0.10 6.30 0.10 1.10 0.10 7.500 0.10 12.0 0.10 16.00 +0.30/-0.
A.5.2 Reel Information: 180mm Reel 10 – 1x10 12 Surface Resistivity Between 1x10 Ohms Square Material High Impact Polystyrene, environmentally friendly, recyclable All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 6 window design with one window on each side blanked to allow adequate labelling space.
A.5.3 Reel Information: 330mm Reel 9 11 Surface Resistivity Between 10e – 10e Material High Impact Polystyrene with Antistatic Additive Ohms Square All dimensions and tolerances are fully compliant with EIA-481-B and are specified in millimetres. 3 window design to allow adequate labelling space. Figure 51: 330mm Reel Dimensions A.5.4 Dry Pack Requirement for Moisture Sensitive Material Moisture sensitive material, as classified by JEDEC standard J-STD-033, must be dry packed.
Appendix B Development Support B.1 Crystal Oscillators This Section covers some of the general background to crystal oscillators, to help the user make informed decisions concerning the choice of crystal and the associated capacitors. B.1.1 Crystal Equivalent Circuit Cs Rm Lm Cm C1 Where C2 Cm is the motional capacitance Lm is the motional inductance. This together with Cm defines the oscillation frequency (series) Rm is the equivalent series resistance ( ESR ).
B.1.3 Crystal ESR and Required Transconductance The resistor in the crystal equivalent circuit represents the energy lost. To maintain oscillation, power must be supplied by the amplifier, but how much? Firstly, the Pi connected capacitors C 1 and C2 with CS from the crystal, apply an impedance transformation to Rm, when viewed from the amplifier.
B.2 32MHz Oscillator The JN5142 contains the necessary on-chip components to build a 32 MHz reference oscillator with the addition of an external crystal resonator, two tuning capacitors. The schematic of these components are shown in Figure 52. The two capacitors, C1 and C2, will typically be 15pF ±5% and use a COG dielectric. For a detailed specification of the crystal required and factors affecting C1 and C2 see Appendix B.1.
As is stated above, not all combinations of crystal load capacitance and ESR are valid, and as explained in Appendix B.1.3 there is a trade-off that exists between the load capacitance and crystal ESR to achieve reliable performance. For this reason, we recommend that for a 9pF load capacitance crystals be specified with a maximum ESR of 40 ohms. For lower load capacitances the recommended maximum ESR rises, for example, CL=7pF the max ESR is 61 ohms.
B.3 32kHz Oscillator In order to obtain more accurate sleep periods, the JN5142 contains the necessary on-chip components to build an optional 32kHz oscillator with the addition of an external 32.768kHz crystal and two tuning capacitors. The crystal should be connected between XTAL32K_IN and XTAL32K_OUT (DIO9 and DIO10), with two equal capacitors to ground, one on each pin. The schematic of these components are shown in Figure 53.
Three examples of typical crystals are given, each with the value of external capacitors to use, plus the likely supply current and start-up time that can be expected. Also given is the maximum recommended ESR based on the start-up criteria given in Appendix B.1.3. The values of the external capacitors can be calculated using the equation in Appendix B.1.2 . Load Capacitance Ext Capacitors Current Start-up Time Max ESR 9pF 15pF 1.6µA 0.8Sec 70K 6pF 9pF 1.4µA 0.6sec 80K 12.5pF 22pF 2.
B.4 JN5142 Module Reference Designs For customers wishing to integrate the JN5142 device directly into their system, NXP provide a range of Module Reference Designs, covering standard and high-power modules fitted with different Antennae To ensure the correct performance, it is strongly recommended that where possible the design details provided by the reference designs, are used in their exact form for all end designs, this includes component values, pad dimensions, track layouts etc.
2-wire Serial Port Timer0 TIM0CAP TIM0OUT DIO11 VB_DIG DIO12 DIO13 SIF_CLK VSS2 SIF_D TIM0CK_GT C7: 100nF Analogue IO C16: 100nF UART0/JTAG VDD2 COMP1P 40 1 31 30 COMP1M 2 29 RESETN 3 28 4 27 XTAL_OUT C10: 15pF 39 38 37 XTAL_IN 34 33 32 RXD0 RTS0 VSSA 5 VB_SYNTH 35 TXD0 Y1 C11: 15pF 36 26 6 25 7 24 8 23 CTS0 VB_RAM C15: 100nF C6: 100nF VCOTUNE (NC) VB_VCO SPISELO SS SPIMOSI SDO C2: 10nF VDD1 VDD 9 22 WP VDD C14: 100nF VB_RF L2: 2.
Component Designator Value/Type Function PCB Layout Constraints C13 10µF Power source decoupling C14 100nF Analogue Power decoupling Adjacent to U1 pin 9 C16 100nF Digital power decoupling Adjacent to U1 pin 30 C15 100nF VB Synth decoupling Less than 5mm from U1 pin 6 C2 10nF VB VCO decoupling Less than 5mm from U1 pin 8 C3 100nF VB RF decoupling Less than 5mm from U1 pin 12 and U1 pin 14 C12 47pF VB RF decoupling Less than 5mm from U1 pin 12 and U1 pin 14 C6 100nF VB RAM de
B.4.2 PCB Design and Reflow Profile PCB and land pattern designs are key to the reliability of any electronic circuit design. The Institute for Interconnecting and Packaging Electronic Circuits (IPC) defines a number of standards for electronic devices. One of these is the "Surface Mount Design and Land Pattern Standard" IPC-SM-782 [3], commonly referred to as “IPC782". This specification defines the physical packaging characteristics and land patterns for a range of surface mounted devices.
Related Documents [1] IEEE Std 802.15.4-2006 IEEE Standard for Information Technology – Part 15.4 Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs).
Disclaimers The contents of this document are subject to change without notice. NXP Semiconductors reserves the right to make changes, without notice, in the products, including circuits and/or software, described or contained here in. Information contained in this document regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.
Contact Details NXP Laboratories UK Ltd Furnival Street Sheffield S1 4QT United Kingdom Tel: +44 (0)114 281 2655 Fax: +44 (0) 114 281 2951 For the contact details of your local NXP office or distributor, refer to the NXP web site: www.nxp.
