Manual

Bluespark Technical Overview
25/3/03
D.Swarbrick
Bluespark is a battery operated GPS receiver that transmits the NMEA data to a remote host
using the Bluetooth protocol.
The schematic is divided in to four sections:
Page 1. GPS RF front end and Receiver.
Page 2. GPS processor and flash memory.
Page 3. Bluetooth transceiver/processor and flash memory.
Page 4. Power supplies and logic translation.
GPS RF front end and Receiver.
GPS signals on 1575.42 MHz are picked up by the dielectric patch antenna (P1) and amplified
by the LNA, Q4, whose bias is controlled/switched by Q1.
Q3-A and Q3-B form a high side comparator sensing the voltage across R38 when current is
drawn by an external antenna applied to J2. Q2-A and Q2-B buffer the comparator output
and switch pin diode D10 on while switching Q1 off, thus selecting the external antenna while
shutting off the LNA and hence the internal antenna.
Note that the external antenna is applied after the on board LNA and assumes an active gain
in the order of 18-30dB. (3V source, 5-20mA operating current)
Q14 provides the processor with a level translated, active low flag to indicate that an
external antenna is applied.
U6 is a low noise 2.8V regulator providing power to the RF section and is controlled via the
RFPC0 line from the processor when using trickle mode.
Q15 and Q6 are also controlled from this line and switch off power to the external antenna
when in trickle mode in order to conserve battery power.
Signals from the selected source (either int. or ext. antenna) are presented to FL2, a SAW
filter on 1575.42MHz to remove out of band signals before being input to U4, the SiRF RF IC.
The GPS TCXO, Y5, and resonant circuit C96, L7 provide a clean, stable oscillator source.
The SiRF RF IC uses a superheterodyne principle with a VCO local oscillator on 1565.97MHz
and an IF of 9.45MHz.
2 bit sign and magnitude data is sent to the SiRF processor while RF power and AGC control
signals are received.
GPS processor and flash memory.
The GPS processor is based on the ARM7 CPU and runs a 1.8V core with 3.3V I/O.
It is a true system on a chip and contains at least the following functions:
1Mbit SRAM, Boot ROM, Real Time Clock, GPS DSP, Battery backed SRAM, Beacon DSP, SPI
bus, I/O unit and Dual UARTs.
Refering to page 2 of the schematic, U10 is a voltage monitor providing an active low reset to
the processor if the 3V SiRF Vcc drops below 2.8V. D6 provides a non-return charging path
(when the GPS is active) for the 3V MS Li-Ion battery (BT1) which supplies the RTC and
BBSRAM via U18, a 1.8V regulator, when main batteries/ext power is absent. When either