Lab-NB User Manual Low-Cost Multifunction I/O Board for Macintosh NuBus September 1995 Edition Part Number 320174B-01 © Copyright 1989, 1995 National Instruments Corporation. All Rights Reserved.
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Limited Warranty The Lab-NB is warranted against defects in materials and workmanship for a period of one year from the date of shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace equipment that proves to be defective during the warranty period. This warranty includes parts and labor.
WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on the part of the user or application designer.
Contents About This Manual ............................................................................................................ xi Organization of This Manual .........................................................................................xi Conventions Used in This Manual.................................................................................xii National Instruments Documentation ............................................................................xii Related Documentation.
Contents Chapter 3 Theory of Operation........................................................................................................... 3-1 Functional Overview...................................................................................................... 3-1 NuBus Interface Circuitry.............................................................................................. 3-2 Analog Input and DAQ Circuitry.................................................................................
Contents Programming Considerations......................................................................................... 4-35 Register Programming Considerations .............................................................. 4-35 Initializing the Lab-NB Board ........................................................................... 4-35 Programming the Analog Input Circuitry .......................................................... 4-36 Analog Input Circuitry Programming Sequence....................
Contents Chapter 5 Calibration............................................................................................................................. 5-1 Calibration Equipment Requirements............................................................................ 5-1 Calibration Trimpots...................................................................................................... 5-2 Analog Input Calibration ....................................................................................
Contents Figures Figure 1-1. The Relationship between the Programming Environment, NI-DAQ, and Your Hardware............................................................................................................ 1-3 Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 2-8. Figure 2-9. Figure 2-10. Figure 2-11. Figure 2-12. Figure 2-13. Figure 2-14. Figure 2-15. Figure 2-16. Figure 2-17. Figure 2-18. Parts Locator Diagram ........................................
Contents Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Bipolar Input Mode A/D Conversion Values (Two’s Complement Coding) .... 4-38 Analog Output Voltage Versus Digital Code .................................................... 4-53 Analog Output Voltage Versus Digital Code (Bipolar Mode, Two's Complement Coding)..................................................... 4-54 Mode 0 I/O Configurations................................................................................
About This Manual This manual describes the mechanical and electrical aspects of the Lab-NB and contains information concerning its installation and operation. The Lab-NB is a low-cost multifunction analog, digital, and timing I/O board for Macintosh NuBus computers.
About This Manual • The Glossary contains an alphabetical list and description of terms used in this manual, including abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms. • The Index alphabetically lists topics covered in this manual, including the page where you can find each one. Conventions Used in This Manual The following conventions are used in this manual. bold Bold text denotes menus, menu items, or dialog box buttons or options.
About This Manual • Your DAQ hardware user manuals—These manuals have detailed information about the DAQ hardware that plugs into or is connected to your computer. Use these manuals for hardware installation and configuration instructions, specification information about your DAQ hardware, and application hints. • Software manuals—Examples of software manuals you may have are the LabVIEW and LabWindows®/CVI manual sets and the NI-DAQ manuals (a 4.6.
Chapter 1 Introduction This chapter describes the Lab-NB, lists what you need to get started, software programming choices, optional equipment, and explains how to unpack the Lab-NB. About the Lab-NB Thank you for buying the National Instruments Lab-NB. The Lab-NB is a low-cost multifunction analog, digital, and timing I/O board for Macintosh NuBus computers.
Introduction Chapter 1 What You Need to Get Started To set up and use your Lab-NB board, you will need the following: Lab-NB board Lab-NB User Manual One of the following software packages and documentation: NI-DAQ software for Macintosh LabVIEW for Macintosh Your computer Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware. You can use LabVIEW, LabWindows/CVI, or NI-DAQ. A 4.6.
Chapter 1 Introduction NI-DAQ Driver Software The NI-DAQ driver software is included at no charge with all National Instruments DAQ hardware. NI-DAQ is not packaged with SCXI or accessory products, except for the SCXI-1200. NI-DAQ has an extensive library of functions that you can call from your application programming environment.
Introduction Chapter 1 Register-Level Programming The final option for programming any National Instruments DAQ hardware is to write registerlevel software. Writing register-level programming software can be very time-consuming and inefficient, and is not recommended for most users. Even if you are an experienced register-level programmer, consider using NI-DAQ, LabVIEW, or LabWindows/CVI to program your National Instruments DAQ hardware.
Chapter 1 Introduction The Lab-NB I/O connector is a 50-pin male ribbon cable header. The manufacturer part numbers used by National Instruments for this header are as follows: • Electronic Products Division/3M (part number 3596-5002) • T&B/Ansley Corporation (part number 609-500) The mating connector for the Lab-NB is a 50-position, polarized, ribbon socket connector with strain relief.
Chapter 2 Configuration and Installation This chapter describes how to configure and install the Lab-NB into your Macintosh computer, and also includes signal connections to the Lab-NB and cable wiring. Board Configuration The Lab-NB contains three jumpers for changing the analog input and output configuration of the board. The jumpers are shown in the parts locator diagram in Figure 2-1. Jumpers W1 and W2 configure the two analog outputs.
Configuration and Installation Chapter 2 3 2 1 1 2 3 W1 W2 W3 Figure 2-1.
Chapter 2 Configuration and Installation Factory Default Jumper Settings The Lab-NB is shipped from the factory with the following configuration: • Jumpers W1 and W2–bipolar analog output • Jumper W3–bipolar analog input Table 2-1 lists all the available jumper configurations for the Lab-NB with the factory defaults noted. Table 2-1.
Configuration and Installation Chapter 2 W1 Channel 0 A B C A B C W2 Channel 1 Figure 2-2. Bipolar Output Jumper Configuration Unipolar Output Selection You can select the unipolar (0 to 10 V) output configuration for either analog output channel by setting the following jumpers: Analog Output Channel 0 W1 B-C Analog Output Channel 1 W2 B-C This configuration is shown in Figure 2-3. W1 Channel 0 A B C W2 Channel 1 A B C Figure 2-3.
Chapter 2 Configuration and Installation W3 A B C Figure 2-4. Bipolar Input Jumper Configuration Unipolar Input Selection You can select the unipolar (0 to 10 V) input configuration by setting the following jumper: Analog Input W3 B-C This configuration is shown in Figure 2-5. W3 A B C Figure 2-5. Unipolar Input Jumper Configuration Note: If you are using a software package such as NI-DAQ or LabVIEW, you may need to reconfigure your software to reflect any changes in jumper or switch settings.
Configuration and Installation Chapter 2 Warning: Connections that exceed any of the maximum ratings of input or output signals on the Lab-NB may result in damage to the Lab-NB board and to the Macintosh computer. This includes connecting any power signals to ground and vice versa. National Instruments is NOT liable for any damages resulting from any such signal connections.
Chapter 2 Configuration and Installation Signal Connection Descriptions Pin Signal Name Description 1-8 ACH<0..7> Analog input channels 0 through 7 (single-ended). 9 AIGND Analog input ground. 10 DAC0 OUT Voltage output signal for analog output channel 0. 11 AOGND Analog output ground. 12 DAC1 OUT Voltage output signal for analog output channel 1. 13 DGND Digital ground. 14–21 PA<0..7> Bidirectional data lines for port A. PA7 is the MSB, PA0 the LSB. 22–29 PB<0..
Configuration and Installation Chapter 2 cause conversions to occur; it cannot be used as a monitor to detect conversions caused by the onboard sample-interval timer. The following input ranges and maximum ratings apply to inputs ACH<0..7>: Input impedance 0.
Chapter 2 Configuration and Installation Analog Output Signal Connections Pins 10 through 12 of the I/O connector are analog output signal pins. Pins 10 and 12 are the DAC0 OUT and DAC1 OUT signal pins. DAC0 OUT is the voltage output signal for Analog Output Channel 0. DAC1 OUT is the voltage output signal for Analog Output Channel 1. Pin 11, AOGND, is the ground reference point for both analog output channels as well as analog input.
Configuration and Installation Chapter 2 Digital I/O Signal Connections Pins 13 through 37 of the I/O connector are digital I/O signal pins. Digital I/O on the Lab-NB is designed around the 82C55A integrated circuit. The 82C55A is a general-purpose PPI containing 24 programmable I/O pins. These pins represent the three 8-bit ports (PA, PB, and PC) of the 82C55A. Pins 14 through 21 are connected to the digital lines PA<0..7> for digital I/O port A.
Chapter 2 Configuration and Installation Figure 2-9 illustrates signal connections for three typical digital I/O applications. +5 V LED Port A 14 PA0 PA<7..0> Port B 22 PB0 PB<7..0> TTL Signal 30 PC0 +5 V Port C PC<7..0> Switch 13 DGND I/O Connector Lab-NB Board Figure 2-9. Digital I/O Connections In Figure 2-9, port A is configured for digital output, and ports B and C are configured for digital input.
Configuration and Installation Chapter 2 Table 2-2. Port C Signal Assignments Programming Mode Group A Group B PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Mode 0 I/O I/O I/O I/O I/O I/O I/O I/O Mode 1 Input I/O I/O IBF A STBA* INTRA STBB* IBFBB INTRB Mode 1 Output OBFA* ACKA* I/O I/O INTRA ACKB* OBFB* INTRB Mode 2 OBFA* ACKA* IBF A STBA* INTRA I/O I/O I/O * Indicates that the signal is active low.
Chapter 2 Configuration and Installation The following signals are used in the timing diagrams shown later in this chapter: Pin Direction Description STB* Input Strobe Input—A low signal on this handshaking line loads data into the input latch. IBF Output Input Buffer Full—A high signal on this handshaking line indicates that data has been loaded into the input latch. This is basically an input acknowledge signal.
Configuration and Installation Chapter 2 Mode 1 Input Timing The following figure illustrates the timing specifications for an input transfer in mode 1. T1 T2 T4 STB * T7 IBF T6 INTR RD * T5 T3 DATA Name Description T1 T2 T3 T4 T5 T6 T7 STB* pulse width STB* = 0 to IBF = 1 Data before STB* = 1 STB* = 1 to INTR = 1 Data after STB* = 1 RD* = 0 to INTR = 0 RD* = 1 to IBF = 0 Minimum Maximum 100 – 20 – 50 – – – 150 – 150 – 200 150 All timing values are in nanoseconds.
Chapter 2 Configuration and Installation Mode 1 Output Timing The following figure illustrates the timing specifications for an output transfer in mode 1. T3 WR* T4 OBF* T1 T6 INTR T5 ACK* DATA T2 Name Description T1 T2 T3 T4 T5 T6 WR* = 0 to INTR = 0 WR* = 1 to output WR* = 1 to OBF* = 0 ACK* = 0 to OBF* = 1 ACK* pulse width ACK* = 1 to INTR = 1 Minimum Maximum – – – – 100 – 250 200 150 150 – 150 All timing values are in nanoseconds.
Configuration and Installation Chapter 2 Mode 2 Bidirectional Timing The following figure illustrates the timing specifications for bidirectional transfers in mode 2.
Chapter 2 Configuration and Installation Timing Connections Pins 38 through 48 of the I/O connector are connections for timing I/O signals. The timing I/O of the Lab-NB is designed around the 8253 Counter/Timer integrated circuit. Two of these integrated circuits are employed in the Lab-NB. One, designated 8253(A), is used exclusively for DAQ timing, and the other, 8253(B), is available for general use.
Configuration and Installation Chapter 2 effect until a new DAQ sequence is established. Figures 2-11 and 2-12 illustrate two possible posttrigger DAQ timing cases. In Figure 2-11, the rising edge on EXTTRIG is sensed when the EXTCONV* input is high. Thus, the first A/D conversion occurs on the second falling edge of EXTCONV*, after the rising edge on EXTTRIG. In Figure 2-12, the rising edge on EXTTRIG is sensed when the EXTCONV* input is low.
Chapter 2 Configuration and Installation If PRETRIG is set, EXTTRIG serves as a pretrigger signal. In pretrigger mode, A/D conversions are enabled via software before a rising edge is sensed on the EXTTRIG input. However, the sample counter, counter A1, is not gated on until a rising edge is sensed on the EXTTRIG input. Additional transitions on this line have no effect until a new DAQ sequence is set up.
Configuration and Installation Chapter 2 EXTUPDATE* text DAC OUTPUT UPDATE TMRINTUP DACWRT text Minimum 50 nsec Figure 2-14. Waveform Generation Timing with the EXTUPDATE* Signal Since a rising edge on the EXTUPDATE* signal always sets the TMRINTUP bit in the Interrupt Status Register, the EXTUPDATE* signal can also be used for periodic interrupt generation timed by an external source. The TMRINTUP bit is cleared by writing to either of the two DACs or to the TMRINTCL bit location.
Chapter 2 Configuration and Installation 8253 digital input specifications (referenced to DGND): VIH input logic high voltage 2.2 V min VIL input logic low voltage 0.8 V max Input load current ±10 µA max 8253 digital output specifications (referenced to DGND): VOH output logic high voltage 2.4 V min VOL output logic low voltage 0.45 V max IOH output source current, at VOH 400 µA max IOL output sink current, at VOL 2.
Configuration and Installation Chapter 2 +5 V 4.7 kΩ CLK OUT GATE Switch Signal Source Counter (from Group B) 13 DGND I/O Connector Lab-NB Board Figure 2-16. Event-Counting Application with External Switch Gating Pulse-width measurement is performed by level gating. The pulse to be measured is applied to the counter GATE input. The counter is loaded with the known count and is programmed to count down while the signal at the GATE input is high.
Chapter 2 Configuration and Installation +5 V 4.7 kΩ CLK OUT GATE Signal Source Gate Source Counter 13 DGND I/O Connector Lab-NB Board Figure 2-17. Frequency Measurement Application The GATE, CLK, and OUT signals for counters B1 and B2 are available at the I/O connector. In addition, the GATE and CLK pins are pulled up to +5 V through a 4.7 kΩ resistor. The input and output ratings and timing specifications for the 8253 signals are given next.
Configuration and Installation Chapter 2 Figure 2-18 shows the timing requirements for the GATE and CLK input signals and the timing specifications for the OUT output signals of the 8253.
Chapter 3 Theory of Operation This chapter contains a functional overview of the Lab-NB and explains the operation of each functional unit making up the Lab-NB. Functional Overview The block diagram in Figure 3-1 shows a functional overview of the Lab-NB board.
Theory of Operation Chapter 3 The following are the major components making up the Lab-NB board: • NuBus interface circuitry • Analog input and DAQ circuitry • Analog output circuitry • Digital I/O circuitry • Timing I/O circuitry DAQ functions can be executed by using the analog input circuitry and some of the timing I/O circuitry. The internal data and control buses interconnect the components. The theory of operation for each of these components is explained in the remainder of this chapter.
Chapter 3 Theory of Operation The starting-address-detecting circuitry on the Lab-NB matches address lines 23 through 21 to the starting address specified by the slot in which the Lab-NB board is installed. The remaining address lines (19 through 0) are decoded by the Lab-NB address-decoding circuitry to generate select signals for the registers on the board.
Theory of Operation Chapter 3 Analog Input Circuitry The analog input circuitry consists of an input multiplexer, a software-programmable gain amplifier, a 12-bit ADC, and a 12-bit FIFO memory that is sign-extended to 16 bits. The input multiplexer is made up of a CMOS analog input multiplexer and has eight analog input channels (channels 0 through 7). The input multiplexers provide input overvoltage protection of ±45 V, powered on or off.
Chapter 3 Theory of Operation multichannel (scanned) data acquisition. Scanned data acquisition uses a counter to automatically switch between analog input channels during data acquisition. DAQ timing consists of signals that initiate a DAQ operation, initiate individual A/D conversions, gate the DAQ operation, and generate scanning clocks. Sources for these signals are supplied mainly by timers on the Lab-NB board. One of the two 8253 integrated circuits is reserved for this purpose.
Theory of Operation Chapter 3 DAQ Rates Maximum DAQ rates (number of samples per second) are determined by the conversion period of the ADC plus the sample-and-hold acquisition time. During multichannel scanning, the DAQ rates are further limited by the settling time of the input multiplexers and programmable gain amplifier.
Chapter 3 Theory of Operation The recommended DAQ rates given in Table 3-2 assume that voltage levels on all the channels included in the scan sequence are within range for the given gain and are driven by lowimpedance sources. The signal ranges for the possible gains are shown in Table 3-3 and Table 3-4. Signal levels outside the ranges shown in Table 3-3 on the channels included in the scan sequence adversely affect the input settling time.
Theory of Operation Chapter 3 TWOSDA0 DAC0WR Coding DAC0 DAC0 OUT Ref Data I/O Connector NuBus Interface DAC1WR AGND 5 V Internal Reference 12 Ref DAC1 Coding DAC1 OUT Counter A2 TWOSDA1 EXTUPDATE* CNFGWR DAC Configuration Register TWOSDA1 TMRWGN1 TWOSDA0 TMRWGN0 Figure 3-4. Analog Output Circuitry Block Diagram Each analog output channel contains a 12-bit DAC.
Chapter 3 Theory of Operation corresponding to an LSB change in the digital code word. For both unipolar and bipolar output, one LSB corresponds to the following formula: 10 V 4,096 Digital I/O Circuitry The digital I/O circuitry is designed around an 82C55A integrated circuit. The 82C55A is a general-purpose PPI containing 24 programmable I/O pins. These pins represent the three 8-bit I/O ports (A, B, and C) of the 82C55A as well as PA<0..7>, PB<0..7>, and PC<0..7> on the Lab-NB I/O connector.
Theory of Operation Chapter 3 All three ports on the 82C55A are TTL-compatible. When enabled, the digital output ports are capable of sinking 2.5 mA of current and sourcing 2.5 mA of current on each digital I/O line. When the ports are not enabled, the digital I/O lines act as high-impedance inputs. Timing I/O Circuitry The Lab-NB uses two 8253 Counter/Timer integrated circuits for DAQ timing and for generalpurpose timing I/O functions.
Chapter 3 Theory of Operation Each 8253 contains three independent 16-bit counter/timers and one 8-bit Mode Register. As shown in Figure 3-6, counter group A is reserved for DAQ timing, and counter group B is free for general use. The output of counter B0 can be used in place of the 1-MHz clock source on counter A0 to allow clock periods greater than 65,536 µsec. All six counter/timers can be programmed to operate in several useful timing modes.
Chapter 4 Register-Level Programming This chapter describes in detail the address and function of each of the Lab-NB control and status registers. This chapter also includes important information about register-level programming the Lab-NB. Note: If you plan to use a programming software package such as NI-DAQ or LabVIEW with your Lab-NB board, you need not read this chapter. Register Access The Macintosh uses memory mapping to access boards in the system.
Register-Level Programming Chapter 4 Table 4-1.
Chapter 4 Register-Level Programming Table 4-2.
Register-Level Programming Chapter 4 Register Sizes The Macintosh permits three different memory word sizes for memory read and write operations–byte (8-bit), half-word (16-bit), and word (32-bit). Table 4-2 shows the word sizes of the Lab-NB registers. For example, reading the A/D FIFO Register requires a 16-bit read operation at the specified address. Register Descriptions Table 4-2 divides the Lab-NB registers into six different register groups.
Chapter 4 Register-Level Programming Analog Input Register Group The four registers making up the Analog Input Register Group control the analog input circuitry and are used for reading from the A/D FIFO. The A/D Configuration Register selects the input channel to be read, the gain for that channel, and some information about the input data. The Status Register reports the status of the current A/D conversion and returns any errors found.
Register-Level Programming Chapter 4 A/D Configuration Register The A/D Configuration Register indicates the input channel to be read and the gain for the analog input circuitry. Address: Base address + 0 8000 (hex) Type: Write-only Word Size: 16-bit Bit Map: 15 14 13 12 11 10 9 8 X X X X X TBSEL EXTTRIGEN PRETRIG 7 6 5 4 3 2 1 0 SCANEN MA2 MA1 MA0 GAIN2 GAIN1 GAIN0 TWOSCMP Bit Name Description 15–11 X Don’t care bits.
Chapter 4 Register-Level Programming Bit Name Description (continued) 8 PRETRIG Pretrigger Bit—This bit is used to set the pretriggering feature on the Lab-NB. It also supersedes any setting in the EXTTRIGEN bit described earlier. If PRETRIG is cleared, then the function of the EXTTRIG line on the I/O connector is determined by EXTTRIGEN. If PRETRIG is set, then the EXTTRIG line becomes a pretrigger.
Register-Level Programming Bit Name Chapter 4 Description (continued) Channel Scanning later in this chapter for the correct sequence involved in setting the SCANEN bit. 3–1 GAIN<2..0> Gain Bit—These three bits select the gain setting as follows: GAIN<2..0> 000 001 010 011 100 101 110 111 0 TWOSCMP Lab-NB User Manual Selected Gain 1 1.25 2 5 10 20 50 100 Two’s Complement Bit—This bit selects the format of the coding of the output of the ADC.
Chapter 4 Register-Level Programming Status Register The Status Register indicates the status of the current A/D conversion. The bits in this register determine if a conversion is being performed or if data is available and any errors have been found. Address: Base address + 0 8000 (hex) Type: Read-only Word Size: 8-bit Bit Map: 7 6 5 4 X X X GATA1 3 2 OVERRUN OVERFLOW 1 0 GATA0 DAVAIL Bit Name Description 7–5 X Don’t care bits.
Register-Level Programming Chapter 4 A/D FIFO Register Reading the A/D FIFO Register returns the next A/D conversion value stored in the A/D FIFO. Whenever the A/D FIFO Register is read, the value read is removed from the A/D FIFO, thereby freeing space for another A/D conversion value to be stored. Values are stored into the A/D FIFO Register by the ADC whenever an A/D conversion is complete. Although A/D conversion values are in 12-bit format, they are automatically sign-extended to 16 bits in the FIFO.
Chapter 4 Register-Level Programming A/D FIFO Register (continued) Bit Map: Two’s complement binary mode 15 14 13 12 Sign Extension Bits 11 10 9 8 D11 D10 D9 D8 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 15– 0 D<15..0> Data Bit—These bits contain the 16-bit, sign-extended two's complement result of a 12-bit A/D conversion. Values read, therefore, range from -2,048 to +2,047 decimal (F800 to 07FF hex).
Register-Level Programming Chapter 4 A/D Clear Register The ADC can be reset by writing to this register. This operation clears the FIFO and loads the last conversion value into the FIFO. All error bits in the Status Register are cleared as well. Notice that the FIFO contains one data word after reset, so a FIFO read is necessary after reset to empty the FIFO. The data that is read should be ignored.
Chapter 4 Register-Level Programming Analog Output Register Group The four registers making up the Analog Output Register Group are used for loading the two 12-bit DACs in the two analog output channels. DAC0 controls analog output channel 0. DAC1 controls analog output channel 1. These DACs can be written to individually or simultaneously. Bit descriptions of the registers making up the Analog Output Register Group are given on the following pages.
Register-Level Programming Chapter 4 DAC Configuration Register This register determines if data written to the DACs is in straight binary or two’s complement form. It also configures the DACs to output data automatically at a rate controlled by counter A2 OR EXTUPDATE*. This feature is particularly useful for automatic waveform generation.
Chapter 4 Register-Level Programming DAC0 and DAC1 Data Registers Writing to these registers loads the corresponding analog output channel DAC, thereby updating the voltages generated by the analog output channels. The voltage is updated immediately, unless the TMRWGN bit for that DAC is set. If this bit is set, then the voltages are not updated until the next pulse from counter A2 or the next low-to-high transition on the EXTUPDATE* line on the I/O connector.
Register-Level Programming Chapter 4 8253 Counter/Timer Register Groups The eight registers making up the two Counter/Timer Register Groups access the two onboard 8253 Counter/Timers. Each 8253 has three counters. For convenience, the two Counter/Timer Groups and their respective 8253 integrated circuits have been designated A and B. The three counters of group A control onboard DAQ timing and waveform generation. The three counters of group B are available for general-purpose timing functions.
Chapter 4 Register-Level Programming Counter A0 Data Register The Counter A0 Data Register is used for loading and reading back contents of 8253(A) counter 0. Address: Base address + 4 0000 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..0> Data Bit—8-bit counter A0 contents.
Register-Level Programming Chapter 4 Counter A1 Data Register The Counter A1 Data Register is used for loading and reading back contents of 8253(A) counter 1. Address: Base address + 4 0010 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..0> Data Bit—8-bit counter A1 contents.
Chapter 4 Register-Level Programming Counter A2 Data Register The Counter A2 Data Register is used for loading and reading back contents of 8253(A) counter A2. Address: Base address + 4 0020 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..0> Data Bit—8-bit counter A2 contents.
Register-Level Programming Chapter 4 Counter A Mode Register The Counter A Mode Register determines the operation mode for each of the three counters on the 8253(A) chip. The Counter A Mode Register selects the counter involved, its read/load mode, its operation mode (that is, any of the 8253’s six operation modes), and the counting mode (binary or BCD counting). The Counter A Mode Register is an 8-bit register. Bit descriptions for each of these bits are given in Appendix C, AMD 8253 Data Sheet.
Chapter 4 Register-Level Programming Counter B0 Data Register The Counter B0 Data Register is used for loading and reading back the contents of 8253(B) counter 0. Address: Base address + 4 8000 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..0> Data Bit—8-bit counter B0 contents.
Register-Level Programming Chapter 4 Counter B1 Data Register The Counter B1 Data Register is used for loading and reading back the contents of 8253(B) counter 1. Address: Base address + 4 8010 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..0> Data Bit—8-bit counter B1 contents.
Chapter 4 Register-Level Programming Counter B2 Data Register The Counter B2 Data Register is used for loading and reading back the contents of 8253(B) counter 2. Address: Base address + 4 8020 (hex) Type: Read-and-write Word Size: 8-bit Bit Map: 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit Name Description 7–0 D<7..0> Data Bit—8-bit counter B2 contents.
Register-Level Programming Chapter 4 Counter B Mode Register The Counter B Mode Register determines the operation mode for each of the three counters on the 8253(B) chip. The Counter B Mode Register selects the counter involved, its read/load mode, its operation mode (that is, any of the 8253’s six operation modes), and the counting mode (binary or BCD counting). The Counter Mode Register is an 8-bit register. Bit descriptions for each of these bits are given in Appendix C, AMD 8253 Data Sheet.
Chapter 4 Register-Level Programming 82C55A Digital I/O Register Group Digital I/O on the Lab-NB uses an 82C55A integrated circuit. The 82C55A is a general-purpose PPI containing 24 programmable I/O pins. These pins represent the three 8-bit I/O ports (A, B, and C) of the 82C55A. These ports can be programmed as two groups of 12 signals or as three individual 8-bit ports.
Register-Level Programming Chapter 4 Port A Register Reading the Port A Register returns the logic state of the eight digital I/O lines constituting port A, that is, PA<0..7>. If port A is configured for output, the Port A Register can be written to in order to control the eight digital I/O lines constituting port A. See Programming the Digital I/O Circuitry later in this chapter for information on how to configure port A for input or output.
Chapter 4 Register-Level Programming Port B Register Reading the Port B Register returns the logic state of the eight digital I/O lines constituting port B, that is, PB<0..7>. If port B is configured for output, the Port B Register can be written to in order to control the eight digital I/O lines constituting port B. See Programming the Digital I/O Circuitry later in this chapter for information on how to configure port B for input or output.
Register-Level Programming Chapter 4 Port C Register Port C is special in the sense that it can be used as an 8-bit I/O port like port A and port B if neither port A nor port B is used in handshaking (latched) mode. If either port A or port B is configured for latched I/O, some of the bits in port C are used for handshaking signals. See Programming the Digital I/O Circuitry later in this chapter for a description of the individual bits in the Port C Register.
Chapter 4 Register-Level Programming Digital Control Register The Digital Control Register can be used to configure port A, port B, and port C as inputs or outputs as well as selecting simple mode (basic I/O) or handshaking mode (strobed I/O) for transfers. See Programming the Digital I/O Circuitry later in this chapter for a description of the individual bits in the Digital Control Register.
Register-Level Programming Chapter 4 Interrupt Control Register Group This group is made up of two registers. Writing to the Interrupt Control Register enables the interrupt facility on the Lab-NB. The Interrupt Status Register contains information about the Interrupt Control Register and the interrupt line. Bit descriptions of the registers making up the Interrupt Control Group are given on the following pages.
Chapter 4 Register-Level Programming Interrupt Control Register Setting bits of this register causes an interrupt to occur when the current process is complete. Address: Base address + 1 0000 (hex) Type: Write-only Word Size: 8-bit Bit Map: 7 6 5 4 3 2 X X X X PAINTEN PBINTEN 1 0 TMRINTEN ADCINTEN Bit Name Description 7–4 X Don’t care bits. 3 PAINTEN Port A Interrupt Enable Bit—This bit enables or disables generation of an interrupt via PC3.
Register-Level Programming Bit Name Chapter 4 Description (continued) the Timer Interrupt Clear Register. This interrupt allows waveform generation on the analog output because the same signal that sets the interrupt also updates the DAC output if the corresponding TMRWG bit in the DAC Configuration Register is set. If this bit is cleared, interrupts from EXTUPDATE* and counter A2 output are ignored.
Chapter 4 Register-Level Programming Interrupt Status Register The Interrupt Status Register indicates the status of the Interrupt Control Register bits and the interrupt lines. Address: Base address + 1 0000 (hex) Type: Read-only Word Size: 8-bit Bit Map: 7 6 5 4 X X INT TIMERUP 3 2 1 0 *PAINTEN *PBINTEN *TMRINTEN *ADCINTEN Bit Name Description 7, 6 X Don’t care bits. 5 INT Interrupt Bit—This bit shows the overall state of interrupts generated by the Lab-NB board.
Register-Level Programming Chapter 4 Timer Interrupt Clear Register Writing to the Timer Interrupt Clear Register clears the TIMERUP bit in the Interrupt Status Register. The Timer Interrupt Clear Register can be used to service any timer-related or EXTUPDATE*-caused interrupts generated by the Lab-NB. This register provides an alternate means of clearing timer-generated interrupts besides writing to one or both of the DACs.
Chapter 4 Register-Level Programming Configuration EPROM The Configuration EPROM is an onboard read-only memory that contains information required by the Macintosh operating system. The Macintosh system Slot Manager reads the Configuration EPROM upon system startup. The Configuration EPROM is mapped to address offset locations F 8000 through F FFFC. The EPROM is 8 bits (1 byte) wide and 8 kilobytes in length.
Register-Level Programming Chapter 4 4. Write 0000 (hex) to the A/D Configuration Register (16-bit write). 5. Write 00 (hex) to the A/D Clear Register (8-bit write). 6. Read the data from the A/D FIFO Register (16-bit read). Ignore the data. 7. Write 0000 (hex) to the DAC0 Data Register if DAC0 is configured for unipolar output. Write 0800 (hex) to the DAC0 Data Register if DAC0 is configured for bipolar output. 8. Write 0000 (hex) to the DAC1 Data Register if DAC1 is configured for unipolar output.
Chapter 4 Register-Level Programming 1. Select analog input channel and gain. The analog input channel and gain are selected by writing to the A/D Configuration Register. See the A/D Configuration Register bit description earlier in this chapter for gain and analog input channel bit patterns. Set up the bits as given in the A/D Configuration Register bit description, and write to the A/D Configuration Register.
Register-Level Programming Chapter 4 used for A/D timing, the DAVAIL bit should be set after 12 msec or after a rising edge in EXTCONV*, whichever occurs later. An A/D FIFO overflow condition occurs if more than 16 conversions are initiated and stored in the A/D FIFO before the A/D FIFO Register is read. If this condition occurs, the OVERFLOW bit is set in the Status Register to indicate that one or more A/D conversion results have been lost because of FIFO overflow.
Chapter 4 Register-Level Programming Clearing the Analog Input Circuitry The analog input circuitry can be cleared by writing to the A/D Clear Register, which leaves the analog input circuitry in the following state: • Analog input error flags OVERFLOW and OVERRUN are cleared. • Pending interrupt requests are cleared. • A/D FIFO has one garbage word of data. Empty the A/D FIFO before starting any A/D conversions by performing a read on the A/D FIFO Register and ignoring the data read.
Register-Level Programming Chapter 4 Programming in Controlled Acquisition Mode The following programming steps are required for a DAQ operation in controlled acquisition mode: 1. Select analog input channel, gain, and timebase source for counter A0. 2. Program counter B0 (if necessary). 3. Program counters A0 and A1. 4. Clear the A/D circuitry. 5. Program the sample-interval counter (counter A0). 6. Service the DAQ operation. Each of these programming steps is explained below. 1.
Chapter 4 Register-Level Programming 3. Program counters A0 and A1. This step involves programming counter A0 to generate periodic conversion pulses and programming counter A1 to interrupt on terminal count mode (mode 0). Counter A0 of the 8253(A) Counter/Timer is used as the sample-interval counter. A high-to-low transition on the counter A0 output initiates a conversion. Counter A0 can be programmed to generate a pulse once every N µsec.
Register-Level Programming Chapter 4 Use the following programming sequence to program the sample-interval counter. All writes are 8-bit write operations. All values given are hexadecimal. a. Write 34 to the Counter A Mode Register (select counter A0, mode 2). b. Write the least significant byte of the sample interval to the Counter A0 Data Register. c. Write the most significant byte of the sample interval to the Counter A0 Data Register. 6. Service the DAQ operation.
Chapter 4 Register-Level Programming Programming in Freerun Acquisition Mode Freerun acquisition mode uses only counter A0 as the sample-interval counter. The number of A/D conversions that have occurred (that is, the sample count) is maintained by software in this case. With this arrangement, DAQ operations can acquire more than 65,535 samples. The following programming steps are required for a DAQ operation in freerun acquisition mode: 1. Select analog input channel, gain, and timebase for counter A0.
Register-Level Programming Chapter 4 c. Write the most significant byte of the timebase count to the Counter B Data Register. For example, programming a timebase of 10 µsec requires a timebase count of 10 µsec = 20 µsec 0.5 µsec 3. Program counter A0 to force OUT0 high. Counter A0 of the 8253(A) Counter/Timer is used as the sample-interval counter. A high-to-low transition on OUT0 (counter A0 output) initiates a conversion. Counter A0 can be programmed to generate a pulse once every N µsec.
Chapter 4 Register-Level Programming 7. Service the DAQ operation. Once the DAQ operation is started by writing the most significant byte of the sample interval to the Counter A0 Data Register, the operation must be serviced by reading the A/D FIFO Register every time an A/D conversion result becomes available. To do this, perform the following sequence until the desired number of conversion results has been read: a. Read the Status Register (8-bit read). b.
Register-Level Programming Chapter 4 Using the EXTTRIG Signal to Terminate a Multiple A/D Conversion DAQ Operation (Pretrigger Mode) If the PRETRIG bit is set in the ADC Command Register, EXTTRIG functions as a stop trigger for a multiple A/D conversion DAQ operation. In this mode, referred to as pretriggering, the sample counter is gated off until a low-to-high edge is sensed on EXTTRIG. Pretriggering is performed in a manner similar to external triggering.
Chapter 4 Register-Level Programming 4. Clear the A/D circuitry. 5. Program counter A1 and enable EXTCONV* and EXTTRIG input. 6. Service the DAQ operation. Each of these programming steps is explained as follows. 1. Disable EXTCONV* and EXTTRIG input. The EXTCONV* bit can be disabled by setting the GATA0 bit low. The GATA0 bit is low whenever OUTA1 is high, regardless of the settings for the PRETRIG or EXTTRIGEN bits in the ADC Configuration Register or the EXTTRIG signal.
Register-Level Programming Chapter 4 To program the counters, use the following programming sequence: a. Write 70 (hex) to the Counter A Mode Register (select counter A1, mode 0). This step sets the output of counter A1 (OUTA1) low, which in turn enables EXTTRIG; that is, the first rising edge on EXTTRIG after OUTA1 goes low starts the DAQ sequence. b. Write the least significant byte of (M-1), where M is the sample count, to the Counter A1 Data Register. c.
Chapter 4 Register-Level Programming Pretrigger Mode The following programming steps are required for a DAQ operation in controlled acquisition mode using EXTCONV*. In the following programming sequence, EXTTRIG is used as a pretrigger signal; that is, A/D conversions are enabled but the sample count is not started until a rising edge is detected on the EXTTRIG input. Data acquisition remains enabled for the programmed count after the rising edge on the EXTTRIG input.
Register-Level Programming Chapter 4 4. Clear the A/D circuitry. Before the DAQ operation is started, the A/D FIFO must be emptied in order to clear any old A/D conversion results. Empty the A/D FIFO after the counters are programmed because programming the counters can cause spurious edges. Write 0 to the A/D Clear Register to empty the FIFO (8-bit write) and to read from the A/D FIFO (16-bit read). Ignore the data obtained while reading the A/D Clear Register.
Chapter 4 Register-Level Programming Two error conditions may occur during a DAQ operation: an overflow error or an overrun error. These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the DAVAIL bit. An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more data.
Register-Level Programming Chapter 4 channel 3, channel 2, channel 1, channel 0, channel 3, channel 2, channel 1, channel 0, channel 3, and so on. Note: Select the analog input channel and gain in the following order: 1. Write the configuration value indicating the highest channel number in the scan sequence, the gain, and the input polarity to the A/D Configuration Register. The SCANEN bit must be cleared during this first write to the A/D Configuration Register. 2.
Chapter 4 Register-Level Programming by jumper settings described in Chapter 2, Configuration and Installation. Table 4-5 shows the output voltage versus digital code for a unipolar analog output configuration. Table 4-6 shows the voltage versus digital code for a bipolar analog output configuration. The following formula calculates the voltage output versus digital code for a unipolar analog output configuration and straight binary coding: digital code V out = 10.
Register-Level Programming Chapter 4 Table 4-6. Analog Output Voltage Versus Digital Code (Bipolar Mode, Two’s Complement Coding) Digital Code (Decimal) (Hex) -2,048 -1,024 0 1,024 2,047 Voltage Output (Vref = 10 V) F800 FC00 0000 0400 07FF -5.0 V -2.5 V 0.0 V 2.5 V 4.9976 V Interrupt Programming for the Analog Output Circuitry Interrupts can be used for writing successive values in a sequence to the DAC Data Registers during a waveform generation operation.
Chapter 4 Register-Level Programming 3. Install an interrupt service routine. You must install an interrupt service routine for the slot containing the Lab-NB. Consult the Inside Macintosh manual for information regarding the installation of interrupt service routines.
Register-Level Programming Chapter 4 Mode 0–Basic I/O This mode is for simple I/O operations for each of the ports. No handshaking is required; data is simply written to or read from a specified port. Mode 0 has the following features: • Two 8-bit ports (A and B) and two 4-bit ports (upper and lower nibble of port C). • Any port can be input or output. • Outputs are latched, but inputs are not latched. Mode 1–Strobed I/O This mode is used for transferring data with handshake signals.
Chapter 4 Register-Level Programming Register Descriptions and Programming Examples The following figures show the two control-word formats used to completely program the 82C55A. The control-word flag determines which control-word format is being programmed. When the control-word flag is 1, bits 0 through 6 specify the I/O characteristics of the 82C55A’s ports and the mode in which they are operating (that is, mode 0, mode 1, or mode 2).
Register-Level Programming Chapter 4 This section describes the Digital Control Register, which is used to program the 82C55A ports in any one of the three modes discussed earlier in this section. Specific control words for each mode are described later in this section along with programming examples for each mode. Mode 0 Control Words Mode 0 provides simple I/O functions for each of the three ports with no handshaking. Each port can be assigned as an input port or as an output port.
Chapter 4 Register-Level Programming Example 2. Configure port A for input, port B and port C for output: • Write 90 (hex) to the Digital Control Register. • Write 8-bit data to port B or port C. Read 8-bit data from port A as appropriate. Example 3. Configure port A and port C for output, port B for input: • Write 82 (hex) to the Digital Control Register. Example 4. Configure port A and port B for output, port C for input: • Write 89 (hex) to the Digital Control Register.
Register-Level Programming Chapter 4 Port C status-word bit definitions for input (port A and port B): 7 6 5 4 3 2 1 0 I/O I/O IBFA INTEA INTRA INTEB IBFB INTRB Bit Name Description 7, 6 I/O Extra I/O status lines when port A is in mode 1 input. 5 IBFA Input Buffer Full for Port A—High indicates that data has been loaded into the input latch for port A. 4 INTEA Interrupt Enable Bit for Port A—Enables interrupts from the 82C55A for port A.
Chapter 4 Register-Level Programming Mode 1 Input Programming Example Example 1. Configure port A as an input port in mode 1: • Write B0 (hex) to the Digital Control Register. • Wait for bit 5 of port C (IBFA) to be set, indicating that data has been latched into port A. • Read data from port A. Example 2. Configure port B as an input port in mode 1: • Write 86 (hex) to the Digital Control Register. • Wait for bit 1 of port C (IBFB) to be set, indicating that data has been latched into port A.
Register-Level Programming Chapter 4 Port C status-word bit definitions for output (port A and port B): 7 6 5 4 3 2 1 0 OBFA* INTEA I/O I/O INTRA INTEB* OBFB INTRB Bit Name Description 7 OBFA* Output Buffer Full for Port A—Low indicates that the CPU has written data out to port A. 6 INTEA Interrupt Enable Bit for Port A—If this bit is high, interrupts are enabled from the 82C55A for port A. Controlled by setting or resetting PC6.
Chapter 4 Register-Level Programming Mode 1 Output Programming Example Example 1. Configure port A as an output port in mode 1: • Write A0 (hex) to the Digital Control Register. • Wait for bit 7 of port C (OBFA*) to be cleared, indicating that the data last written to port A has been read. • Write new data to port A. Example 2. Configure port B as an output port in mode 1: • Write 84 (hex) to the Digital Control Register.
Register-Level Programming Chapter 4 Port C status-word bit definitions for bidirectional data path (port A only): 7 6 5 4 3 2 1 0 OBFA* INTE1 IBFA INTE2 INTRA I/O I/O I/O Bit Name Description 7 OBFA* Output Buffer Full—Low indicates that the CPU has written data out to port A. 6 INTE1 Interrupt Enable Bit for Output—If this bit is set, interrupts are enabled from the 82C55A for OBF*. Controlled by setting or resetting PC6.
Chapter 4 Register-Level Programming Mode 2 Programming Example Example 1. Configure port A in mode 2: • Write C0 (hex) to the Digital Control Register. • Wait for bit 7 of port C (OBFA*) to be cleared, indicating that the data last written to port A has been read. • Write new data to port A. • Wait for bit 5 of port C (IBFA) to be set, indicating that data is available in port A to be read. • Read data from port A.
Chapter 5 Calibration This chapter discusses the calibration procedures for the Lab-NB analog input and analog output circuitry. The Lab-NB is calibrated at the factory before shipment. To maintain the 12-bit accuracy of the Lab-NB analog input and analog output circuitry, recalibration at six-month intervals is recommended. Recalibration is also recommended whenever the input or output configuration is changed.
Calibration Chapter 5 Calibration Trimpots The Lab-NB has six trimpots for calibration. The location of these trimpots on the Lab-NB board is shown in the partial diagram of the board in Figure 5-1. 1 1 3 5 R6 R8 R10 2 4 6 2 3 4 5 R7 R9 R1 Figure 5-1.
Chapter 5 Calibration Analog Input Calibration To null out error sources that compromise the quality of measurements, you must calibrate the analog input circuitry by adjusting the following potential sources of error: • Offset errors • Gain error of the analog input circuitry The calibration must be performed if the input configuration is changed from bipolar (the factory setting) to unipolar.
Calibration Chapter 5 Input Range -5 to +5 V 0 to 10 V V-fs -5 V 0V V+fs - 1 1 LSB 0.5 LSB +4.99756 V +9.99756 V 2.44 mV 2.44 mV 1.22 mV 1.22 mV Board Configuration The calibration procedure differs if you select either bipolar or unipolar input configuration. A procedure for each configuration is given next. Bipolar Input Calibration Procedure If your board is configured for bipolar input, which provides the range -5 to +5 V, then complete the following procedure in the order given.
Chapter 5 Calibration b. Take analog input readings from channel 0 at a gain of 1, and adjust trimpot R10 until the ADC readings flicker evenly between 2,046 and 2,047. Alternatively, you can average a number of readings (approximately 100) and adjust trimpot R10 until the average reading is 2,046.5. Unipolar Input Calibration Procedure If your board is configured for unipolar input, which has an input range of 0 to +10 V, then complete the following steps in sequence.
Calibration Chapter 5 Offset error in the analog output circuitry is the total of the voltage offsets contributed by each component in the circuitry. This error appears as a voltage difference between the desired voltage and the actual output voltage generated and is independent of the D/A setting. To correct this offset gain error, set the D/A to negative full-scale and adjust a trimpot until the output voltage is the negative full-scale value ±0.5 LSB.
Chapter 5 Calibration c. Adjust trimpot R9 until the output voltage read is -5 V. 2. Adjust the Analog Output Gain Adjust the analog output gain by measuring the output voltage generated with the DAC set at positive full-scale (4,095). This output voltage should be V+fs ±0.5 LSB. For bipolar output, V+fs = +4.99756 V, and 0.5 LSB = 1.22 mV. For analog output channel 0: a. Connect the voltmeter between DAC0 OUT (pin 10 on the I/O connector) and AOGND (pin 11). b. Set the analog output channel to +4.
Calibration Chapter 5 For analog output channel 1: a. Connect the voltmeter between DAC1 OUT (pin 12 on the I/O connector) and AOGND (pin 11). b. Set the analog output channel to 0 V by writing 0 to the DAC. c. Adjust trimpot R9 until the output voltage read is 0 V. 2. Adjust the Analog Output Gain Adjust the analog output gain by measuring the output voltage generated with the DAC set at positive full-scale (4,095). This output voltage should be V+fs ±0.5 LSB. For unipolar output, V+fs = +9.
Appendix A Specifications This appendix lists the specifications of the Lab-NB. These specifications are typical at 25° C unless otherwise stated. The operating temperature range is 0° to 70° C. Analog Input Number of input channels........................................................8 single-ended Analog resolution........................................................................12 bits, one part in 4,096 Relative accuracy (nonlinearity) ...........................................±1.
Specifications Appendix A normally called nonlinearity, because relative accuracy ensures that the sum of quantization uncertainty and A/D conversion error does not exceed a given amount. Integral nonlinearity in an ADC is an often ill-defined specification that is supposed to indicate a converter's overall A/D transfer linearity.
Appendix A Specifications Voltage offset ......................................................................±60 µV/° C Explanation of Analog Output Specifications Relative accuracy in a D/A system is the same as nonlinearity, because no uncertainty is added due to code width. Unlike an ADC, every digital code in a D/A system represents a specific analog value rather than a range of values.
Specifications Appendix A Physical Board dimensions........................................................................27.62 by 10.16 cm (10.875 by 4.0 in.) I/O connector................................................................................50-pin D male ribbon-cable connector Environment Operating temperature...............................................................0° to 70° C Storage temperature ...................................................................
Appendix B I/O Connector This appendix contains the pinout and signal names for the I/O connector on the Lab-NB. Figure B-1 shows the Lab-NB 50-pin I/O connector.
Appendix C AMD 8253 Data Sheet* This appendix contains the manufacturer data sheet for the AMD 8253 System Timing Controller integrated circuit (Advanced Micro Devices, Inc.). This circuit is used on the LabNB. * Copyright © Advanced Micro Devices, Inc. 1987. Reprinted with permission of copyright owner. All rights reserved. Advanced Micro Devices, Inc. 1987 Data Book MOS Microprocessors and Peripherals.
Appendix D OKI 82C55A Data Sheet* This appendix contains the manufacturer data sheet for the OKI 82C55A (OKI Semiconductor) CMOS programmable peripheral interface . This interface is used on the Lab-NB. * Copyright © OKI Semiconductor. 1993. Reprinted with permission of copyright owner. All rights reserved. OKI Semiconductor Data Book Microprocessor, Seventh Edition, March 1993.
OKI 82C55A Data Sheet Lab-NB User Manual Appendix D D-2 © National Instruments Corporation
Appendix D © National Instruments Corporation OKI 82C55A Data Sheet D-3 Lab-NB User Manual
OKI 82C55A Data Sheet Lab-NB User Manual Appendix D D-4 © National Instruments Corporation
Appendix D © National Instruments Corporation OKI 82C55A Data Sheet D-5 Lab-NB User Manual
OKI 82C55A Data Sheet Lab-NB User Manual Appendix D D-6 © National Instruments Corporation
Appendix D © National Instruments Corporation OKI 82C55A Data Sheet D-7 Lab-NB User Manual
OKI 82C55A Data Sheet Lab-NB User Manual Appendix D D-8 © National Instruments Corporation
Appendix D © National Instruments Corporation OKI 82C55A Data Sheet D-9 Lab-NB User Manual
OKI 82C55A Data Sheet Lab-NB User Manual Appendix D D-10 © National Instruments Corporation
Appendix D © National Instruments Corporation OKI 82C55A Data Sheet D-11 Lab-NB User Manual
OKI 82C55A Data Sheet Lab-NB User Manual Appendix D D-12 © National Instruments Corporation
Appendix D © National Instruments Corporation OKI 82C55A Data Sheet D-13 Lab-NB User Manual
OKI 82C55A Data Sheet Lab-NB User Manual Appendix D D-14 © National Instruments Corporation
Appendix D © National Instruments Corporation OKI 82C55A Data Sheet D-15 Lab-NB User Manual
OKI 82C55A Data Sheet Lab-NB User Manual Appendix D D-16 © National Instruments Corporation
Appendix D © National Instruments Corporation OKI 82C55A Data Sheet D-17 Lab-NB User Manual
Appendix E Customer Communication ___________________________________________________ For your convenience, this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation. Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster. National Instruments provides comprehensive technical assistance around the world.
Technical Support Form ___________________________________________________ Photocopy this form and update it each time you make changes to your software or hardware, and use the completed copy of this form as a reference for your current configuration. Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently.
Lab-NB Hardware and Software Configuration Form ___________________________________________________ Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a new copy of this form each time you revise your software or hardware configuration, and use this form as a reference for your current configuration.
Documentation Comment Form ___________________________________________________ National Instruments encourages you to comment on the documentation supplied with our products. This information helps us provide quality products to meet your needs. Title: Lab-NB User Manual Edition Date: September 1995 Part Number: 320174B-01 Please comment on the completeness, clarity, and organization of the manual. If you find errors in the manual, please record the page numbers and describe the errors.
Glossary ___________________________________________________ ° Ω % A A/D ADC AMD ANSI AWG BCD C CMOS D/A DAC DAQ dB DC DMA DOS EPROM F FIFO ft hex Hz IIH IIL in.
Glossary ksamples LED LS LSB MB m MSB PA PB PC PC PPI ppm REXT rms RTSI SCXI s TTL V VEXT VIH VIL VIN VI Lab-NB User Manual 1,000 samples light-emitting diode Low-power Schottky least significant bit megabytes of memory meters most significant bit port A port B port C personal computer programmable peripheral interface parts per million external resistance root mean square Real-Time System Integration System Conditioning eXtensions for Instrumentation seconds transistor-transistor logic volts external vo
Index Numbers/Symbols Counter A1 Data Register description, 4-18 programming controlled acquisition mode, 4-41, 4-47 to 4-48 freerun acquisition mode, 4-44, 4-50 Counter A2 Data Register description, 4-19 interrupt programming of analog output circuitry, 4-54 Counter B Mode Register, 4-24 Counter B0 Data Register description, 4-21 programming controlled acquisition mode, 4-40 freerun acquisition mode, 4-43 to 4-44 Counter B1 Data Register, 4-22 Counter B2 Data Register, 4-23 counter block diagram, 3-11 ove
Index analog input circuitry block diagram, 3-3 programming, 4-36 to 4-38 A/D FIFO output binary modes, 4-38 bipolar input mode (two's complement coding) (table), 4-38 unipolar input mode (straight binary coding) (table), 4-38 clearing, 4-39 initiating A/D conversion, 4-37 interrupt programming, 4-52 programming sequence, 4-36 to 4-38 reading A/D conversion result, 4-37 to 4-38 selecting analog input channel and gain, 4-37 theory of operation, 3-4 Analog Input Register group, 4-5 to 4-12 A/D Clear Register
Index analog output voltage versus digital code bipolar mode, two’s complement coding (table), 4-54 calculating for bipolar analog output, 4-53 for unipolar analog output, 4-53 unipolar mode, straight binary coding (table), 4-53 analog-to-digital converter (ADC), 3-4 AOGND signal (table), 2-7 analog input signal connections, 2-7 to 2-8 connections for signal sources (figure), 2-8 exceeding input signal range (warning), 2-8 analog input specifications, A-1 to A-2 analog output calibration, 5-5 to 5-8 bipol
Index bipolar input calibration procedure, 5-4 to 5-5 gain calibration, 5-4 to 5-5 offset calibration, 5-4 board configuration, 5-4 unipolar input calibration procedure gain calibration, 5-5 offset calibration, 5-5 analog output, 5-5 to 5-8 bipolar output calibration procedure, 5-6 to 5-7 adjusting analog output gain, 5-6 adjusting analog output offset, 5-6 board configuration, 5-6 unipolar output calibration procedure adjusting analog output gain, 5-8 adjusting analog output offset, 5-7 to 5-8 equipment r
Index Counter A0 Data Register description, 4-17 programming controlled acquisition mode, 4-40 to 4-42, 4-47 freerun acquisition mode, 4-43 to 4-44, 4-49 Counter A1 Data Register description, 4-18 programming controlled acquisition mode, 4-41, 4-47 to 4-48 freerun acquisition mode, 4-44, 4-50 Counter A2 Data Register description, 4-19 interrupt programming of analog output circuitry, 4-54 Counter B Mode Register, 4-24 Counter B0 Data Register description, 4-21 programming controlled acquisition mode, 4-40
Index pretrigger DAQ timing (figure), 2-19 waveform generation timing with EXTUPDATE* signal (figure), 2-20 data acquisition. See controlled acquisition mode; DAQ entries; freerun acquisition mode.
Index programming example, 4-63 mode 2 bidirectional bus control words, 4-63 Port C pin assignments (figure), 4-64 Port C status-word bit definitions, 4-64 programming example, 4-65 register descriptions and programming examples, 4-57 to 4-65 single bit set/reset control words, 4-65 digital I/O signal connections, 2-10 to 2-16 digital input specifications, 2-10 digital output specifications, 2-10 mode 1 input timing, 2-14 mode 1 output timing, 2-15 mode 2 bidirectional timing, 2-16 Port C pin connections,
Index programming analog output circuitry, 4-52 specifications and ratings, 2-20 to 2-21 waveform generation timing (figure), 2-20 frequency measurement, 2-22 application (figure), 2-23 GATE, CLK, and OUT signals, 2-21 to 2-24 requirements for (figure), 2-24 pulse and square wave generation, 2-21 pulse-width measurement, 2-22 specifications and ratings for 8253 I/O signals, 2-23 time-lapse measurement, 2-22 getting started with Lab-NB, 1-2 F fax technical support, E-1 freerun acquisition mode counter A0
Index programming examples, 4-58 to 4-59 mode 0 basic I/O, 82C55A integrated circuit, 4-56 mode 1 bidirectional bus, 82C55A integrated circuit, 4-56 mode 1 input timing, digital I/O, 2-14 mode 1 output timing, digital I/O, 2-15 mode 1 strobed input control words, 4-59 to 4-60 Port C pin assignments (figure), 4-60 Port C status-word bit definitions, 4-60 programming examples, 4-61 mode 1 strobed I/O, 82C55A integrated circuit, 4-56 mode 1 strobed output control words, 4-61 Port C pin assignments (figure), 4
Index parts locator diagram, 2-2 PB<0..7> signal (table), 2-7 PBINTEN bit, 4-31 *PBINTEN bit, 4-33 PC<0..
Index interrupt programming, 4-54 to 4-55 digital I/O circuitry, 4-55 to 4-65 82C55A modes of operation, 4-55 to 4-56 mode 0 basic I/O, 4-56 mode 1 bidirectional bus, 4-56 mode 1 strobed I/O, 4-56 single bit set/reset feature, 4-56 control-word format with control-word flag set to 0 (figure), 4-57 with control-word flag set to 1 (figure), 4-57 interrupt programming, 4-65 mode 0 control words (table), 4-58 programming examples, 4-58 to 4-59 mode 1 strobed input control words, 4-59 to 4-60 Port C pin assignm
Index programming. See digital I/O circuitry, programming.
Index freerun acquisition mode, 4-44 sample-interval timer, 3-5 and timebase source for counter A0, 4-40, 4-43 SCANEN bit DAQ operations on single input channel, 4-40 description, 4-7 multiple A/D conversions with channel scanning, 4-51 to 4-52 selecting posttrigger mode, 4-47 selecting pretrigger mode, 4-49 scanned (multichannel) data acquisition, 3-5 signal connections, 2-5 to 2-24 analog input signal connections, 2-7 to 2-8 analog output signal connections, 2-9 descriptions (table), 2-7 digital I/O si
Index block diagram, 3-8 EXTCONV* low, 2-18 DAQ circuitry, 3-4 to 3-7 analog input settling time versus gain (figure), 3-6 bipolar analog input signal range versus gain (figure), 3-7 block diagram, 3-3 DAQ rates, 3-6 to 3-7 description, 3-4 to 3-5 Lab-NB maximum recommended DAQ rates (figure), 3-6 multichannel (scanned) data acquisition, 3-5 single-channel data acquisition, 3-5 unipolar analog input signal range versus gain (figure), 3-7 digital I/O circuitry, 3-9 to 3-10 block diagram, 3-9 functional ov
Index general-purpose timing signal connections, 2-21 to 2-24 event-counting application with external switch gating (figure), 2-22 frequency measurement application (figure), 2-23 requirements for GATE and CLK and OUT signals (figure), 2-24 timing I/O circuitry, 3-10 to 3-11 block diagram, 3-10 counter block diagram, 3-11 timing I/O specifications, A-3 timing specifications, digital I/O signal connections, 2-12 to 2-13 mode 1 input timing, 2-14 mode 1 output timing, 2-15 mode 2 bidirectional timing, 2-16
