Date: 20.07.2020 Page 1 of 34 User Manual Indy 2k UHF Reader For Muehlbauer RFID production machines Version 1.
Date: 20.07.2020 Page 2 of 34 Index Safety instructions ................................................................................................................................... 4 1 System Overview .............................................................................................................................. 5 1.1 2 How is the reader hardware used ....................................................................................................... 5 Reader Firmware .........
Date: 20.07.2020 5.3 5.3.1 5.3.2 5.3.3 Page 3 of 34 Sampes for memory bank access with EPC1 Gen 2 Chips............................................................. 24 EPC Memory Bank ........................................................................................................................................ 25 USER Memory Bank ..................................................................................................................................... 25 Reserved Memory Bank ..........
Date: 20.07.2020 Page 4 of 34 Safety instructions FCC: This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interferences, and (2) this device must accept any interference received, including interference that may cause undesired operation. Note: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
Date: 20.07.2020 1 Page 5 of 34 System Overview The process department of Muehlbauer develop a new UHF reader hardware together with Impinj Inc. USA. Basic component of this system are the Impinj IPJ-E3004 reader board from Indy@R2000 development platform. This reader board provide all features of INDY 2000 reader chip family and support all UHF reader features of standard EPC1 Gen2 V 1.2.
Date: 20.07.2020 Page 6 of 34 The configuration of reader hardware are depend from country regulations and we limit the used frequency range in production process to the country related frequency bands. The frequency band are depend from telecommunication rules at customer side where the machine is located. The setup of the reader hardware works in production with low power levels (normally ca. 5 - 15dBm) and we shield the radiated power with metal plates and antennas in metal boxes.
Date: 20.07.2020 2.2 Page 7 of 34 Software Tools 2.2.1 Indy Tool (Development Tool) For the communication with Indy reader hardware exist from Impinj side and development tool with name “Indy Tool”. The current version is 2.6.0 but the new version 2.7.0 for new MAC firmware 2.7.0 is available. Differences between both tools are, the new version 2.7.0 can handle additionally new EPC1 Gen2 functions like “Untraceable” and “Authenticate”.
Date: 20.07.2020 Page 8 of 34 24V DC Mini-USB socket 3.2 serial UART 9-pin (female) Mini-USB interface The Indy 2k UHF reader provides a USB HOST interface with Mini-USB socket. This interface is not active in default setup. The reader can power up via USB but before you must set two jumpers at reader board from Main power to USB power. 3.3 Reset input The reader hardware have since revision 2.0 and optoisulated reset input for hardware resets. 24 volts at input start a reset when signal are min.
Date: 20.07.2020 3.5 Page 9 of 34 GPIO TTL Interface The TTL GPIO interface provide four lines and can independent configure as Input or Output by jumper at interface board. Voltage level for Inputs are max. 3.3 volts and is not 5V tolerant! The TTL input lines goes directly to the ARM 7 controller of the reader board. When you use the GPIO as output, then is a Inverter as driver between and you get a inverted logic at TTL output.
Date: 20.07.2020 4 Page 10 of 34 Command dialog between Host <==> Reader Between Indy 2k reader and HOST system exist an intensive dialog with register and packet structures. The HOST-PC send commands to store the data values into MAC register of the reader. When the HOST will start a command, then this command code must store in execute MAC register F0 00h. The reader respond then with Start- and Stop packages, show the error status, time stamps and measured values.
Date: 20.07.2020 4.2 Page 11 of 34 Reader commands for INDY R2k Readers The command structure are descripted in follow documents “MAC register documentation” and in “HOST packet definitions” from Impinj. The reader respond only at executable commands. MAC register Write cycles create no response! The reason for that are, this reduce the traffic at UART interface. The Error status can checked with Read cycle at follow MAC addresses: 00 05h (Current Error Status) 00 06h (Last existing MAC Error).
Date: 20.07.2020 4.4 4.4.1 Page 12 of 34 Register Struktur MAC Firmware General Block (address range 0x00) In this address range are stored the Firmware version data, Hardware data and Serial numbers of the reader hardware. These registers have Read only status and can’t overwrite. 4.4.2 Test Block (address range 0x01) This range are used for hardware values of test functions.
Date: 20.07.2020 Page 13 of 34 This range define the function of four GPIO lines. The GPIO ports can configure as Input or Output. But signals at GPIO inputs can’t start special test commands. The firmware do not provide that. GPIO lines can used to control multiplexers or other external hardware over the HOST interface. 4.4.8 Antenna Block (address range 0x07) This MAC register range are used for config parameters of antenna ports and multiplexer modes.
Date: 20.07.2020 Page 14 of 34 4.4.13 Frequency Block (address range 0x0C) This range are not used for setup reader frequencies, it’s for parameters of PLL systems, synthesizers, frequency divider factors and BIAS parameter for power amplifier. In this area are no modification required. 4.4.14 Reserved Customer Block (address range 0x0F) This address range are free and reserved for custom programs. We do not use it at moment. 4.4.
Date: 20.07.2020 5 Page 15 of 34 Configuration of INDY R2k Reader The reader setup have a lot of parameters and it is not easy to handle that without software assistance. We use for that our „MB Reader Tool“ and built macros with command sequences to make it easier and transparent for operators. This tool monitor a copy of the command dialog and analyse data for operator. In the next chapters below exist examples for hardware dialog with comments.
Date: 20.07.2020 ; Ant. port 0 set, 100ms antenna slot active, count off 01 00 00 07 01 00 00 00 01 00 01 07 00 00 00 00 01 00 02 07 01 00 00 00 01 00 04 07 00 00 00 00 01 00 05 07 64 00 00 00 01 00 07 07 00 00 00 00 ;Setup Inventory, EPC, Stop after 1.
Date: 20.07.2020 Page 17 of 34 [COM2] ; RF_power_off !!! 01 00 00 F0 18 00 00 00 ; set test power 15,0dBm 01 00 14 01 96 00 00 00 01 00 06 07 96 00 00 00 00 00 05 00 00 00 00 00 ; Working frequency set to 907,3MHz = 907300 = 0DD824 01 00 0A 01 24 D8 0D 00 01 00 08 01 01 01 00 00 01 00 00 F0 27 00 00 0 5.2 Command-Dialog between Maschine <==> Indy Reader: Connect request, (only for USB connection required!) ---------------------------------------------02:40:02.
Date: 20.07.2020 RF power 15,0dBm (Test port + Tag Access) ---------------------------------------------02:40:41.912 HostPC >> 01 00 00 F0 18 00 00 00 02:40:41.912 HostPC >> 01 00 14 01 96 00 00 00 02:40:41.912 HostPC >> 01 00 06 07 96 00 00 00 02:40:41.912 HostPC >> 00 00 05 00 00 00 00 00 - - - - - - - - - - - - - - - 02:40:42.271 Reader << 01 00 00 00 02 00 00 00 02:40:42.271 Reader << 18 00 00 00 40 79 41 00 02:40:42.271 Reader << 01 00 01 00 02 00 00 00 02:40:42.
Date: 20.07.2020 Tag Access Setup: Read EPC 96Bit ---------------------------------------------02:42:36.714 HostPC >> 01 00 01 0A 06 00 00 00 02:42:36.714 HostPC >> 01 00 02 0A 01 00 00 00 02:42:36.714 HostPC >> 01 00 03 0A 02 00 00 00 02:42:36.714 HostPC >> 01 00 04 0A 06 00 00 00 02:42:36.714 HostPC >> 01 00 05 0A 00 00 00 00 02:42:36.714 HostPC >> 01 00 06 0A 00 00 00 00 02:42:36.714 HostPC >> 01 00 07 0A 00 00 00 00 02:42:36.714 HostPC >> 01 00 08 0A 00 00 00 00 02:42:36.
Date: 20.07.2020 Write Setup EPC 96 Bit ---------------------------------------------02:44:00.476 HostPC >> 01 00 05 07 64 00 00 00 02:44:00.476 HostPC >> 01 00 01 09 01 00 00 00 02:44:00.476 HostPC >> 01 00 11 09 00 00 00 00 02:44:00.476 HostPC >> 01 00 01 0A 06 00 00 00 02:44:00.476 HostPC >> 01 00 02 0A 01 00 00 00 02:44:00.476 HostPC >> 01 00 03 0A 02 00 00 00 02:44:00.476 HostPC >> 01 00 04 0A 06 00 00 00 02:44:00.476 HostPC >> 01 00 06 0A 00 00 00 00 02:44:00.
Date: 20.07.2020 Setup Tag Acces Read EPC 96 Bit ---------------------------------------------02:46:41.469 HostPC >> 01 00 01 0A 06 00 00 00 02:46:41.469 HostPC >> 01 00 02 0A 01 00 00 00 02:46:41.469 HostPC >> 01 00 03 0A 02 00 00 00 02:46:41.469 HostPC >> 01 00 04 0A 06 00 00 00 02:46:41.469 HostPC >> 01 00 05 0A 00 00 00 00 02:46:41.469 HostPC >> 01 00 06 0A 00 00 00 00 02:46:41.469 HostPC >> 01 00 07 0A 00 00 00 00 02:46:41.469 HostPC >> 01 00 08 0A 00 00 00 00 02:46:41.
Date: 20.07.2020 Page 22 of 34 Write “Kill Code”: AB CD EF 01 in Reserd Memory Bank, no block write! ---------------------------------------------02:16:07.484 HostPC >> 01 00 02 0A 00 00 00 00 ; memory bank 00 ==> Resered bank 02:16:07.484 HostPC >> 01 00 03 0A 00 00 00 00 ; offset counter 00, memory map: Kill data 02:16:07.484 HostPC >> 01 00 04 0A 02 00 00 00 ; Block counter 02 02:16:07.484 HostPC >> 01 00 08 0A 00 00 00 00 ; Config Tag Write dat register, max. 128 bits 02:16:07.
Date: 20.07.2020 Read “Kill Code” from Reserved Bank ---------------------------------------------02:17:08.470 HostPC >> 01 00 02 0A 00 00 00 00 02:17:08.470 HostPC >> 01 00 03 0A 00 00 00 00 02:17:08.470 HostPC >> 01 00 04 0A 02 00 00 00 02:17:08.470 HostPC >> 01 00 00 F0 10 00 00 00 - - - - - - - - - - - - - - - 02:17:09.298 Reader << 01 00 00 00 02 00 00 00 02:17:09.298 Reader << 10 00 00 00 61 0B 12 00 02:17:09.298 Reader << 01 02 05 00 07 00 00 00 02:17:09.
Date: 20.07.2020 With Blockwrite Write new EPC data into Reader 96Bit, with Blockwrite! Write command (Tag Access Write 96Bit, with Blockwrite) Write Access Code: 87 65 43 21 to Reserd Memory Bank, with Blockwrite! Write Kill Code: AB CD EF 01 in Reserd Memory Bank, with Blockwrite Write PC Parameter in EPC Speicherbank PC = 30 00 = 96Bit PC = 40 00 = 128Bit 5.
Date: 20.07.2020 5.3.1 EPC Memory Bank ==> Setup EPC 96Bit 11:45:18.539 > von Maschine: 01 00 01 09 40 00 00 00 11:45:18.539 > von Maschine: 01 00 11 09 00 00 00 00 11:45:18.555 > von Maschine: 01 00 01 0A 06 00 00 00 11:45:18.555 > von Maschine: 01 00 02 0A 01 00 00 00 11:45:18.555 > von Maschine: 01 00 03 0A 02 00 00 00 11:45:18.555 > von Maschine: 01 00 04 0A 06 00 00 00 11:45:18.555 > von Maschine: 01 00 06 0A 00 00 00 00 11:45:18.555 > von Maschine: 01 00 07 0A 00 00 00 00 11:45:18.
Date: 20.07.2020 ==> Send User Memory Data for Reader (kein Blockwrite) 11:45:47.165 > von Maschine: 01 00 09 0A BB AA 00 00 11:45:47.165 > von Maschine: 01 00 0A 0A DD CC 01 00 11:45:47.165 > von Maschine: 01 00 0B 0A FF EE 02 00 11:45:47.165 > von Maschine: 00 00 05 00 00 00 00 00 11:45:47.165 < von Reader: 00 00 05 00 00 00 00 00 ==> Write USER Data into Memory 11:45:47.993 > von Maschine: 01 00 00 F0 11 00 00 00 11:45:47.993 < von Reader: 01 00 00 00 02 00 00 00 11:45:47.
Date: 20.07.2020 Page 27 of 34 Set Access Passwort in MAC Register for Reader <=> Chip Communication 11:46:09.275 > von Maschine: 01 00 06 0A 21 43 65 87 ; Access Code PWD 87 65 43 21 11:46:09.275 > von Maschine: 00 00 05 00 00 00 00 00 11:46:09.
Date: 20.07.2020 5.4 Page 28 of 34 Samples for Lock Functions with EPC 1 Gen2 Chips Before you can Lock a Tag, the MAC register 0A 08h (Tag Write Selector) must set to value 00 00 00 00h. We do this as default with Init sequence for the reader. If the register not set to zero, you can get Error codes when you start Lock functions, e.g. error code 00 09 11:46:06.
Date: 20.07.2020 Page 29 of 34 ==> Lock Comand, the type a Write protection and memeory banks will defined by Lock Mask 11:46:12.665 > von Maschine: 01 00 00 F0 12 00 00 00 11:46:12.665 < von Reader: 01 00 00 00 02 00 00 00 11:46:12.665 < von Reader: 12 00 00 00 50 12 62 00 11:46:12.665 < von Reader: 01 12 05 00 07 00 00 00 11:46:12.665 < von Reader: 64 12 62 00 5E 7F 04 01 11:46:12.665 < von Reader: 7B FE 5D 3F 34 00 11 11 11:46:12.665 < von Reader: 11 11 11 11 11 11 11 11 11:46:12.
Date: 20.07.2020 Page 30 of 34 5.5 Example Command sequence TID Read, EPC Write, Access Code Write, Lock for EPC and Access Code 1. Setup TID 96 Bit HostPC >> 01 00 02 0A 02 00 00 00 HostPC >> 01 00 03 0A 00 00 00 00 HostPC >> 01 00 04 0A 06 00 00 00 HostPC >> 01 00 00 F0 10 00 00 00 ; memory bank 2 = TID ; offset counter 0 blocks ; word counter 6 blocks = 96 Bit ; start Read comand 2.
Date: 20.07.2020 5.6 Page 31 of 34 Example, how modify a Secure locked EPC bank with new data If a memory bank Secure locked, you can modify the memory bank only when you use the Access password for that. The access password is stored in chip Reserved memory bank area. Lock cycles before activate it as Write protection password and now is the bank locked.
Date: 20.07.2020 Page 32 of 34 Important packet types for our machines: 0000 Start Packet 0001 End Packet 0004 Inventory beginn 0005 Inventory Packet (PC-Value, EPC, Time stamp, RSSI) 0006 Tag Access Packet (with Chip Data, Chip Error Codes, Test Error Codes) 0009 Inventory end 7 Error Codes 7.
Date: 20.07.2020 7.2 TAG Error Codes (Packet type 0006) Tag Access functions respond with packet type 6. Byte no. 12 proive a command code for the test running test function Chip Error (Backscatter Error) responce are in byte 13.
Date: 20.07.2020 Test Errors monitor the MAC firmware in byte 14 and 15.
