MVME1X7P Single-Board Computer Programmer’s Reference Guide V1X7PA/PG1 Edition of October 2000
© Copyright 2000 Motorola, Inc. All rights reserved. Printed in the United States of America. Motorola® and the Motorola logo are registered trademarks of Motorola, Inc. MC68040™ and MC68060™ are trademarks of Motorola, Inc. All other products mentioned in this document are trademarks or registered trademarks of their respective holders.
Safety Summary The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware.
Flammability All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. EMI Caution ! Caution This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection. Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry.
CE Notice (European Community) Motorola Computer Group products with the CE marking comply with the EMC Directive (89/336/EEC). Compliance with this directive implies conformity to the following European Norms: EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment”; this product tested to Equipment Class B EN50082-1:1997 “Electromagnetic Compatibility—Generic Immunity Standard, Part 1.
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Contents About This Manual Overview of Contents ...............................................................................................xxii Comments and Suggestions ......................................................................................xxii Conventions Used in This Manual...........................................................................xxiii CHAPTER 1 Programming Issues Introduction.............................................................................................
Functional Description ............................................................................................ 1-17 VMEbus Interface and VMEchip2................................................................... 1-18 VMEchip2 General-Purpose I/O............................................................... 1-18 Petra/VMEchip2 Redundant Logic ........................................................... 1-18 Memory Maps.....................................................................................
LAN Offboard Error .........................................................................................1-61 LAN LTO Error ................................................................................................1-62 SCSI Parity Error ..............................................................................................1-62 SCSI Offboard Error .........................................................................................1-62 SCSI LTO Error ......................................
VMEbus Slave Address Modifier Select Register 1 ................................. 2-36 Programming the Local-Bus-to-VMEbus Map Decoders................................ 2-37 Local Bus Slave (VMEbus Master) Ending Address Register 1 .............. 2-39 Local Bus Slave (VMEbus Master) Starting Address Register 1 ............. 2-40 Local Bus Slave (VMEbus Master) Ending Address Register 2 .............. 2-40 Local Bus Slave (VMEbus Master) Starting Address Register 2 .............
VME Access, Local Bus, and Watchdog Time-out Control Register ......2-66 Prescaler Control Register ........................................................................2-67 Tick Timer 1 Compare Register ...............................................................2-68 Tick Timer 1 Counter ...............................................................................2-68 Tick Timer 2 Compare Register ...............................................................2-69 Tick Timer 2 Counter .............
I/O Control Register 2 .............................................................................. 2-97 I/O Control Register 3 .............................................................................. 2-97 Miscellaneous Control Register ............................................................... 2-98 GCSR Programming Model .................................................................................. 2-100 Programming the GCSR..................................................................
Programming the Tick Timers ..........................................................................3-18 Tick Timer 1 Compare Register ................................................................3-18 Tick Timer 1 Counter ................................................................................3-19 Tick Timer 2 Compare Register ................................................................3-19 Tick Timer 2 Counter ................................................................................
CHAPTER 4 MCECC Functions Introduction ............................................................................................................... 4-1 Features...................................................................................................................... 4 -2 Functional Description .............................................................................................. 4-3 General Description..................................................................................
Scrub Prescaler Counter (Bits 7-0) ...................................................................4-24 Scrub Timer Counter (Bits 15-8) ......................................................................4-24 Scrub Timer Counter (Bits 7-0) ........................................................................4-25 Scrub Address Counter (Bits 26-24).................................................................4-25 Scrub Address Counter (Bits 23-16)....................................................
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List of Figures Figure 1-1. MVME167P Block Diagram...................................................................1-5 Figure 1-2. MVME177P Block Diagram...................................................................1-6 Figure 1-3. MVME177 Flash and EPROM Memory Mapping Schemes................1-10 Figure 2-1. VMEchip2 Block Diagram .....................................................................2-5 Figure 3-1. PCCchip2 Block Diagram.................................................................
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List of Tables Table 1-1. MVME1X7P Features Summary ..............................................................1-3 Table 1-2. Functions Duplicated in VMEchip2 and Petra ASICs............................1-19 Table 1-3. Local Bus Memory Map .........................................................................1-21 Table 1-4. Local I/O Devices Memory Map ............................................................1-22 Table 1-5. VMEchip2 Memory Map (Sheet 1 of 3)..........................................
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About This Manual This manual provides board-level information and detailed ASIC information, including register bit descriptions, for the MVME167PAxxSE and MVME177PA-xxSE series of VME single-board computers, known collectively as the ‘‘MVME1X7P’’.
Overview of Contents Chapter 1, Programming Issues, describes the board-level hardware features of MVME1X7P single-board computers. It includes memory maps and a discussion of some general software considerations such as cache coherency, interrupts, and bus errors. Chapter 2, VMEchip2, describes the VMEchip2 ASIC, the local bus/VMEbus interface chip on MVME1X7P boards. Chapter 3, PCCchip2, describes the PCCchip2 ASIC.
You can also submit comments to the following e-mail address: reader-comments@mcg.mot.com In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.
bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files. italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms. courier is used for system output (for example, screen displays, reports), examples, and system prompts.
The terms control bit, status bit, true, and false are used extensively in this document. The term control bit is used to describe a bit in a register that can be set and cleared under software control. The term true is used to indicate that a bit is in the state that enables the function it controls. The term false is used to indicate that the bit is in the state that disables the function it controls.
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1Programming Issues 1 Introduction The MVME167P and MVME177P single-board computers are complex boards that interface both to the VMEbus and the SCSI bus. From a programming standpoint, their multiple-bus interfaces raise issues of cache coherency and support of indivisible cycles. There are also various potential sources of bus error. This chapter discusses those topics in addition to interrupt handling, the use of bus timers, and the programming interface to each device on the board.
1 Programming Issues The Petra ASIC is functionally compatible with each of the components that it replaces. In cases where functionality between ASICs is exclusive, configuration switches or jumpers are provided to let you select the desired functionality. In several areas of functionality, the configuration switches provide backward compatibility with earlier MVME167/177 implementations, but you can override their settings in software if you wish.
Introduction Features The “Petra” ASIC supplants the MCECC memory controller ASIC on MVME1X7P boards, performing the memory control functions previously carried out by the MCECC chip: It supplies the programmable interface for the ECC-protected 16/32/64/128MB DRAM emulation. The following table summarizes the features of the MVME167P and MVME177P single-board computers. Table 1-1.
1 Programming Issues Table 1-1.
P1 EPROM 4 44-pin PLCC i82696CA Ethernet Controller 25/33MHZ MC68040 MPU 53C710 SCSI Compressor PETRA P2 CD2401 Quad Serial I/O Controller Centronics Compatible Parallel I/O Port M48T58 Battery Backed 8KB RAM/Clock PCCCHIP 2 Mezzanine Connectors Up to 128MB ECC DRAM 1-5 http://www.motorola.com/computer/literature VMEchip 2 VMEbus Interface 128KB SRAM Battery Option 16-64MB ECC SDRAM Memory Array 2816 0800 Figure 1-1.
Programming Issues 1 P1 EPROM 2 44-pin PLCC 4MB FLASH i82696CA Ethernet Controller 50/60MHZ MC68040 MPU 53C710 SCSI Compressor PETRA P2 CD2401 Quad Serial I/O Controller Centronics Compatible Parallel I/O Port M48T58 Battery Backed 8KB RAM/Clock PCCCHIP 2 Mezzanine Connectors Up to 128MB ECC DRAM Computer Group Literature Center Web Site 1-6 VMEchip 2 VMEbus Interface 128KB SRAM Battery Option 16-128MB ECC SDRAM Memory Array 2816 0800 Figure 1-2.
Programming Interfaces Programming Interfaces The following sections describe the programming interface to devices on the MVME167P and MVME177P single-board computers. Unless the section specifies a particular board type, the discussion applies to both models. MC680X0 MPU The MVME167P is based on the MC68040 microprocessor. The MVME177P is based on the MC68060 microprocessor.
1 Programming Issues As a general rule, any master can access any slave; not all combinations pass the common sense test, however. Refer to the device-specific sections of this manual and to the user’s guide for each device to determine its port size, data bus connection, and any restrictions that apply when accessing the device.
Programming Interfaces MVME177 The EEPROMs on the MVME177 share 2MB of memory with the first 2MB of Flash memory. The EEPROM can co-exist with 2MB of Flash, or you may wish to program all 4MB as Flash memory. The Flash and EEPROM configuration is jointly controlled by a configuration switch (S4) as described in Chapters 1 and 4 of MVME177P Single Board Computer Installation and Use, and by control bit GPIO2 in the VMEchip2 ASIC, as described in Chapter 2, VMEchip2.
1 Programming Issues MAP 1 MAP 2 (as shipped) MAP 3 FFBFFFFF FFBFFFFF FLASH MEMORY 4MB FLASH TOP 2MB FLASH BOTTOM 2MB 1MB EPROM DUPLICATED: READABLE NOT WRITABLE 1MB EPROM DUPLICATED: READABLE NOT WRITABLE FFA00000 FF900000 1MB EPROM (BUG) 1MB EPROM FF800000 FF800000 NO EPROM IN MAP 1534 9408 Figure 1-3.
Programming Interfaces The MVME177P implements primary and secondary backup sources. You can select from +5V standby power, the onboard battery, or both. The jumpers and configuration switches for the MVME167P and MVME177P are described in Chapter 1 of the Installation and Use manual for the respective boards. Onboard SDRAM MVME167P boards are built with 16MB-64MB synchronous DRAM (SDRAM). MVME177P boards are built with 16MB-128MB SDRAM.
1 Programming Issues Battery-Backed-Up RAM and Clock Although the M48T58-70 RAM and clock chip is an 8-bit device, the interface provided by the PCCchip2 supports 8-, 16-, and 32-bit accesses to the M48T58. No interrupts are generated by the clock. Refer to Chapter 3, PCCchip2 and to the M48T58 data sheet for detailed programming guidance and battery life information. VMEbus Interface The VMEbus interface is implemented with an ASIC called the VMEchip2.
Programming Interfaces Serial Port Interface The CD2401 serial controller chip (SCC) is used to implement the four serial ports. The serial ports support the standard baud rates (110 to 38.4K baud). The four serial ports differ in function because of the limited number of pins on the P2 I/O connector: ❏ Serial port 1 is a minimum-function asynchronous port. It uses RXD, CTS, TXD, and RTS. ❏ Serial ports 2 and 3 are full-function asynchronous ports. They use RXD, CTS, DCD, TXD, RTS, and DTR.
1 Programming Issues The CD2401 supports DMA operations to local memory. Because the CD2401 does not support a retry operation necessary to break VMEbus lockup conditions, the CD2401 DMA controllers should not be programmed to access the VMEbus. The hardware does not restrict the CD2401 to onboard DRAM. Parallel (Printer) Interface The PCCchip2 ASIC provides an 8-bit bidirectional parallel port. All eight bits of the port must be either inputs or outputs (no individual selection).
Programming Interfaces Ethernet Interface The MVME1X7P uses the Intel 82596CA LAN coprocessor to implement the Ethernet transceiver interface. The 82596CA accesses local RAM using DMA operations to perform its normal functions. Because the 82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus.
1 Programming Issues SCSI Interface The MVME167P and MVME177P single-board computers provide for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The SCSI interface is implemented using the NCR 53C710 SCSI I/O controller. Support functions for the 53C710 are provided by the PCCchip2 ASIC.
Functional Description Watchdog Timer The VMEchip2 ASIC supplies a watchdog timer function. When enabled, the watchdog timer must be reset by software within the programmed interval or it times out. The watchdog timer can be programmed to generate a SYSRESET∗ signal, a local reset signal, or a board fail signal if it times out. Refer to Chapter 2, VMEchip2 for detailed programming information.
1 Programming Issues VMEbus Interface and VMEchip2 The local-bus-to-VMEbus interface and the VMEbus-to-local-bus interface are provided by the VMEchip2 ASIC. The VMEchip2 can also provide the VMEbus system controller functions. Refer to the VMEchip2 description in Chapter 2 for detailed programming information.
Functional Description Table 1-2.
1 Programming Issues 8. 32-bit prescaler. The prescaler can also be accessed at $FFF40064 when the optional VMEbus is not enabled. Memory Maps There are two points of view for memory maps: 1. The mapping of all resources as viewed by local bus masters (local bus memory map) 2. The mapping of onboard resources as viewed by VMEbus masters (VMEbus memory map) The memory maps and I/O maps described in the following tables are correct for all local bus masters.
Memory Maps The onboard I/O space must be marked cache-inhibit and serialized in its page table. Table 1-4 on page 1-22 further defines the map for the local I/O devices on the MVME1X7P. Table 1-3.
1 Programming Issues ($00000000 - $003FFFFF). The VMEchip2 and DRAM map decoders are disabled by a local bus reset. On the MVME177P, the Flash/EPROM memory is mapped at $00000000 - $003FFFFF by hardware default through the VMEchip2. 2. This area is user-programmable. The suggested use is shown in the table. The DRAM decoder is programmed in the MCECC chip, and the local-to-VMEbus decoders are programmed in the VMEchip2. 3. Size is approximate. 4. Cache inhibit depends on devices in area mapped. 5.
Memory Maps Table 1-4. Local I/O Devices Memory Map (Continued) Address Range Devices Accessed Port Size Size Notes $FFF43100 - $FFF431FF Petra/MCECC #2 D8 256B 1 $FFF43200 - $FFF43FFF Petra/MCECCs (repeated) -- 3.5KB 1,7 $FFF44000 - $FFF44FFF Reserved -- 4KB 5 $FFF45000 - $FFF451FF CD2401 (Serial Comm. Cont.
1 Programming Issues Notes 1. For a complete description of the register bits, refer to the data sheet for the specific chip. For a more detailed memory map refer to the following detailed peripheral device memory maps. 2. On the MVME1X7P, this area does not return an acknowledge signal. If the local bus timer is enabled, the access times out and is terminated by a TEA signal. 3. Byte reads should be used to read the interrupt vector. These locations do not respond when an interrupt is not pending.
Memory Maps Detailed I/O Memory Maps Tables 1-5 through 1-14 give the detailed memory maps for: 7 VMEchip2 Table 1-5 PCCchip 2 Table 1-7 Printer Table 1-6 MCECC Internal Register Table 1-8 Cirrus Logic CD2401 Serial Port Table 1-9 82596CA Ethernet LAN chip Table 1-10 53C710 SCSI chip Table 1-11 M48T58 BBRAM, TOD Clock Table 1-12 BBRAM Configuration Area Table 1-13 TOD Clock Table 1-14 You can obtain manufacturers’ errata sheets for the various chips listed above by contacting your local
1 Programming Issues Table 1-5.
Memory Maps 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A24 1 BLK D64 1 BLK 1 PRGM 1 DATA 1 4 3 2 1 0 SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER 1 15 14 13 12 SNP 1 11 10 9 WP 1 SUP 1 USR 1 8 7 6 A32 1 5 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST D16 EN MAST WP EN IO2 EN IO2 WP EN 15
1 Programming Issues Table 1-5.
Memory Maps 15 14 13 VME ACCESS TIMER 12 11 LOCAL BUS TIMER 10 9 8 7 6 5 WD TIME OUT SELECT 4 3 2 1 0 CLR OVF 1 COC EN 1 TIC EN 1 PRESCALER CLOCK ADJUST COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER CLR OVF 2 OVERFLOW COUNTER 2 COC EN 2 TIC EN 2 OVERFLOW COUNTER 1 SCALER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SW7 IRQ SW6 IRQ SW5 IRQ SW4 IRQ SW3 IRQ SW2 IRQ SW1 IRQ SW0 IRQ SPARE VME IRQ7 VME IRQ6 VME IRQ5 VME IRQ4 VME IRQ3 VME IRQ2 VME IRQ1 EN I
1 Programming Issues Table 1-5.
Memory Maps Table 1-6.
1 Programming Issues Table 1-7.
Memory Maps D15 D8 DRO CPU 040 MSTR INT EN FAST BRAM CLR OVF 2 COC EN 2 TIC EN 2 D7 D0 VECTOR BASE REGISTER COMPARE REGISTER COUNTER REGISTER COMPARE REGISTER COUNTER REGISTER OVERFLOW COUNTER 2 TIC2 INT TIC2 IEN TIC2 ICLR TIC TIMER 2 IRQ LEVEL SCC TX IRQ SCC TX IEN SCC TX AVEC SCC TRANSMIT IRQ LEVEL CLR OVF 1 OVERFLOW COUNTER 1 SCC SC1 SCC SC0 COC EN 1 TIC EN 1 TIC1 INT TIC1 IEN TIC1 ICLR TIC TIMER 1 IRQ LEVEL SCC RX IRQ SCC RX IEN SCC RX AVEC SCC RECEIVE IRQ LEVEL SCC MO
1 Programming Issues Table 1-8.
Memory Maps Table 1-8.
1 Programming Issues Table 1-9.
Memory Maps Table 1-9.
1 Programming Issues Table 1-9.
Memory Maps Table 1-9.
1 Programming Issues Table 1-9. Cirrus Logic CD2401 Serial Port Memory Map (Continued) Base Address = $FFF45000 Register Description Register Name Offsets Size Access General Timer 1 low GT1l 2B B R Sync General Timer 1 high GT1h 2A B R Sync General Timer 2 GT2 29 B R Sync Transmit Timer Register TTR 29 B R Async Note This is a 16-bit register Table 1-10.
Memory Maps Table 1-11.
1 Programming Issues used by the MVME1X7P board debugger (MVME1X7Bug). The fifth area, detailed in Table 1-13, is the configuration area. The sixth area, the TOD clock, detailed in Table 1-14, is defined by the chip hardware. Table 1-12.
Memory Maps Table 1-13. BBRAM Configuration Area Memory Map Address Range Description Size (Bytes) $FFFC1F4E - $FFFC1F55 Mezz. Board 2 PWB 8 $FFFC1F56 - $FFFC1F5D Mezz. Board 2 Serial Number 8 $FFFC1F5E - $FFFC1FF6 Reserved 153 $FFFC1FF7 Checksum 1 Table 1-14.
1 Programming Issues struct brdi_cnfg { char char char char char char char char char char char char char char char } version[4]; serial[12]; id[16]; pwa[16]; speed[4]; ethernet_adr[6]; fill[2]; lscsiid[2]; sysid[8]; brd1_pwb[8]; brd1_serial[8]; brd2_pwb[8]; brd2_serial[8]; reserved[153]; cksum[1]; The fields are defined as follows: 1. Four bytes are reserved for the revision or version of this structure.
Memory Maps structure for that set. For example, for a 64MB, 33MHz MVME167P board at revision C, the PWA field contains: 01-W3620F35C (The 13 characters are followed by three blanks.) 5. Four bytes contain the speed of the board in MHz. The first two bytes are the whole number of MHz and the second two bytes are fractions of MHz. For example, for a 25.00 MHz board, this field contains: 2500 6. Six bytes are reserved for the Ethernet address. The address is stored in hexadecimal format.
1 Programming Issues 15. The final byte of the area is reserved for a checksum (as defined in the Debugging Package User’s Manual for MVME167Bug and MVME177Bug, and the Debugging Package for Motorola 68K CISC CPUs User’s Manual) for security and data integrity of the configuration area of the NVRAM. This data is stored in hexadecimal format. Interrupt Acknowledge Map The local bus distinguishes interrupt acknowledge cycles from other cycles by placing the binary value %11 on TT1-TT0.
Interrupt Handling Interrupt Handling M68000-based systems use hardware-vectored interrupts. Board MPUs from the M68000 family require that the C040 bit in the PCCchip2 General Control register (address $FFF42002) be set. For more information, refer to the General Control Register section in Chapter 3, PCCchip2. Most interrupt sources are level and base vector programmable.
1 Programming Issues 1. Set up Tick Timer: Step Register and Address Action and Reference 1 Prescaler Control register $FFF4004C If not already initialized by the debugger, initialize as follows: Prescaler register = 256–Bclock (MHz). This gives a 1 MHz clock to the tick timers. Bclock is the bus clock rate, such as 25MHz. 256–25 = $E7. 2 Tick Timer 1 Compare register $FFF40050 For periodic interrupts, set the Compare Register value = Period (s).
Cache Coherency (MVME167P) Periodic Tick Timer 1 interrupts now occur, so you need an interrupt handler. Section 3 gives the details, as follows. 3. Set up an interrupt handler routine: Step Action and Reference Your interrupt handler should include the following features. 1 Be sure the MC680x0 Vector Base register is set up. Set the proper MC680x0 exception vector location so the processor vectors to your interrupt handler location.
1 Programming Issues ensure that data shared by multiple processors is kept in un-cached memory. The software must also mark all onboard I/O areas as cache inhibited and serialized. Cache Coherency (MVME177P) The MVME177P’s MC68060 processor has the ability to watch the external bus during accesses by other bus masters, maintaining coherency between the MC68060’s caches and external memory systems.To maintain cache coherency, the MC68060 provides automatic snoopinvalidation when it is not the bus master.
Using Bus Timers Using Bus Timers This section illustrates the use of bus timers by describing the sequence of events when the MPU on one single-board computer accesses the Local Bus memory on another single-board computer using the VMEbus.
1 Programming Issues DS1 goes inactive). This time should be longer than any expected legitimate transfer time on the bus. We normally set it to 256 µsec. This timer can also be disabled for debug purposes. Before a single-board computer access to another single-board computer can complete, however, the VMEchip2 on the accessed board must decode a slave access and request the Local Bus of the second board.
Supervisor Stack Pointer (MC68060) Note Software emulation of CAS2 and misaligned CAS instructions is performed by the MC68060 Software Package, which is included in all Motorola-supplied operating systems for the MVME177P. Contact your sales office for information about obtaining the MC68060 Software Package for use with other operating systems. The single-board computers do not fully support all RMW operations in all possible cases.
1 Programming Issues Sources of Local Bus Errors A TEA* signal (indicating a bus error) is returned to the Local Bus master when a Local Bus time-out occurs, a DRAM parity error occurs and parity checking is enabled, or a VME bus error occurs during a VMEbus access. The sources of Local Bus errors on the Single Board Computers are described in the next subsections.
Error Conditions ❏ A hardware error occurs on the VMEbus. ❏ A VMEbus slave reports an access error (such as parity error). VMEchip2 An 8- or 16-bit write to the LCSR in the VMEchip2 ASIC causes a local BERR∗. Bus Error Processing Because different conditions can cause bus error exceptions, the software must be able to distinguish the source. To aid in this, status registers are provided for every Local Bus master.
1 Programming Issues MPU Parity Error Description: A DRAM parity error. MPU Notification: TEA is asserted during an MPU DRAM access. Status: Bit 9 of the MPU Status and DMA Interrupt Count register in the VMEchip2 at address $FFF40048. Comments: After memory has been initialized, this error normally indicates a hardware problem. MPU Offboard Error Description: An error occurred while the MPU was attempting to access an offboard resource. MPU Notification: TEA is asserted during offboard access.
Error Conditions MPU Local Bus Time-out Description: An error occurred while the MPU was attempting to access a local resource. MPU Notification: TEA is asserted during the MPU access. Status: Bit 7 of the MPU Status and DMA Interrupt Count register (actually in the DMAC Status register). Address $FFF40048 Comments: The Local Bus timer timed out. This usually indicates the MPU tried to read or write an address at which there was no resource. Otherwise, it indicates a hardware problem.
1 Programming Issues DMAC Offboard Error Description: Error encountered while the Local Bus side of the DMAC was attempting to go to the VMEbus. MPU Notification: DMAC interrupt (when enabled) Status: The DLOB bit is set in the DMAC Status register (address $FFF40048 bit 4). Comments: This is normally caused by a programming error. The Local Bus address of the DMAC should not be programmed with a Local Bus address that maps to the VMEbus.
Error Conditions DMAC TEA - Cause Unidentified Description: An error occurred while the DMAC was Local Bus master and additional status was not provided. MPU Notification: DMAC interrupt (when enabled) Status: The DLBE bit is set in the DMAC Status register (address $FFF40048 bit 6). Comments: An 8- or 16-bit write to the LCSR in the VMEchip2 causes this error.
1 Programming Issues SCC Parity Error Description: Parity Error detected while the SCC was reading DRAM. MPU Notification: SCC Transmit Interrupt or SCC Receive Interrupt Status: SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High SCC Receive Current Buffer Address register PCCchip2 SCC Error Status register ($FFF4201C) Comments: SCC Transmit and Receive interrupt enables are controlled in the SCC and in the PCCchip2.
Error Conditions SCC LTO Error Description: Local Bus Time-out occurred while the SCC was Local Bus master. MPU Notification: SCC Transmit Interrupt or SCC Receive Interrupt Status: SCC Transmit Interrupt Status register SCC Transmit Current Buffer Address register SCC Receive Interrupt Status register High SCC Receive Current Buffer Address register PCCchip2 SCC Error Status register ($FFF4201C) Comments: SCC Transmit and Receive interrupt enables are controlled in the SCC and in the PCCchip2.
1 Programming Issues LAN LTO Error Description: Local Bus Time-out occurred while the LANCE was Local Bus master. MPU Notification: PCCchip2 Interrupt (LAN ERROR IRQ) Status: PCCchip2 LAN Error Status register ($FFF42028) Comments: The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the PCCchip2. Control for the interrupt is in the PCCchip2 LAN Error Interrupt Control register ($FFF4202B).
Error Conditions SCSI LTO Error Description: Local Bus Time-out occurred while the 53C710 was Local Bus master. MPU Notification: 53C710 Interrupt Status: 53C710 DMA Status register 53C710 DMA Interrupt Status register PCCchip2 SCSI Error Status register ($FFF4202C) Comments: 53C710 interrupt enables are controlled in the 53C710 and in the PCCchip2. http://www.motorola.
1 Programming Issues 1-64 Computer Group Literature Center Web Site
2VMEchip2 2 Introduction This chapter describes the VMEchip2 ASIC, the local-bus/VMEbus interface chip. The VMEchip2 interfaces the local bus to the VMEbus. In addition to its VMEbus-defined functions, the VMEchip2 includes a local-bus-toVMEbus DMA controller, VME board support features, and Global Control and Status Registers (GCSRs) for interprocessor communications. The following table summarizes the characteristics of the VMEchip2 ASIC. Table 2-1.
VMEchip2 Table 2-1.
Introduction Table 2-1.
VMEchip2 2 Functional Blocks The following sections provide an overview of the functions implemented by the VMEchip2 ASIC. See Figure 2-1 for a block diagram of the VMEchip2. Detailed programming models for the local control and status registers (LCSRs) and the global control and status registers (GCSRs) appear in subsequent sections. Local-Bus-to-VMEbus Interface The local-bus-to-VMEbus interface allows local bus masters access to global resources on the VMEbus.
ADDRESS CONTROL ADDRESS CONTROL DATA ADDRESS ADDRESS http://www.motorola.
VMEchip2 Using the four programmable map decoders, separate VMEbus maps can be created, each with its own attributes. For example, one map can be configured as A32, D32 with write posting enabled while a second map can be A24, D16 with write posting disabled. 2 The first I/O map decoder decodes local bus addresses $FFFF0000 through $FFFFFFFF as the short I/O A16/D16 or A16/D32 area. The other provides an A24/D16 space at $F0000000 to $F0FFFFFF and an A32/D16 space at $F1000000 to $FF7FFFFF.
Functional Blocks have been accessed. This enhances the portability of software because it allows software to run on the system regardless of the physical organization of global memory. Using the local bus map decoder attribute register, the AM code that the master places on the VMEbus can be programmed under software control. The VMEchip2 includes a software-controlled VMEbus access timer. It starts ticking when the chip is requested to do a VMEbus data transfer or an interrupt acknowledge cycle.
VMEchip2 The requester requests the bus if any of the following conditions occur: 2 1. The local bus master initiates either a data transfer cycle or an interrupt acknowledge cycle to the VMEbus. 2. The chip is requested to acquire control of the VMEbus as signaled by the DWB input signal pin. 3. The chip is requested to acquire control of the VMEbus as signaled by the DWB control bit in the LCSR. The local-bus-to-VMEbus requester in the VMEchip2 implements a fair mode.
Functional Blocks VMEbus-to-Local-Bus Interface 2 The VMEbus-to-local-bus interface allows an off-board VMEbus master access to onboard resources. The VMEbus-to-local-bus interface includes the VMEbus slave, write post buffer, and local bus master. Adhering to the IEEE 1014-87 VMEbus standard, the slave can withstand address-only cycles, as well as address pipelining, and respond to unaligned transfers.
VMEchip2 Each map decoder includes an alternate address register and an alternate address select register. These registers allow any or all of the upper 16 VMEbus address lines to be replaced by signals from the alternate address register. This allows the address of local resources to differ from their VMEbus address. 2 The alternate address register also provides the upper eight bits of the local address when the VMEbus slave cycle is A24.
Functional Blocks Using control register bits in the LCSR, the DMAC can be configured to provide the following VMEbus capabilities: Addressing capabilities: A16, A24, A32 Data transfer capabilities: D16, D32, D16/BLT, D32/BLT, D64/BLT (BLT = block transfer) Using the DMA AM (Address Modifier) control register, the address modifier code that the VMEbus DMA controller places on the VMEbus can be programmed under software control.
VMEchip2 The DMAC also supports command chaining through the use of a singlylinked list built in local memory. Each entry in the list includes a VMEbus address, a local bus address, a byte count, a control word, and a pointer to the next entry. When the command chaining mode is enabled, the DMAC reads and executes commands from the list in local memory until all commands are executed.
Functional Blocks and to allow transfers which are not an even byte count or which start at an odd address, with respect to the port size. A 16-bit device should respond with VA<1> high or low. Devices on the local bus should respond to any combination of LA<3..2>. This is required to support the burst mode on the MC680x0 bus. Normally when the non-increment mode is used, the starting address and byte count would be aligned to the port size.
VMEchip2 The DMAC requester requests the bus as required to transfer data to or from the FIFO buffer. 2 The requester implements a fair mode. By setting the DFAIR bit, the requester refrains from requesting the bus until it detects its assigned request line in its negated state. The requester releases the bus when requested to by the DMA controller. The DMAC always releases the VMEbus when the FIFO is full (VMEbus to local bus) or empty (local bus to VMEbus).
Functional Blocks Tick Timers 2 The VMEchip2 includes two general-purpose tick timers. These timers can be used to generate interrupts at various rates or the counters can be read at various times for interval timing. The timers have a resolution of 1 µs. When free running, they roll over every 71.6 minutes. Each tick timer has a 32-bit counter, a 32-bit compare register, a 4-bit overflow register, an enable bit, an overflow clear bit, and a clear-on-compare enable bit.
VMEchip2 2 VMEbus Interrupter The interrupter provides all the signals necessary to allow software to request interrupt service from a VMEbus interrupt handler. The chip connects to all signals that a VMEbus interrupter is required to drive and monitor. Requiring no external jumpers, the chip provides the means for software to program the interrupter to request an interrupt on any one of the seven interrupt request lines.
Functional Blocks VMEbus System Controller 2 With the exception of the optional SERCLK driver and the Power Monitor, the chip includes all the functions that a VMEbus system controller must provide. The system controller is enabled/disabled with the aid of an external jumper (J1), the only jumper required in a VMEchip2-based VMEbus interface. Arbiter The arbitration algorithm used by the chip arbiter is selected by software.
VMEchip2 In addition to the VMEbus timer, the chip contains a local bus timer. This timer asserts the local TEA when the local bus cycle maintained in its asserted state for longer that the programmed time-out period. This timer can be enabled or disabled under software control. The time-out period can be programmed for 8, 64, or 256 seconds. 2 Reset Driver The chip includes both a global and a local reset driver.
Functional Blocks Each of the 31 interrupts can be enabled to generate a local bus interrupt at any level. For example, VMEbus IRQ5 can be programmed to generate a level 2 local bus interrupt. The VMEbus AC fail interrupter is an edge-sensitive interrupter connected to the VMEbus ACFAIL∗ signal line. This interrupter is filtered to remove the ACFAIL∗ glitch which is related to the BBSY∗ glitch. The SYS fail interrupter is an edge-sensitive interrupter connected to the VMEbus SYSFAIL∗ signal line.
VMEchip2 The interrupt handler provides all logic necessary to identify and handle all local interrupts as well as VMEbus interrupts. When a local interrupt is acknowledged, a unique vector is provided by the chip. Edge-sensitive interrupters are not cleared during the interrupt acknowledge cycle and must by reset by software as required. If the interrupt source is the VMEbus, the interrupt handler instructs the VMEbus master to execute a VMEbus IACK cycle to obtain the vector from the VMEbus interrupter.
LCSR Programming Model 4. The operations possible on the register bits, defined as follows: R This bit is a read-only status bit. R/W This bit is readable and writable. W/AC This bit can be set and it is automatically cleared. This bit can also be read. C Writing a 1 to this bit clears this bit or another bit. This bit reads 0. S Writing a 1 to this bit sets this bit or another bit. This bit reads 0. 5.
VMEchip2 Table 2-2.
LCSR Programming Model 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A24 1 BLK D64 1 BLK 1 PRGM 1 DATA 1 4 3 2 1 0 SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER 1 15 14 13 12 SNP 1 11 10 9 WP 1 SUP 1 USR 1 8 7 6 A32 1 5 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST D16 EN MAST WP EN IO2 EN I
VMEchip2 Table 2-2.
LCSR Programming Model 2 15 14 13 VME ACCESS TIMER 12 11 LOCAL BUS TIMER 10 9 8 7 6 5 WD TIME OUT SELECT 4 3 2 1 0 CLR OVF 1 COC EN 1 TIC EN 1 PRESCALER CLOCK ADJUST COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER CLR OVF 2 OVERFLOW COUNTER 2 COC EN 2 TIC EN 2 OVERFLOW COUNTER 1 SCALER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SW7 IRQ SW6 IRQ SW5 IRQ SW4 IRQ SW3 IRQ SW2 IRQ SW1 IRQ SW0 IRQ SPARE VME IRQ7 VME IRQ6 VME IRQ5 VME IRQ4 VME IRQ3 VME IRQ2
VMEchip2 2 Programming the VMEbus Slave Map Decoders This section includes programming information for the VMEbus-to-localbus map decoders. The VMEbus-to-local-bus interface allows off-board VMEbus masters access to local on-board resources. The address of the local resources as viewed from the VMEbus is controlled by the VMEbus slave map decoders, which are part of the VMEbus-to-local-bus interface.
LCSR Programming Model You program a VMEbus slave map decoder by loading the starting address of the segment into the starting address register and the ending address of the segment into the ending address register. If the VMEbus address modifier codes indicate an A24 VMEbus address cycle, then the upper eight bits of the VMEbus address are forced to 0 before the compare. The address modifier select register should be programmed for the required address modifier codes.
VMEchip2 $FFF40010. The adders allow any size board to be mapped on any 64KB boundary. The adders are disabled and the address replacement method is used following reset. 2 Write posting is enabled for the segment by setting the write post enable bit in the attribute register. Local bus snooping for the segment is enabled by setting the snoop bits in the attribute register. The snoop bits in the attribute register are driven on to the local bus when the VMEbus-to-localbus interface is local bus master.
LCSR Programming Model VMEbus Slave Ending Address Register 2 ADR/SIZ BIT 2 $FFF40004 (16 bits of 32) 31 ... NAME Ending Address Register 2 OPER R/W RESET 0 PS 16 This register is the ending address register for the second VMEbus-tolocal-bus map decoder. VMEbus Slave Starting Address Register 2 ADR/SIZ BIT $FFF40004 (16 bits of 32) 15 ... NAME Starting Address Register 2 OPER R/W RESET 0 PS 0 This register is the starting address register for the second VMEbus-tolocal-bus map decoder.
VMEchip2 2 VMEbus Slave Address Translation Select Register 1 ADR/SIZ BIT $FFF40008 (16 bits of 32) 15 ... 0 NAME Address Translation Select Register 1 OPER R/W RESET 0 PS This register is the address translation select register for the first VMEbusto-local-bus map decoder. The address translation select register value is based on the segment size (the difference between the VMEbus starting and ending addresses).
LCSR Programming Model VMEbus Slave Address Translation Address Offset Register 2 ADR/SIZ BIT 2 $FFF4000C (16 bits of 32) 31 ... 16 NAME Address Translation Address Offset Register 2 OPER R/W RESET 0 PS This register is the address translation address register for the second VMEbus-to-local-bus map decoder. It should be programmed to the local bus starting address. When the adder is enabled, this register is the offset value.
VMEchip2 2 VMEbus Slave Write Post and Snoop Control Register 2 ADR/SIZ BIT $FFF40010 (8 bits [4 used] of 32) 31 30 29 28 27 26 25 24 NAME ADDER 2 SNP2 WP2 OPER R/W R/W R/W RESET 0 PS 0 PS 0 PS This register is the slave write post and snoop control register for the second VMEbus-to-local-bus map decoder. WP2 When this bit is high, write posting is enabled for the address range defined by the second VMEbus slave map decoder.
LCSR Programming Model VMEbus Slave Address Modifier Select Register 2 ADR/SIZ 2 $FFF40010 (8 bits of 32) BIT 23 22 21 20 19 18 17 16 NAME SUP USR A32 A24 D64 BLK PGM DAT OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is the address modifier select register for the second VMEbus-to-local-bus map decoder. There are three groups of address modifier select bits: DAT, PGM, BLK and D64; A24 and A32; and USR and SUP.
VMEchip2 2 2-34 A32 When this bit is high, the second map decoder responds to VMEbus A32 (extended) access cycles. When this bit is low, the second map decoder does not respond to VMEbus A32 access cycles. USR When this bit is high, the second map decoder responds to VMEbus user (non-privileged) access cycles. When this bit is low, the second map decoder does not responded to VMEbus user access cycles. SUP When this bit is high, the second map decoder responds to VMEbus supervisory access cycles.
LCSR Programming Model VMEbus Slave Write Post and Snoop Control Register 1 ADR/SIZ BIT 2 $FFF40010 (8 bits [4 used] of 32) 15 14 13 12 11 10 9 8 NAME ADDER 1 SNP1 WP1 OPER R/W R/W R/W RESET 0 PS 0 PS 0 PS This register is the slave write post and snoop control register for the first VMEbus-to-local-bus map decoder. WP1 When this bit is high, write posting is enabled for the address range defined by the first VMEbus slave map decoder.
VMEchip2 2 VMEbus Slave Address Modifier Select Register 1 ADR/SIZ $FFF40010 (8 bits of 32) BIT 7 6 5 4 3 2 1 0 NAME SUP USR A32 A24 D64 BLK PGM DAT OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is the address modifier select register for the first VMEbusto-local-bus map decoder. There are three groups of address modifier select bits: DAT, PGM, BLK and D64; A24 and A32; and USR and SUP.
LCSR Programming Model A32 When this bit is high, the first map decoder responds to VMEbus A32 (extended) access cycles. When this bit is low, the first map decoder does not respond to VMEbus A32 access cycles. USR When this bit is high, the first map decoder responds to VMEbus user (non-privileged) access cycles. When this bit is low, the first map decoder does not respond to VMEbus user access cycles. SUP When this bit is high, the first map decoder responds to VMEbus supervisory access cycles.
VMEchip2 Each of the four programmable local bus map decoders has a starting address, an ending address, an address modifier register with attribute bits, and an enable bit. The fourth decoder also has address translation registers. The addresses and bit definitions for these registers are in the tables below.
LCSR Programming Model Write posting is enabled for the segment by setting the write post enable bit in the address modifier register. D16 transfers are forced by setting the D16 bit in the address modifier register. A segment is enabled by setting the enable bit. Segments should not be programmed to overlap. The first I/O map decoder maps the local bus address range $FFFF0000 to $FFFFFFFF to the A16 (short I/O) map of the VMEbus. This segment may be enabled using the enable bit.
VMEchip2 2 Local Bus Slave (VMEbus Master) Starting Address Register 1 ADR/SIZ BIT $FFF40014 (16 bits of 32) 15 ... NAME Starting Address Register 1 OPER R/W RESET 0 PS 0 This register is the starting address register for the first local-bus-toVMEbus map decoder. Local Bus Slave (VMEbus Master) Ending Address Register 2 ADR/SIZ BIT $FFF40018 (16 bits of 32) 31 ...
LCSR Programming Model Local Bus Slave (VMEbus Master) Ending Address Register 3 ADR/SIZ BIT 2 $FFF4001C (16 bits of 32) 31 ... NAME Ending Address Register 3 OPER R/W RESET 0 PS 16 This register is the ending address register for the third local-bus-toVMEbus map decoder. Local Bus Slave (VMEbus Master) Starting Address Register 3 ADR/SIZ BIT $FFF4001C (16 bits of 32) 15 ...
VMEchip2 2 Local Bus Slave (VMEbus Master) Starting Address Register 4 ADR/SIZ BIT $FFF40020 (16 bits of 32) 15 ... NAME Starting Address Register 4 OPER R/W RESET 0 PS 0 This register is the starting address register for the fourth local-bus-toVMEbus map decoder. Local Bus Slave (VMEbus Master) Address Translation Address Register 4 ADR/SIZ BIT $FFF40024 (16 bits of 32) 31 ...
LCSR Programming Model Local Bus Slave (VMEbus Master) Attribute Register 4 ADR/SIZ 2 $FFF40028 (8 bits of 32) BIT 31 30 NAME D16 WP AM OPER R/W R/W R/W RESET 0 PS 0 PS 0 PS 29 28 27 26 25 24 This register is the attribute register for the fourth local-bus-to-VMEbus bus map decoder. AM These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 4.
VMEchip2 2 Local Bus Slave (VMEbus Master) Attribute Register 3 ADR/SIZ $FFF40028 (8 bits of 32) BIT 23 22 NAME D16 WP AM OPER R/W R/W R/W RESET 0 PS 0 PS O PS 21 20 19 18 17 16 This register is the attribute register for the third local-bus-to-VMEbus bus map decoder. 2-44 AM These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 3.
LCSR Programming Model Local Bus Slave (VMEbus Master) Attribute Register 2 ADR/SIZ 2 $FFF40028 (8 bits of 32) BIT 15 14 NAME D16 WP AM OPER R/W R/W R/W RESET 0 PS 0 PS O PS 13 12 11 10 9 8 This register is the attribute register for the second local-bus-to-VMEbus bus map decoder. AM These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 2.
VMEchip2 2 Local Bus Slave (VMEbus Master) Attribute Register 1 ADR/SIZ $FFF40028 (8 bits of 32) BIT 7 6 NAME D16 WP AM OPER R/W R/W R/W RESET 0 PS 0 PS O PS 5 4 3 2 1 0 This register is the attribute register for the first local-bus-to-VMEbus bus map decoder. 2-46 AM These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 1.
LCSR Programming Model VMEbus Slave GCSR Group Address Register ADR/SIZ BIT 2 $FFF4002C (8 bits of 32) 31 ... NAME GCSR Group Address Register 4 OPER R/W RESET $00 PS 24 This register defines the group address of the GCSR as viewed from the VMEbus. The GCSR address is defined by the group address and the board address. Once enabled, the GCSR register should not be reprogrammed unless the VMEchip2 ASIC is VMEbus master. GCSR Group These bits define the group portion of the GCSR address.
VMEchip2 2 VMEbus Slave GCSR Board Address Register ADR/SIZ BIT $FFF4002C (4 bits of 32) 23 ... NAME GCSR Board Address OPER R/W RESET $F PS 20 This register defines the board address of the GCSR as viewed from the VMEbus. The GCSR address is defined by the group address and the board address. Once enabled, the GCSR register should not be reprogrammed unless the VMEchip2 is VMEbus master. The value $F in the GCSR board address register disables the map decoder.
LCSR Programming Model Local-Bus-to-VMEbus Enable Control Register ADR/SIZ 2 $FFF4002C (4 bits of 32) BIT 19 18 17 16 NAME EN4 EN3 EN2 EN1 OPER R/W R/W R/W R/W RESET 0 PSL 0 PSL 0 PSL 0 PSL This register is the map decoder enable register for the four programmable local-bus-to-VMEbus map decoders. EN1 When this bit is high, the first local-bus-to-VMEbus map decoder is enabled. When this bit is low, the first localbus-to-VMEbus map decoder is disabled.
VMEchip2 2 Local-Bus-to-VMEbus I/O Control Register ADR/SIZ $FFF4002C (8 bits of 32) BIT 15 14 13 12 11 10 9 8 NAME I2EN I2WP I2SU I2PD I1EN I1D16 I1WP I1SU OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PSL 0 PS O PS 0 PS 0 PS O PS 0 PS O PS This register controls the VMEbus short I/O map and the F page ($F0000000 through $FF7FFFFF) I/O map. 2-50 I1SU When this bit is high, the VMEchip2 drives a supervisor address modifier code when the short I/O space is accessed.
LCSR Programming Model I2WP When this bit is high, write posting is enabled to the local bus F page. When this bit is low, write posting is disabled to the local bus F page. I2EN When this bit is high, the F page ($F0000000 through $FF7FFFFF) map decoder is enabled. The F0 page is defined as A24/D16 on the VMEbus while the F1-FE pages are defined as A32/D16. When this bit is low, the F page is disabled.
VMEchip2 A maximum of 4GB of data may be transferred with one DMAC command. Larger transfers can be accomplished using the command chaining mode. In command chaining mode, a singly-linked list of commands is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands. The DMAC control register is programmed and the DMAC is enabled. The DMAC executes commands from the list until all commands are executed or an error is detected.
LCSR Programming Model . 2 Table 2-3. DMAC Command Packet Format Entry Function 0 (bits 0-15) -- Control Word 1 (bits 0-31) Local Bus Address 2 (bits 0-31) VMEbus Address 3 (bits 0-31) Byte Count 4 (bits 0-31) Address of Next Command Packet DMAC Registers This section provides addresses and bit level descriptions of the DMAC counters, control registers, and status registers. Other control functions are also included in this section.
VMEchip2 TBLSC 2 These bits control the snoop signal lines on the local bus when the DMAC is table walking. The snooping functions differ according to processor type, as shown: TBLSC Requested Snoop Operation 19 18 MC68040 0 0 Snoop disabled Snoop enabled 0 1 Source dirty, sink byte/word/longword Snoop disabled 1 0 Source dirty, invalidate line Snoop enabled 1 1 Snoop disabled (Reserved) Snoop disabled ROM0 MC68060 This bit is not used on the MVME1x7P.
LCSR Programming Model 0 1 2 3 The request level is 0. The request level is 1. The request level is 2. The request level is 3. 2 LVRWD When this bit is high, the requester operates in release-when-done mode. When this bit is low, the requester operates in release-on-request mode. LVFAIR When this bit is high, the requester operates in fair mode. When this bit is low, the requester does not operate in fair mode.
VMEchip2 always requests at the old level until it becomes bus master and the new level takes effect. If the VMEchip2 is bus master when the level is changed, the new level does not take effect until the bus has been released and rerequested at the old level. The requester always requests the VMEbus at level 3 the first time following a SYSRESET. 2 0 1 2 3 DRELM These bits define the VMEbus release mode for the DMAC requester.
LCSR Programming Model DMAC Control Register 2 (bits 8-15) ADR/SIZ 2 $FFF40034 (8 bits [7 USED] of 32) BIT 15 NAME INTE OPER RESET 14 13 12 11 10 9 8 SNP VINC LINC TVME D16 R/W R/W R/W R/W R/W R/W 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS This portion of the control register is loaded by the processor or by the DMAC when it loads the command word from the command packet.
VMEchip2 SNP 2 These bits control the snoop signal lines on the local bus when the DMAC is local bus master and it is not accessing the command table.
LCSR Programming Model VMEbus address modifier bits 2-5, and address modifier bits 0 and 1 are provided by the DMAC to indicate a block transfer. Block transfer mode should not be set in the address modifier codes. The special block transfer bits should be set to enable block transfers. If non-block cycles are required to reach a 32- or 64-bit boundary, bits 0 and 1 are used during these cycles.
VMEchip2 2 DMAC VMEbus Address Counter ADR/SIZ BIT $FFF4003C (32 bits) 31 ... NAME DMAC VMEbus Address Counter OPER R/W RESET 0 PS 0 In direct mode, this counter is programmed with the starting address of the data in VMEbus memory. DMAC Byte Counter ADR/SIZ BIT $FFF40040 (32 bits) 31 ... NAME DMAC Byte Counter OPER R/W RESET 0 PS 0 In direct mode, this counter is programmed with the number of bytes of data to be transferred. Table Address Counter ADR/SIZ BIT $FFF40044 (32 bits) 31 ..
LCSR Programming Model VMEbus Interrupter Control Register ADR/SIZ BIT 2 $FFF40048 (8 bits [7 used] of 32) 31 30 29 28 27 26 25 NAME IRQ1S IRQC IRQS IRQL OPER R/W S R S RESET 0 PS 0 PS 0 PS 0 PS 24 This register controls the VMEbus interrupter. IRQL These bits define the level of the VMEbus interrupt generated by the VMEchip2. A VMEbus interrupt is generated by writing the desired level to these bits. These bits always read 0 and writing 0 to these bits has no effect.
VMEchip2 2 VMEbus Interrupter Vector Register ADR/SIZ BIT $FFF40048 (8 bits of 32) 23 ... 16 NAME Interrupter Vector OPER R/W RESET $0F PS This register controls the VMEbus interrupter vector. MPU Status and DMA Interrupt Count Register ADR/SIZ BIT $FFF40048 (8 bits of 32) 15 14 13 12 11 10 9 8 NAME DMAIC MCLR MLBE MLPE MLOB OPER R C R R R RESET 0 PS 0 PS 0 PS 0 PS 0 PS This is the MPU status register and DMAC interrupt counter.
LCSR Programming Model DMAIC The DMAC interrupt counter is incremented when an interrupt is sent to the local bus interrupter. The value in this counter indicates the number of commands processed when the DMAC is operated in command chaining mode. If the interrupt count exceeds 15, the counter rolls over. This counter operates regardless of whether the DMAC interrupts are enabled. This counter is cleared when the DMAC is enabled.
VMEchip2 2 DLPE If this bit is set, the DMAC has received a TEA and the status indicated a parity error during a DRAM data transfer. This bit is cleared when the DMAC is enabled. DLBE If this bit is set, the DMAC has received a TEA and no additional status was provided. This bit is cleared when the DMAC is enabled. MLTO If this bit is set, the MPU has received a TEA and the status indicated a local bus time-out. This bit is cleared by writing a 1 to the MCLR bit in this register.
LCSR Programming Model DMAC Ton/Toff Timers and VMEbus Global Time-out Control Register ADR/SIZ BIT 2 $FFF4004C (8 bits of 32) 23 22 21 20 19 18 17 16 NAME TIME OFF TIME ON VGTO OPER R/W R/W R/W RESET 0 PS 0 PS 0 PS This register controls the DMAC time off timer, the DMAC time on timer, and the VMEbus global time-out timer. VGTO These bits define the VMEbus global time-out value. When DS0 or DS1 is asserted on the VMEbus, the timer begins timing.
VMEchip2 2 VME Access, Local Bus, and Watchdog Time-out Control Register ADR/SIZ BIT $FFF4004C (8 bits of 32) 15 14 13 12 10 9 NAME VATO LBTO WDTO OPER R/W R/W R/W RESET 0 PS 0 PS 0 PS WDTO LBTO VATO 8 These bits define the watchdog time-out period: Bit Encoding 0 1 2 3 4 5 6 7 2-66 11 Time-out 512 µs 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms Bit Encoding 8 9 10 11 12 13 14 15 Time-out 128 ms 256 ms 512 ms 1 s 4 s 16 s 32 s 64 s These bits define the local bus time-out value.
LCSR Programming Model Prescaler Control Register ADR/SIZ BIT 2 $FFF4004C (8 bits of 32) 7 ... NAME Prescaler Adjust OPER R/W RESET $DF P 0 The prescaler provides the various clocks required by the counters and timers in the VMEchip2. In order to specify absolute times from these counters and timers, the prescaler must be adjusted for different local bus clocks. The prescaler register should be programmed based on the following equation. This provides a 1MHz clock to the Tick timers.
VMEchip2 2 Tick Timer 1 Compare Register ADR/SIZ BIT $FFF40050 (32 bits) 31 ... NAME Tick timer 1 Compare Register OPER R/W RESET 0P 0 The tick timer 1 counter is compared to this register. When they are equal, an interrupt is sent to the local bus interrupter and the overflow counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared.
LCSR Programming Model Tick Timer 2 Compare Register 2 ADR/SIZ BIT $FFF40058 (32 bits) 31 ... NAME Tick timer 2 Compare Register OPER R/W RESET 0P 0 The tick timer 2 counter is compared to this register. When they are equal, an interrupt is sent to the local bus interrupter and the overflow counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared.
VMEchip2 2 Board Control Register ADR/SIZ BIT 2-70 $FFF40060 (8 bits [7 used] of 32) 31 30 29 28 27 26 25 NAME SCON SFFL BRFLI PURS OPER R R R R C R/W R/W RESET X X 1 PSL 1P 0 PS 1 PSL 1P CPURS BDFLO 24 RSWE RSWE The RESET switch enable bit is used with the “no VMEbus interface” option. This bit is duplicated at the same bit position in the MC2 chip at location $FFF42044. When this bit or the duplicate bit in the MC2 chip is high, the RESET switch is enabled.
LCSR Programming Model Watchdog Timer Control Register ADR/SIZ 2 $FFF40060 (8 bits of 32) BIT 23 22 21 NAME SRST WDCS WDCC OPER S C C R R/W R/W R/W R/W RESET 0 PS 0 0 0P 0 PSL 0 PSL 1 PSL 0 PSL 20 19 18 17 16 WDTO WDBFE WDS/L WDRSE WDEN WDEN When this bit is high, the watchdog timer is enabled. When this bit is low, the watchdog timer is not enabled. WDRSE When this bit is high, and a watchdog time-out occurs, a SYSRESET or LRESET is generated.
VMEchip2 2 WDCS When this bit is set high, the watchdog time-out status bit (WDTO bit in this register) is cleared. SRST When this bit is set high, a SYSRESET signal is generated on the VMEbus. SYSRESET resets the VMEchip2 and clears this bit. Tick Timer 2 Control Register ADR/SIZ BIT $FFF40060 (8 bits [7 used] of 32) 15 NAME 2-72 14 13 OVF 12 11 10 9 8 COVF COC EN OPER R C R/W R/W RESET 0 PS 0 PS 0 PS 0 PS EN When this bit is high, the counter increments.
LCSR Programming Model Tick Timer 1 Control Register 2 ADR/SIZ $FFF40060 (8 bits of 32) BIT 7 6 5 4 3 2 1 0 NAME OVF COVF COC EN OPER R C R/W R/W RESET 0 PS 0 PS 0 PS 0 PS EN When this bit is high, the counter increments. When this bit is low, the counter does not increment. COC When this bit is high, the counter is reset to 0 when it compares with the compare register. When this bit is low, the counter is not reset.
VMEchip2 2 Programming the Local Bus Interrupter The local bus interrupter is used by devices that need to interrupt the local bus. There are 31 devices that can interrupt the local bus through the VMEchip2. In the general case, each interrupter has a level select register, an enable bit, a status bit, a clear bit, and a set bit for the software interrupts. Each interrupter also provides a unique interrupt vector to the processor.
LCSR Programming Model 2 Table 2-4.
VMEchip2 Table 2-4. Local Bus Interrupter Summary (Continued) 2 Interrupt Vector DMAC $X6 VMEbus Interrupter Acknowledge $X7 Tick Timer 1 $X8 Tick Timer 2 $X9 VMEbus IRQ1 Edge-Sensitive $XA (Not used on MVME1x7P) $XB VMEbus Master Write Post Error $XC VMEbus SYSFAIL $XD (Not used on MVME1x7P) $XE VMEbus ACFAIL $XF Priority for Simultaneous Interrupts : : Highest Notes 1. X = The contents of vector base register 0. 2. Y = The contents of vector base register 1. 3.
LCSR Programming Model Local Bus Interrupter Status Register (bits 24-31) ADR/SIZ 2 $FFF40068 (8 bits of 32) BIT 31 30 29 28 27 26 25 24 NAME ACF AB SYSF MWP PE VI1E TIC2 TIC1 OPER R R R R R R R R RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
VMEchip2 2 Local Bus Interrupter Status Register (bits 16-23) ADR/SIZ $FFF40068 (8 bits of 32) BIT 23 22 21 20 19 18 17 16 NAME VIA DMA SIG3 SIG2 SIG1 SIG0 LM1 LM0 OPER R R R R R R R R RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
LCSR Programming Model Local Bus Interrupter Status Register (bits 8-15) ADR/SIZ 2 $FFF40068 (8 bits of 32) BIT 15 14 13 12 11 10 9 8 NAME SW7 SW6 SW5 SW4 SW3 SW2 SW1 SW0 OPER R R R R R R R R RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
VMEchip2 2 Local Bus Interrupter Status Register (bits 0-7) ADR/SIZ $FFF40068 (8 bits of 32) BIT 7 6 5 4 3 2 1 0 NAME SPARE VME7 VME6 VME5 VME4 VME3 VME2 VME1 OPER R R R R R R R R RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is the local bus interrupter status register. When an interrupt status bit is high, a local bus interrupt is being generated. When an interrupt status bit is low, a local interrupt is not being generated.
LCSR Programming Model Local Bus Interrupter Enable Register (bits 24-31) ADR/SIZ 2 $FFF4006C (8 bits of 32) BIT 31 30 29 28 27 26 25 24 NAME EACF EAB ESYSF EMWP EPE EVI1E ETIC2 ETIC1 OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
VMEchip2 2 Local Bus Interrupter Enable Register (bits 16-23) ADR/SIZ $FFF4006C (8 bits of 32) BIT 23 22 21 20 19 18 17 16 NAME EVIA EDMA ESIG3 ESIG2 ESIG1 ESIG0 ELM1 ELM0 OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
LCSR Programming Model Local Bus Interrupter Enable Register (bits 8-15) ADR/SIZ 2 $FFF4006C (8 bits of 32) BIT 15 14 13 12 11 10 9 8 NAME ESW7 ESW6 ESW5 ESW4 ESW3 ESW2 ESW1 ESW0 OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
VMEchip2 2 Local Bus Interrupter Enable Register (bits 0-7) ADR/SIZ $FFF4006C (8 bits of 32) BIT 7 6 5 4 3 2 1 0 NAME SPARE EIRQ7 EIRQ6 EIRQ5 EIRIQ4 EIRQ3 EIRQ2 EIRQ1 OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This is the local bus interrupter enable register. When an enable bit is high, the corresponding interrupt is enabled. When an enable bit is low, the corresponding interrupt is disabled.
LCSR Programming Model Software Interrupt Set Register (bits 8-15) ADR/SIZ 2 $FFF40070 (8 bits of 32) BIT 15 14 13 12 11 10 9 8 NAME SSW7 SSW6 SSW5 SSW4 SSW3 SSW2 SSW1 SSW0 OPER S S S S S S S S RESET 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL 0 PSL This register is used to set the software interrupts. An interrupt is set by writing a 1 to it. The software interrupt set bits are: SSW0 Set software 0 interrupt. SSW1 Set software 1 interrupt.
VMEchip2 2 CVI1E Clear VMEbus IRQ1 edge-sensitive interrupt. CPE Not used on MVME1x7P. CMWP Clear VMEbus master write post error interrupt. CSYSF Clear VMEbus SYSFAIL interrupt. CAB Not used on MVME1x7P. CACF Clear VMEbus ACFAIL interrupt.
LCSR Programming Model Interrupt Clear Register (bits 8-15) ADR/SIZ 2 $FFF40074 (8 bits of 32) BIT 15 14 13 12 11 10 9 8 NAME CSW7 CSW6 CSW5 CSW4 CSW3 CSW2 CSW1 CSW0 OPER C C C C C C C C RESET X X X X X X X X This register is used to clear the edge software interrupts. An interrupt is cleared by writing a 1 to its clear bit. The clear bits are: CSW0 Clear software 0 interrupt. CSW1 Clear software 1 interrupt. CSW2 Clear software 2 interrupt.
VMEchip2 2 Interrupt Level Register 1 (bits 16-23) ADR/SIZ BIT $FFF40078 (8 bits [6 used] of 32) 23 22 21 20 19 18 17 NAME SYSF LEVEL WPE LEVEL OPER R/W R/W RESET 0 PSL 0 PSL 16 This register is used to define the level of the SYSFAIL interrupt and the master write post bus error interrupt. WPE LEVEL These bits define the level of the master write post bus error interrupt. SYSF LEVEL These bits define the level of the SYSFAIL interrupt.
LCSR Programming Model Interrupt Level Register 1 (bits 0-7) ADR/SIZ BIT 2 $FFF40078 (8 bits [6 used] of 32) 7 6 5 4 3 2 1 NAME TICK2 LEVEL TICK1 LEVEL OPER R/W R/W RESET 0 PSL 0 PSL 0 This register is used to define the level of the tick timer 1 interrupt and the tick timer 2 interrupt. TICK1 LEVEL These bits define the level of the tick timer 1 interrupt. TICK2 LEVEL These bits define the level of the tick timer 2 interrupt.
VMEchip2 2 Interrupt Level Register 2 (bits 16-23) ADR/SIZ BIT $FFF4007C (8 bits [6 used] of 32) 23 22 21 20 19 18 17 NAME SIG3 LEVEL SIG2 LEVEL OPER R/W R/W RESET 0 PSL 0 PSL 16 This register is used to define the level of the GCSR SIG2 interrupt and the GCSR SIG3 interrupt. SIG2 LEVEL These bits define the level of the GCSR SIG2 interrupt. SIG3 LEVEL These bits define the level of the GCSR SIG3 interrupt.
LCSR Programming Model Interrupt Level Register 2 (bits 0-7) ADR/SIZ BIT 2 $FFF4007C (8 bits [6 used] of 32) 7 6 5 4 3 2 1 NAME LM1 LEVEL LM0 LEVEL OPER R/W R/W RESET 0 PSL 0 PSL 0 This register is used to define the level of the GCSR LM0 interrupt and the GCSR LM1 interrupt. LM0 LEVEL These bits define the level of the GCSR LM0 interrupt. LM1 LEVEL These bits define the level of the GCSR LM1 interrupt.
VMEchip2 2 Interrupt Level Register 3 (bits 16-23) ADR/SIZ BIT $FFF40080 (8 bits [6 used] of 32) 23 22 21 20 19 18 17 NAME SW5 LEVEL SW4 LEVEL OPER R/W R/W RESET 0 PSL 0 PSL 16 This register is used to define the level of the software 4 interrupt and the software 5 interrupt. SW4 LEVEL These bits define the level of the software 4 interrupt. SW5 LEVEL These bits define the level of the software 5 interrupt.
LCSR Programming Model Interrupt Level Register 3 (bits 0-7) ADR/SIZ BIT 2 $FFF40080 (8 bits [6 used] of 32) 7 6 5 4 3 2 1 NAME SW1 LEVEL SW0 LEVEL OPER R/W R/W RESET 0 PSL 0 PSL 0 This register is used to define the level of the software 0 interrupt and the software 1 interrupt. SW0 LEVEL These bits define the level of the software 0 interrupt. SW1 LEVEL These bits define the level of the software 1 interrupt.
VMEchip2 2 Interrupt Level Register 4 (bits 16-23) ADR/SIZ BIT $FFF40084 (8 bits [6 used] of 32) 23 22 21 20 19 18 17 NAME VIRQ6 VIRQ5 LEVEL OPER R/W R/W RESET 0 PSL 0 PSL 16 This register is used to define the level of the VMEbus level 5 (IRQ5) interrupt and the VMEbus level 6 (IRQ6) interrupt. The IRQ5 and IRQ6 interrupts may be mapped to any local bus interrupt level. VIRQ5 LEVEL These bits define the level of the VMEbus IRQ5 interrupt.
LCSR Programming Model Interrupt Level Register 4 (bits 0-7) ADR/SIZ BIT NAME OPER RESET 7 2 $FFF40084 (8 bits [6 used] of 32) 5 4 3 2 1 0 VIRQ2 VIRQ1 LEVEL R/W R/W 0 PSL 0 PSL 6 This register is used to define the level of the VMEbus level 1 (IRQ1) interrupt and the VMEbus level 2 (IRQ2) interrupt. The IRQ1 and IRQ2 interrupts may be mapped to any local bus interrupt level. VIRQ1 LEVEL These bits define the level of the VMEbus IRQ1 interrupt.
VMEchip2 2 I/O Control Register 1 ADR/SIZ $FFF40088 (8 bits of 32) BIT 23 22 21 NAME MIEN SYSFL ACFL OPER R/W R R R R/W R/W R/W R/W RESET 0 PSL X X X 0 PS 0 PS 0 PS 0 PS 20 19 18 17 16 ABRTL GPOEN3 GPOEN2 GPOEN1 GPOEN0 This register is a general purpose I/O control register. Bits 16-19 control the direction of the four General Purpose I/O pins (GPIO0-3). 2-96 GPOEN0 When this bit is low, the GPIO0 pin is an input. When this bit is high, the GPIO0 pin is an output.
LCSR Programming Model I/O Control Register 2 2 ADR/SIZ BIT NAME $FFF40088 (8 bits of 32) 15 14 13 12 GPIOO3 GPIOO2 GPIOO1 GPIOO0 11 10 9 8 GPIOI3 GPIOI2 GPIOI1 GPIOI0 OPER R/W R/W R/W R/W R R R R RESET 0 PSL 0 PS 0 PS 0 PS X X X X GPIOO1 Connects to pin 16 of the Remote Status and Control register. GPIOO2 Connects to pin 17 of the Remote Status and Control register. GPIOO3 Connects to pin 18 of the Remote Status and Control register. GPIOI1 Not used.
VMEchip2 2 Miscellaneous Control Register ADR/SIZ $FFF4008C (8 bits of 32) BIT 7 6 5 4 3 2 1 0 NAME MPIRQEN REVEROM DISSRAM DISMST NOELBBSY DISBSYT ENINT DISBGN OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PSL 0 PSL 0 PSL 0 PS 0 PS 0 PS 0 PS 0 PS DISBGN When this bit is high, the VMEbus BGIN filters are disabled. When this bit is low, the VMEbus BGIN filters are enabled. This bit should not be set.
LCSR Programming Model from the retry and the board does not lose its turn on the VMEbus. For this reason, it is recommended that this bit remain low. NOELBBSY When this bit is high, the early release feature of bus busy feature on the VMEbus is disabled. The VMEchip2 drives BBSY∗ low whenever VMEbus AS∗ is low. When this bit is low, the early release feature of bus busy feature on the VMEbus is not disabled.
VMEchip2 2 GCSR Programming Model This section describes the programming model for the Global Control and Status Registers (GCSR) in the VMEchip2. The local bus map decoder for the GCSR registers is included in the VMEchip2. The local bus base address for the GCSR is $FFF40100. The registers in the GCSR are 16 bits wide and they are byte accessible from both the VMEbus and the local bus. The GCSR is located in the 16-bit VMEbus short I/O space and it responds to address modifier codes $29 or $2D.
GCSR Programming Model The Location Monitor Status register provides the status of the location monitors. A location monitor bit is cleared when the VMEchip2 detects a VMEbus cycle to the corresponding location monitor address. When the LM0 or LM1 bits are cleared, an interrupt is set to the local bus interrupter. If the LM0 or LM1 interrupt is enabled in the local bus interrupter, then a local bus interrupt is generated.
VMEchip2 2 Programming the GCSR A complete description of the GCSR appears in the following tables. Each register definition includes a table with five lines. 1. The base address of the register and the number of bits defined in the table. 2. The bits defined by this table. 3. The name of the register or the name of the bits in the register. 4. The operations possible on the register bits, defined as follows: R This bit is a read-only status bit. R/W This bit is readable and writable.
GCSR Programming Model Table 2-5 shows a summary of the GCSR. 2 Table 2-5.
VMEchip2 2 VMEchip2 ID Register ADR/SIZ BIT Local Bus: $FFF40100/VMEbus: $XXY0 (8 bits) 7 ... 0 NAME VMEchip2 ID Register OPER R RESET 10 PS This register is the VMEchip2 ID register. The ID for the VMEchip2 is 10.
GCSR Programming Model SIG3 The SIG3 bit is set when a VMEbus master writes a 1 to it. When the SIG3 bit is set, an interrupt is sent to the local bus interrupter. The SIG3 bit is cleared when the local processor writes a 1 to the SIG3 bit in this register or the CSIG3 bit in the local interrupt clear register. LM0 This bit is cleared by an LM0 cycle on the VMEbus. When this bit is cleared, an interrupt is set to the local bus interrupter.
VMEchip2 2 VMEchip2 Board Status/Control Register ADR/SIZ Local Bus: $FFF40104/VMEbus: $XXY2 (8 bits [5 used]) BIT 7 6 5 4 3 NAME RST ISF BF SCON SYSFL OPER S/R R/W R R R RESET 0 PSL 0 PSL 1 PS X 1 PSL 2 1 0 This register is the VMEchip2 board status/control register. 2-106 SYSFL This bit is set when the VMEchip2 is driving the SYSFAIL signal. SCON This bit is set if the VMEchip2 is system controller. BF When this bit is high, the Board Fail signal is active.
GCSR Programming Model General Purpose Register 0 ADR/SIZ BIT 2 Local Bus: $FFF40108/VMEbus: $XXY4 (16 bits) 15 ... NAME General Purpose Register 0 OPER R/W RESET 0 PS 0 This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification. General Purpose Register 1 ADR/SIZ BIT Local Bus: $FFF4010C/VMEbus: $XXY6 (16 bits) 15 ...
VMEchip2 2 General Purpose Register 3 ADR/SIZ BIT Local Bus: $FFF40114/VMEbus: $XXYA (16 bits) 15 ... NAME General Purpose Register 3 OPER R/W RESET 0 PS 0 This register is a general purpose register that allows a local bus master to communicate with a VMEbus master. The function of this register is not defined by the hardware specification. General Purpose Register 4 ADR/SIZ BIT Local Bus: $FFF40118/VMEbus: $XXYC (16 bits) 15 ...
3PCCchip2 3 Introduction This chapter defines the peripheral channel controller ASIC, referred to hereafter as the PCCchip2. The PCCchip2 is designed to interface an MC68040-compatible local bus (Local Bus) to various peripheral devices. Summary of Major Features This section lists the major features of the PCCchip2. ❏ BBRAM interface with dynamic sizing support. ❏ 8-bit parallel I/O port. ❏ Master and slave interface for CD2401 Intelligent Multi-Protocol Peripheral.
PCCchip2 Functional Description The following sections provide an overview of the functions provided by the PCCchip2. A detailed programming model for the PCCchip2 control and status registers is provided in a later section. 3 General Description The PCCchip2 interfaces the MC68040 microprocessor bus to the local peripherals on the Single-Board Computers including: battery-backed RAM, Serial Communications Controller (CL-CD2401), LAN controller (82596CA), and SCSI controller (NCR53C710).
Functional Description BBRAM Interface The PCCchip2 provides a read/write interface to the BBRAM by any bus master on the MC68040 bus. The PCCchip2 performs dynamic sizing for accesses to the 8-bit BBRAM to make it appear contiguous. This feature allows code to be executable from the BBRAM. The BBRAM device access time must be no greater than 5 BCLK periods in fast mode or 9 BCLK periods in slow mode. The BBRAM speed option is controlled by a control bit in the General Control Register.
PCCchip2 MPU Channel Attention access is used to cause the 82596CA to begin executing memory resident Command blocks. To execute an MPU Channel Attention, the Local Bus bus master performs a simple read or write to address $FFF46004. 3 MC68040-Bus Master Support for 82596CA The 82596CA has DMA capability with an Intel i486-bus interface. When it is the local bus master, external hardware is needed to convert its bus cycles into MC68040-bus cycles.
Functional Description memory. The LANC Error Status Register in the PCCchip2 is updated and a LANC bus error interrupt is generated if it is enabled in the PCCchip2. The Back Off signal remains asserted until the 82596CA is reset via a port reset command. After the 82596CA is reset, pending operations must be restarted. If the GPIO2 signal is programmed as an output and set low, bus errors are processed in the following way.
PCCchip2 53C710 SCSI Controller Interface The PCCchip2 provides a map decoder and an interrupt handler for the NCR-53C710 SCSI I/O Processor. The base address for the 53C710 is $FFF47000. 3 When the PCCchip2 detects low a level on the IRQ* line from the 53C710, if such interrupts are enabled, it generates an interrupt to the MPU. If the C040 bit is set, the interrupt request goes to the MPU via the EIPL* pins at the level that is programmed for SCSI interrupts in the SCSI Interrupt Control Register.
Functional Description General Purpose I/O Pin The General Purpose I/O pin can be used as an input pin, as an output pin, or as both. The PCCchip2 has a status bit that reflects the state of the pin. The PCCchip2 also has a control bit that allows it to drive the pin, and another control bit that controls the level that is driven.
PCCchip2 to the CD2401. Note that the PCCchip2 drives the CD2401 A7-A0 pins with $01 for modem interrupt acknowledges, $02 for transmit interrupt acknowledges and $03 for receive interrupt acknowledges.) The use of the auto vector mode is not recommended because the CD2401 can supply the vector and the CD2401 requires an interrupt acknowledge cycle. 3 In order to support polling with the CD2401, the PCCchip2 supports pseudo interrupt acknowledge (PIACK) cycles to the CD2401.
Functional Description Tick Timer The PCCchip2 includes two 32-bit general purpose tick timers. The tick timers run on a 1MHz clock which is derived from the processor clock by a prescaler. Each tick timer has a 32-bit counter, a 32-bit compare register, and a clearon-compare enable bit. The counter is readable and writable at any time. These timers can be used to generate interrupts at various rates or the counters can be read at various times for interval timing.
PCCchip2 Overall Memory Map The following memory map includes all devices selected by the PCCchip2 map decoders, including those internal to the chip and those external. These devices respond only when the Transfer Type signals carry the values of %00 or %01 which correspond to Normal and MOVE16 accesses on the Local Bus. 3 Table 3-1.
Programming Model Programming Model This section defines the programming model for the control and status registers (CSR) in the PCCchip2. The base address of the CSR is $FFF42000. The PCCchip2 control and status registers can be accessed as bytes (8 bits), two-bytes (16 bits), or four-bytes(32 bits). The possible operations for each bit in the CSR are as follows: R This bit is a read only status bit. R/W This bit is readable and writable. W/AC This bit can be set and it is automatically cleared.
PCCchip2 Table 3-2.
Programming Model 3 D15 D8 DRO CPU 040 MSTR INT EN FAST BRAM CLR OVF 2 COC EN 2 TIC EN 2 D7 D0 VECTOR BASE REGISTER COMPARE REGISTER COUNTER REGISTER COMPARE REGISTER COUNTER REGISTER OVERFLOW COUNTER 2 TIC2 INT TIC2 IEN TIC2 ICLR TIC TIMER 2 IRQ LEVEL SCC TX IRQ SCC TX IEN SCC TX AVEC SCC TRANSMIT IRQ LEVEL CLR OVF 1 OVERFLOW COUNTER 1 SCC SC1 SCC SC0 COC EN 1 TIC EN 1 TIC1 INT TIC1 IEN TIC1 ICLR TIC TIMER 1 IRQ LEVEL SCC RX IRQ SCC RX IEN SCC RX AVEC SCC RECEIVE IRQ LEVE
PCCchip2 Chip ID Register The Chip ID Register is located at $FFF42000. It is an 8-bit read-only register that is hard-wired to a hexadecimal value of $20. Writes to this register are ignored; however, the PCCchip2 always terminates the cycles properly with TA*.
Programming Model General Control Register The General Control Register is located at $FFF42002. It is an 8-bit register that controls chip general functions. The Master Interrupt Enable bit (MIEN) must be set high for any interrupts from the PCCchip2 to be asserted to the processor.
PCCchip2 C040 CPU040. This bit should remain set to indicate that the MPU is from the M68000 family. When the bit is set, EIPL<2..0>∗ are driven as outputs which carry the priority encoded interrupt request from the PCCchip2 interrupt sources. When the bit is cleared, EIPL<2..0>∗ are not driven as outputs, but are inputs only. DR0 Download ROM at 0 (not applicable to MVME1X7P). This bit should remain cleared, so that DROM appears only in its normal address range.
Programming Model A normal read access to the Vector Base Register yields the value $0F if the read happens before it has been initialized. A normal read access yields all 0s on bits 0-3 and the value that was last written on bits 4-7 if the read happens after the Vector Base Register has been initialized. A suggested setting of the Vector Base Register is $50.
PCCchip2 A suggested setting of the Local Interrupt Vector Register in the SCC chip is $5C. This produces the following vectors: 3 $5C Serial RX Exception IRQ $5D Serial Modem IRQ $5E Serial TX IRQ $5F Serial RX IRQ Programming the Tick Timers This section provides addresses and bit level descriptions of the prescaler, tick timers, and various other timer registers. Tick Timer 1 Compare Register The Tick Timer 1 Compare Register is a 32-bit register located at $FFF42004.
Programming Model Tick Timer 1 Counter The Tick Timer 1 Counter is a 32-bit read/write register located at address $FFF42008. When enabled, it increments every microsecond. Software may read or write the counter at any time. ADR/SIZ BIT $FFF42008 (32 bits) 31 ... NAME Tick Timer 1 Counter OPER R/W RESET X 0 Tick Timer 2 Compare Register The Tick Timer 2 Compare Register is a 32-bit register located at $FFF4200C. The count value of Tick Timer 2 is compared to this register.
PCCchip2 Tick Timer 2 Counter The Tick Timer 2 Counter is a 32-bit read/write register located at address $FFF42010. When enabled, it increments every microsecond. Software may read or write the counter at any time. 3 ADR/SIZ BIT $FFF42010 (32 bits) 31 ... NAME Tick Timer 2 Counter OPER R/W RESET X 0 Prescaler Count Register The Prescaler Count Register is an 8-bit counter used to generate the 1 MHz clock for the two tick timers.
Programming Model frequency is used for BCLK. To provide a 1 MHz clock to the tick timers, the prescaler adjust register should be programmed based on the following equation: 3 prescaler clock adjust register = 256 - BCLK (MHz) For example, for operation at 20 MHz the prescaler value is $EC, at 25 MHz it is $E7, and at 33 MHz it is $DF. Non-integer Local Bus clocks introduce an error into the specified times for the tick timers. The tick timer clock can be derived by the following equation.
PCCchip2 Tick Timer 2 Control Register This is an 8-bit read/write register that controls Tick Timer 2. It is located at address $FFF42016. 3 ADR/SIZ 3-22 $FFF42016 (8 bits) BIT 15 14 13 12 NAME OVF3 OVF2 OVF1 OVF0 OPER R R R R RESET 0 PL 0 PL 0 PL 0 PL 11 10 9 8 COVF COC CEN R C R/W R/W 0 0 PL 0 PL 0 PL CEN Counter Enable. When this bit is high, the counter increments. When this bit is low, the counter does not increment. COC Clear On Compare.
Programming Model Tick Timer 1 Control Register This is an 8-bit read/write register that controls Tick Timer 1. It is located at address $FFF42017. ADR/SIZ $FFF42017 (8 bits) BIT 7 6 5 4 NAME OVF3 OVF2 OVF1 OVF0 OPER R R R R RESET 0 PL 0 PL 0 PL 0 PL 3 2 1 0 COVF COC CEN R C R/W R/W 0 0 PL 0 PL 0 PL CEN Counter Enable. When this bit is high, the counter increments. When this bit is low, the counter does not increment. COC Clear On Compare.
PCCchip2 General Purpose Input Interrupt Control Register ADR/SIZ 3 $FFF42018 (8 bits) BIT 31 30 29 28 27 26 25 24 NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0 OPER R/W R/W R R/W C R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 These three bits select the interrupt level for the general purpose input/output (GPIO) pin. Level 0 does not generate an interrupt. ICLR In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.
Programming Model General Purpose Input/Output Pin Control Register ADR/SIZ BIT $FFF42019 (8 bits) 23 22 21 20 19 NAME 18 17 16 GPI GPOE GPO OPER R R R R R R R/W R/W RESET 0 0 0 0 0 X 0 PL 0 PL GPO When GPO is set, and GPOE is set, the GPIO pin is at a logic high level. When GPO is cleared, and GPOE is set, the GPIO pin is at a logic low level. GPOE This bit controls whether or not the PCCchip2 drives the GPIO pin. When GPOE is set, the PCCchip2 drives the GPIO pin.
PCCchip2 INT Interrupt Status. When this bit is high a Tick Timer 2 interrupt is being generated at the level programmed in IL2-IL0 (if nonzero). This bit is edge-sensitive and can be cleared by writing a logic 1 into the ICLR control bit. 3 Tick Timer 1 Interrupt Control Register ADR/SIZ BIT $FFF4201B (8 bits) 7 6 NAME 3-26 5 4 3 2 1 0 INT IEN ICLR IL2 IL1 IL0 OPER R R R R/W C R/W R/W R/W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 Interrupt Request Level.
Programming Model SCC Error Status and Interrupt Control Registers This section provides addresses and bit level descriptions of the SCC interrupt control registers and status registers. 3 SCC Error Status Register ADR/SIZ BIT $FFF4201C (8 bits) 28 27 26 25 24 NAME RTRY PRTY EXT LTO SCLR OPER R R R R W/R-0 0 PL 0 PL 0 PL 0 PL 0 RESET 31 0 SCLR 30 0 29 0 Writing a 1 to this bit clears bits 25 through 28 (LTO, EXT, PRTY, and RTRY). Reading this bit always yields 0.
PCCchip2 SCC Modem Interrupt Control Register ADR/SIZ BIT 3 $FFF4201D (8 bits) 23 22 NAME 3-28 21 20 19 18 17 16 IRQ IEN AVEC IL2 IL1 IL0 OPER R R R R/W R/W R/W R/W R/W RESET 0 0 X 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 Interrupt Request Level. These three bits select the interrupt level for SCC modem Interrupt. Level 0 does not generate an interrupt. AVEC When this bit is high, the PCCchip2 supplies the interrupt vector to the MPU during an IACK for SCC modem interrupt.
Programming Model SCC Transmit Interrupt Control Register ADR/SIZ BIT $FFF4201E (8 bits) 15 14 NAME 13 12 11 10 9 8 IRQ IEN AVEC IL2 IL1 IL0 OPER R R R R/W R/W R/W R/W R/W RESET 0 0 X 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 Interrupt Request Level. These three bits select the interrupt level for SCC Transmit Interrupt. Level 0 does not generate an interrupt.
PCCchip2 SCC Receive Interrupt Control Register ADR/SIZ 3 $FFF4201F (8 bits) BIT 7 6 5 4 3 2 1 0 NAME SC1 SC0 IRQ IEN AVEC IL2 IL1 IL0 OPER R/W R/W R R/W R/W R/W R/W R/W RESET 0 PL 0 PL X 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 Interrupt Request Level. These three bits select the interrupt level for SCC Receive Interrupt. Level 0 does not generate an interrupt.
Programming Model Modem PIACK Register ADR/SIZ $FFF42023 (8 bits) BIT 7 6 5 4 3 2 1 0 NAME MIV7 MIV6 MIV5 MIV4 MIV3 MIV2 MIV1 MIV0 OPER R R R R R R R R RESET X X X X X X X X The Modem PIACK Register is used to execute modem pseudo interrupt acknowledge cycles to the CD2401. When the Local Bus master initiates a read cycle to this register, the PCCchip2 executes an interrupt acknowledge cycle to the CD2401 with A7-A0 = $01.
PCCchip2 Transmit PIACK Register ADR/SIZ 3 $FFF42025 (8 bits) BIT 23 22 21 20 19 18 17 16 NAME TIV7 TIV6 TIV5 TIV4 TIV3 TIV2 TIV1 TIV0 OPER R R R R R R R R RESET X X X X X X X X The Transmit PIACK Register is used to execute transmit pseudo interrupt acknowledge cycles to the CD2401. When the Local Bus master initiates a read cycle to this register, the PCCchip2 executes an interrupt acknowledge cycle to the CD2401 with A7-A0 = $02.
Programming Model Receive PIACK Register ADR/SIZ $FFF42027 (8 bits) BIT 7 6 5 4 3 2 1 0 NAME RIV7 RIV6 RIV5 RIV4 RIV3 RIV2 RIV1 RIV0 OPER R R R R R R R R RESET X X X X X X X X The Receive PIACK Register is used to execute receive pseudo interrupt acknowledge cycles to the CD2401. When the Local Bus master initiates a read cycle to this register, the PCCchip2 executes an interrupt acknowledge cycle to the CD2401 with A7-A0 = $03.
PCCchip2 LANC Error Status and Interrupt Control Registers This section provides addresses and bit level descriptions of the LANC interrupt control registers and status register. 3 LANC Error Status Register ADR/SIZ BIT $FFF42028 (8 bits) 31 30 29 28 NAME 27 26 25 24 PRTY EXT LTO SCLR OPER R R R R R R R W/R-0 RESET 0 0 0 0 0 PL 0 PL 0 PL 0 SCLR Writing a 1 to this bit clears bits 25 through 27 (LTO, EXT, and PRTY). Reading this bit always yields 0.
Programming Model 82596CA LANC Interrupt Control Register ADR/SIZ $FFF4202A (8 bits) BIT 15 14 13 12 11 10 9 8 NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0 OPER R/W R/W R R/W C R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 Interrupt Request Level. These three bits select the interrupt level for the 82596CA LANC. Level 0 does not generate an interrupt. ICLR In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.
PCCchip2 LANC Bus Error Interrupt Control Register ADR/SIZ 3 $FFF4202B (8 bits) BIT 7 6 5 4 3 2 1 0 NAME SC1 SC0 INT IEN ICLR IL2 IL1 IL0 OPER R/W R/W R R/W C R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 Interrupt Request Level. These three bits select the interrupt level. Level 0 does not generate an interrupt. ICLR Writing a logic 1 into this bit clears the INT status bit. This bit is always read as zero. IEN Interrupt Enable.
Programming Model Programming the SCSI Error Status and Interrupt Registers This section provides address and bit level description of the SCSI interrupt control register and status register. 3 SCSI Error Status Register ADR/SIZ BIT $FFF4202C (8 bits) 31 30 29 28 NAME 27 26 25 24 PRTY EXT LTO SCLR OPER R R R R R R R W/R-0 RESET 0 0 0 0 0 PL 0 PL 0 PL 0 SCLR Writing a 1 to this bit clears bits 25 through 27 (LTO, EXT, and PRTY). Reading this bit always yields 0.
PCCchip2 SCSI Interrupt Control Register ADR/SIZ BIT 3 $FFF4202F (8 bits) 7 6 NAME 5 4 3 IRQ IEN 2 1 0 IL2 IL1 IL0 OPER R/W R/W R R/W R/W R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 Interrupt Request Level. These three bits select the interrupt level for the SCSI Processor. Level 0 does not generate an interrupt. IEN Interrupt Enable. When this bit is high, the interrupt is enabled. The interrupt is disabled when this bit is low.
Programming Model Programming the Printer Port This section provides addresses and bit level descriptions of the printer port control, status, and data registers. Printer ACK Interrupt Control Register ADR/SIZ $FFF42030 (8 bits) BIT 31 30 29 28 27 26 25 24 NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0 OPER R/W R/W R R/W C R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 These three bits select the interrupt level for the printer ACK.
PCCchip2 Printer FAULT Interrupt Control Register ADR/SIZ 3 $FFF42031 (8 bits) BIT 23 22 21 20 19 18 17 16 NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0 OPER R/W R/W R R/W C R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 These three bits select the interrupt level for the printer FAULT. Level 0 does not generate an interrupt. ICLR In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.
Programming Model Printer SEL Interrupt Control Register ADR/SIZ $FFF42032 (8 bits) BIT 15 14 13 12 11 10 9 8 NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0 OPER R/W R/W R R/W C R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 These three bits select the interrupt level for the printer SEL. Level 0 does not generate an interrupt. ICLR In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.
PCCchip2 Printer PE Interrupt Control Register ADR/SIZ 3 $FFF42033 (8 bits) BIT 7 6 5 4 3 2 1 0 NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0 OPER R/W R/W R R/W C R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 These three bits select the interrupt level for the printer PE. Level 0 does not generate an interrupt. ICLR In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit. This bit has no function in levelsensitive mode.
Programming Model Printer BUSY Interrupt Control Register ADR/SIZ $FFF42034 (8 bits) BIT 31 30 29 28 27 26 25 24 NAME PLTY E/L* INT IEN ICLR IL2 IL1 IL0 OPER R/W R/W R R/W C R/W R/W R/W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2-IL0 These three bits select the interrupt level for the printer BUSY. Level 0 does not generate an interrupt. ICLR In edge-sensitive mode, writing a logic 1 to this bit clears the INT status bit.
PCCchip2 Printer Input Status Register ADR/SIZ 3 3-44 $FFF42036 (8 bits) BIT 15 NAME PINT OPER R R RESET X 0 14 13 12 11 10 9 8 ACK FLT SEL PE BSY R R R R R R 0 X X X X X BSY This bit reflects the state of the Printer Busy input pin. It is 1 when BSY is high and 0 when BSY is low. PE This bit reflects the state of the Printer Paper Error input pin. It is 1 when PE is high and 0 when PE is low. SEL This bit reflects the state of the Printer Select input pin.
Programming Model Printer Port Control Register ADR/SIZ BIT $FFF42037 (8 bits) 7 6 5 NAME 4 3 2 1 0 DOEN INP STB FAST MAN OPER R R R R/W R/W R/W R/W R/W RESET 0 0 0 0 PL 0 PL 0 PL 0 PL 0 PL MAN Manual Strobe Control - This bit selects the auto or manual mode for the printer strobe. When this bit is low, the printer strobe is generated automatically by a write to the Printer Data Register (auto mode).
PCCchip2 INP Printer Input Prime - This bit controls the input prime signal. When this bit is high, the input prime signal is activated. When this bit is low, the input prime signal is not activated. Software must control the timing of the printer input prime signal. DOEN Printer Data Output Enable - This bit controls the external data buffer for the printer port. When this bit is high, the external printer data buffer is enabled. When this bit is low, the external printer data buffer is disabled.
Programming Model Printer Data Register ADR/SIZ $FFF4203A (16-bits) BIT 15-0 NAME PD15 - PD0 OPER R/W RESET X PD15-PD0 3 Writing to these bits causes the PCCchip2 to latch data into the external printer data buffer. Generally the printer data buffer only connects to PD7-PD0, because most printer data paths are 8 bits wide. PD7-PD0 can be accessed as an 8-bit register at location $FFF4203B, or PD15-PD0 can be accessed as a 16-bit register at location $FFF4203A.
PCCchip2 Interrupt Priority Level Register ADR/SIZ BIT 3 $FFF4203E (8 bits) 15 14 13 12 11 NAME 10 9 8 IPL2 IPL1 IPL0 OPER R R R R R R R R RESET 0 0 0 0 0 X X X IPL2-IPL0 Interrupt Priority Level - These bits reflect the priorityencoded interrupt request level. This level is a combination of the PCCchip2 interrupt requests and the interrupt requests driven onto the EIPL2-EIPL0 pins.
Programming Model Interrupt Mask Level Register ADR/SIZ BIT $FFF4203F (8 bits) 7 6 5 4 3 NAME 2 1 0 MSK2 MSK1 MSK0 OPER R R R R R R/W R/W R/W RESET 0 0 0 0 0 1 PL 1 PL 1 PL MSK2-MSK0 Interrupt Mask Level - The interrupt mask level bits determine the level which must be exceeded by IPL2IPL0 in order for the PCCchip2 to assert its INT pin.
PCCchip2 3 3-50 Computer Group Literature Center Web Site
4MCECC Functions 4 Introduction The ECC DRAM Controller ASIC (MCECC) is a device used on earlier MVME167/177 models whose functions are now incorporated into the Petra chip on the MVME1x7. The two memory controllers modeled in Petra duplicate the functionality of the “parity memory controller” found in MC ASICs as well as that of the “single-bit error correcting/double-bit error detecting” memory controller found in MCECC ASICs.
MCECC Functions Features MCECC functions now implemented on the Petra chip include: Table 4-1.
Functional Description Functional Description The following sections provide an overview of the functions provided by the Petra MCECC sector. For a detailed programming model for the Petra/MCECC control and status registers, refer to the Programming Model section. 4 General Description The Petra MCECC sector is a single-chip solution for memory control functions. The memory architecture is a single bank of SDRAM, 32 bits wide plus seven check bits.
MCECC Functions Note 4 The table is not complete because it cannot account for the effects of a write posting operation. If the Petra MCECC sector is idle and a write cycle is initiated on the local bus, the cycle is writeposted and the local bus is acknowleged in two clock ticks. If another bus cycle is initiated while the write post operation is in progress, the new cycle is stalled until the write posting is complete.
Functional Description ECC The Petra MCECC sector pair performs single-bit error correction and double-bit error detection (SECDED). Since the SDRAM device can deliver data from incremental addresses with each clock tick (subject to boundary limitations), the Petra MCECC sector does not implement an interleaved memory architecture. The SDRAM array is 32 data bits plus seven checkbits wide. The depth is dependent on the number and type of SDRAM devices.
MCECC Functions Double Bit Error (Cycle Type = Burst Read or Non-Burst Read) You cannot correct the data that is driven to the local MC680x0 bus. 1. Leave the error in DRAM. (Note that the error is not corrected in DRAM during the next scrub of that address.) 2. Terminate the cycle with Bus Error (assert TEA∗ to the local bus) if so enabled. 4 3. Log the error if not already logged. 4. Notify the local MPU via interrupt, if so enabled.
Functional Description 4. Notify the local MPU via interrupt if so enabled. Triple (or Greater) Bit Error (Cycle Type = Non-Burst Write) Some of these errors are detected correctly and are handled the same as a double-bit error. The rest may show up as "no error" or "single-bit error", both of which are incorrect. Single Bit Error (Cycle Type = Scrub) 1. Write corrected data to the DRAM. 2. Log the error if not already logged. 3. Notify the local MPU via interrupt if so enabled.
MCECC Functions Error Logging ECC error logging is facilitated by the Petra MCECC sector because of its internal latches. When an error (single- or double-bit) occurs in the DRAMs to which the MCECC sector is connected, it freezes the address of the error and the syndrome bits associated with the data that is in error. Each MCECC sector segment performs this logging function independently of the other.
Functional Description Arbitration The MCECC sector has three different entities that can request use of the DRAM cycle controller: (1) the local bus master, (2) the refresher, and (3) the scrubber. The MCECC pair arbiter accepts requests and provides grants to the requesting entities as follows: 4 ❏ Priority is (highest to lowest) refresher, local bus, and scrubber. ❏ When no requests are pending, the arbiter defaults to providing a local bus grant for fast response to local bus cycles.
MCECC Functions Programming Model This section defines the programming model for the control and status registers (CSRs) in the MCECC sector. The base address of the CSRs is hard-coded to the address $FFF43000 for the MCECC sector on the first mezzanine board and to $FFF43100 for the MCECC sector on the second mezzanine board. 4 Note that several bits in the register map have changed in functionality from the MCECC ASIC pair.
Programming Model Table 4-3.
MCECC Functions Table 4-3.
Programming Model Chip ID Register The Chip ID register is hard-wired to a hexadecimal value of $81. The Petra MCECC sector can be given a software reset by writing a value of $0F to this register. This write is terminated properly with TA∗ and sets most internal registers to their default (power-up) state. Although writes of any value other than $0F to this register are ignored, the MCECC sector always terminates the cycles properly with TA∗.
MCECC Functions Memory Configuration Register ADR/SIZ 1st $FFF43008/2nd $FFF43108 (8-bits) BIT 31 30 29 28 27 26 25 24 NAME 0 0 FSTRD 0 0 MSIZ2 MSIZ1 MSIZ0 OPER R R R R R R R R RESET X X X X X X X X 4 MSIZ2-MSIZ0 MSIZ2-MSIZ0 together define the size of the total memory to be controlled by the MCECC sector. These bits reflect the RSIZ2-RSIZ0 bits in Defaults Register 1.
Programming Model Base Address Register These eight bits are combined with the two most significant bits in Register 7 (the next register) to form BAD31-BAD22, which defines the base address of the memory. For larger memory sizes, the lower significant bits are ignored.
MCECC Functions NCEBEN Setting the NCEBEN control bit enables the MCECC pair to assert TEA∗ when a non-correctable error occurs during a local bus access to memory. In some cases setting NCEBEN causes DRAM accesses to be delayed by one clock. This delay is incurred when the access is a local bus (or scrub) read and the FSTRD bit is set. 4 NCEIEN When NCEIEN is set, the logging of a non-correctable error causes the INT signal pin to pulse true. Note that NCEIEN has no effect on DRAM access time.
Programming Model Note This register is configured only during power-up-reset and is unchanged by software or local reset.
MCECC Functions The writing of checkbits causes the MCECC sector to perform a read-modify-write to DRAM. If the location to which check bits are being written has a single- or doublebit error, data in the location may be altered by the write checkbits operation. To avoid this, it is recommended that the DERC bit also be set while the RWCKB bit is set. A suggested sequence for performing read-write checkbits is as follows: 4 1.
Programming Model cleared during normal system operation. DERC also allows the write portion of a read-modify-write to complete regardless of whether or not there was a multiple bit error during the read portion of the read-modify-write. DERC also affects scrub cycles.
MCECC Functions SCRB This status bit reflects the state of the scrubber. When the scrubber is in the process of doing a scrub, this bit is set. When the scrubber is between scrubs, this bit is cleared. Scrub Period Register Bits 15-8 4 The Scrub Period Control register controls how often a scrub of the entire memory is performed if the SCRBEN bit is set in the Scrub Control register. The time between scrubs is approximately two seconds times the value programmed into the Scrub Period register.
Programming Model Chip Prescaler Counter This register reflects the current value in the prescaler counter. The Prescaler counter is used with the BCLK Frequency register to produce a 1MHz clock signal for use by the refresher and by the scrubber. The register is readable and writable for test purposes. Programming of this register is not recommended.
MCECC Functions 4 STOFF2 STOFF1 STOFF0 Scrubber Time Off 0 0 0 Request DRAM immediately 0 0 1 Request DRAM after 16 BCLK cycles 0 1 0 Request DRAM after 32 BCLK cycles 0 1 1 Request DRAM after 64 BCLK cycles 1 0 0 Request DRAM after 128 BCLK cycles 1 0 1 Request DRAM after 256 BCLK cycles 1 1 0 Request DRAM after 512 BCLK cycles 1 1 1 Request DRAM never STON2-STON0 STON2-STON0 control the amount of time that the scrubber occupies the DRAM before providing a window durin
Programming Model Note that if STON2-0 is zero, the scrubber always releases the DRAM after one memory cycle, even if neither the local bus nor refresher need it. RWB7 Read/Write Bit 7 is a general-purpose read/write bit. 4 Scrub Prescaler Counter (Bits 21-16) The Scrub Prescaler counter uses the 1MHz clock as an input to create the 0.5 Hz clock that is used for the scrub period. Writes to this address update the scrub prescaler. Reads to this address yield the value in the scrub prescaler.
MCECC Functions Scrub Prescaler Counter (Bits 7-0) This register reflects the current value in the scrub prescaler bits 7-0. ADR/SIZ 4 1st $FFF43040/2nd $FFF43140 (8-bits) BIT 31 30 29 28 27 26 25 24 NAME SPS7 SPS6 SPS5 SPS4 SPS3 SPS2 SPS1 SPS0 OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS Scrub Timer Counter (Bits 15-8) This read/write register is the Scrub Timer counter.
Programming Model Scrub Timer Counter (Bits 7-0) This register reflects the current value in the Scrub Timer counter bits 7-0. ADR/SIZ BIT 1st $FFF43048/2nd $FFF43148 (8-bits) 31 30 29 28 27 26 25 24 NAME ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 4 Scrub Address Counter (Bits 26-24) This read/write register is the Scrub Address counter.
MCECC Functions Scrub Address Counter (Bits 23-16) This register reflects the current value in the Scrub Address counter bits 23-16. ADR/SIZ 4 BIT 1st $FFF43050/2nd $FFF43150 (8-bits) 31 30 29 28 27 26 25 24 NAME SAC23 SAC22 SAC21 SAC20 SAC19 SAC18 SAC17 SAC16 OPER R/W R/W R/W R/W R/W R/W R/W R/W RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS Scrub Address Counter (Bits 15-8) This register reflects the current value in the Scrub Address counter bits 15-8.
Programming Model Error Logger Register ADR/SIZ BIT 1st $FFF4305C/2nd $FFF4315C (8-bits) 31 30 29 28 27 26 25 24 NAME ERRLOG ERD ESCRB ERA EALT 0 MBE SBE OPER R/C R R R R R R R RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS X 0 PLS 0 PLS 4 SBE SINGLE BIT ERROR is set when the last error logged was due to a single-bit error. It is cleared when a 1 is written to the ERRLOG bit. The syndrome code reflects the bit in error. (Refer to the Syndrome Decoding section.
MCECC Functions ERRLOG When set, ERRLOG indicates that a single- or a doublebit error has been logged by this MCECC and that no more will be logged until the error is cleared. The bit can only be set by logging an error and cleared by writing a 1 to it. When ERRLOG is cleared, the MCECC is ready to log a new error. Note that because hardware duplicates control register writes to both MCECCs, clearing ERRLOG in one MCECC sector clears it in the other.
Programming Model Error Address (Bits 15-8) This register reflects the value that was on bits 15-8 of the local MC680x0 address bus at the last logging of an error.
MCECC Functions Error Syndrome Register ADR/SIZ 4 1st $FFF43070/2nd $FFF43170 (16-bits) BIT 31 30 29 28 27 26 25 24 NAME 0 S6 S5 S4 S3 S2 S1 S0 OPER R R R R R R R R RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS S6-S0 Bits SYNDROME6-0 reflect the syndrome value at the last logging of an error. The seven-bit code indicates the position of the data error. When all the bits are 0, there is no error.
Programming Model RSIZ2 RSIZ1 RSIZ0 DRAM Array Size 0 0 0 4MB 0 0 1 8MB 0 1 0 16MB 0 1 1 32MB 1 0 0 64MB 1 0 1 128MB 1 1 0 Reserved 1 1 1 Reserved 4 The states of RSIZ2-0 after reset (power-up, soft, or local) match those of the RSIZ2-0 bits from the reset serial bit stream.
MCECC Functions being set. The state of FSTRD after a reset (power-up, soft, or local) is determined by board-level configuration resistors. 4 RWB6 Read/Write Bit 6 is a general-purpose read/write bit. RWB7 Read/Write Bit 7 is a general-purpose read/write bit.
Programming Model SDRAM Configuration Register ADR/SIZ 1st $FFF4307c/2nd $FFF4317c (8-bits) BIT 31 30 29 28 27 NAME 0 0 0 0 0 OPER R R R R R R R R RESET 0 PLS 0 PLS 0 PLS V PLS V PLS V PLS V PLS V PLS 26 25 24 SDCFG2 SDCFG1 SDCGF0 SDCFG2-SDCFG0 Define the physical SDRAM memory population on the printed circuit board: SDCFG2 SDCFG1 SDCFG0 DRAM Array Size 0 0 0 SDRAM device is 64MBit x 16 data with one bank composed of 3 devices 0 0 1 SDRAM device is 64MBit x 8
MCECC Functions Initialization Most DRAM vendors require that the DRAMs be subjected to some number of access cycles before the DRAMs are fully operational. The MCECC does not perform this initialization automatically, but depends on software to perform enough dummy accesses to DRAM to meet the requirement. The number of cycles required is fewer than 10. If there are multiple blocks of DRAM, software has to perform at least 10 accesses to each block. 4 The MCECC pair provides a fast zero-fill capability.
Programming Model 9. Ensure that the zero-fill stops after one pass by clearing the SCRBEN bit in the Scrub Control register. (Clear bit 27 of offset $24.) 10. Wait for the zero-fill to complete by waiting for the SCRB bit in the Scrub Control register to be cleared. (Wait for bit 28 of offset $24 = 0.) 11. Clear the ZFILL bit in the MCECC pair. (Clear Bit 28 of offset $20.) 12. The entire DRAM that is controlled by this MCECC is now zerofilled.
MCECC Functions Syndrome Decoding The following table defines the syndrome bit encoding for the Petra/MCECC ASIC. A syndrome code value of $00 indicates no error found. All other syndrome code values denote an error. The bit in error is decoded as shown in the table. 4 Table 4-4.
Syndrome Decoding Since the memory architecture is 32 data bits plus seven syndrome bits with a non-interleaved architecture, there is no corresponding entry for Bank in Error. The selection of the physical SDRAM bank is decoded from the address bus. Consequently, the Error Address register must be examined to determine which bank contains the error. Given a specific SDRAM configuration, the following table relates bits in the Error Address register to the physical bank where the error originated. .
MCECC Functions 4 4-38 Computer Group Literature Center Web Site
ASummary of Changes A Introduction This appendix summarizes the modifications that accompanied the introduction of the Petra ASIC on the MVME167P and MVME177P single-board computers. Differences in function and implementation between previous MVME167 and MVME177 models and the new MVME1x7P boards are listed in the following table.. Table A-1. List of Changes Function Previous Implementation MVME1x2P2 Implementation MCECC memory control MCECC ASIC, revision 00. Petra ASIC, revision 02 (page 3-12).
A Summary of Changes A-2 Computer Group Literature Center Web Site
BPrinter and Serial Port Connections B Introduction This appendix has connection diagrams for the printer port and the four serial ports on the MVME1X7P. These ports are connected to external devices through an MVME712M transition module. The configuration of the serial ports as Data Terminal Equipment (DTE) or Data Circuit-terminating Equipment (DCE) is accomplished by jumpers on the transition module. For more information, refer to the user’s manual for the MVME712M.
B-2 PDEN* PRFLT* PRPE PRBSY PRACK* PRSEL PRINP* PRSTB* PRWE* 9P F543 LS244 LS244 LS244 LS244 LS244 LS244 LS244 A A A A A A A A OEBA ENBA ENBA LEBA OEAB ENAB LEAB B B B B B B B B P2 ADAPTER BOARD 64 COND CABLE MVME712M 1347 9403 32 12 11 10 13 31 1 2 3 4 5 6 7 8 9 36 PIN RIBBON B SAD < 0 > SAD < 1 > SAD < 2 > SAD < 3 > SAD < 4 > SAD < 5 > SAD < 6 > SAD < 7 > PRRE* PCCCHIP2 MVME167P / MVME177P Printer and Serial Port Connections Figure B-1.
http://www.motorola.com/computer/literature CTS0* CD0* RXD0 DTR0* TXD0 CD2401 54 85 1.5K 34 55 39 R MC145406 R MC145406 D MC145406 D MC145406 MVME167P / MVME177P C26 C24 C25 C23 P2 ADAPTER BOARD 64 COND CABLE +12V +12V 1.5K 1.5K MVME712 TRANSITION BOARD 4 2 7 6 5 8 3 DB25 1348 9403 RTS TXD GND DSR CTS DCD RXD Connection Diagrams B Figure B-2.
B-4 CTS1* CD1* RXD1 DTR1* RTS1* TXD1 CD2401 58 11 35 59 60 40 R MC145406 R MC145406 R MC145406 D MC145406 D MC145406 D MC145406 MVME167P / MVME177P C30 C32 C28 C29 C31 C27 P2 ADAPTER BOARD 64 COND CABLE +12V 1.5K MVME712 TRANSITION BOARD 4 20 2 7 6 5 8 3 DB25 1349 9403 RTS DTR TXD GND DSR CTS DCD RXD Printer and Serial Port Connections B Figure B-3.
http://www.motorola.com/computer/literature CTS2* CD2* RXD2 DTR2* RTS2* TXD2 CD2401 63 18 36 64 65 41 R MC145406 R MC145406 R MC145406 D MC145406 D MC145406 D MC145406 MVME167P / MVME177P A22 A24 A20 A21 A23 A19 P2 ADAPTER BOARD 64 COND CABLE +12V 1.5K MVME712 TRANSITION BOARD 4 20 2 7 6 5 8 3 DB25 1350 9403 RTS DTR TXD GND DSR CTS DCD RXD Connection Diagrams B Figure B-4.
B-6 CTS3* CD3* RXD3 TXCI3 RXCI3 TXCO3 DTR3* RTS3* TXD3 CD2401 67 22 38 52 51 47 68 69 42 R MC145406 R MC145406 R MC145406 R MC145406 D MC145406 R MC145406 D MC145406 D MC145406 D MC145406 D MC145406 MVME167P / MVME177P 1 J7 1 J6 A29 A31 A26 A28 A32 A27 A30 A25 P2 ADAPTER BOARD 64 COND CABLE RTXC4 TRXC4 1 J15 +12V 1.
http://www.motorola.com/computer/literature CTS0* CD0* RXD0 DTR0* TXD0 CD2401 54 85 1.5K 34 55 39 R MC145406 9P R MC145406 D MC145406 D MC145406 MVME167P / MVME177P C26 C24 C25 C23 P2 ADAPTER BOARD 64 COND CABLE +12V 1.5K MVME712 TRANSITION BOARD 5 3 7 4 20 2 DB25 1352 9403 CTS RXD GND RTS DTR TXD Connection Diagrams B Figure B-6.
B-8 CTS1* CD1* RXD1 DTR1* RTS1* TXD1 CD2401 58 11 35 59 60 40 R MC145406 R 11P MC145406 R MC145406 D MC145406 D MC145406 D MC145406 MVME167P / MVME177P C30 C32 C28 C29 C31 C27 P2 ADAPTER BOARD 64 COND CABLE MVME712 TRANSITION BOARD 5 8 3 7 4 20 2 DB25 1353 9403 CTS DCD RXD GND RTS DTR TXD Printer and Serial Port Connections B Figure B-7.
http://www.motorola.com/computer/literature CTS2* CD2* RXD2 DTR2* RTS2* TXD2 CD2401 63 18 36 64 65 41 R MC145406 R 9P MC145406 R MC145406 D MC145406 D MC145406 D MC145406 MVME167P / MVME177P A22 A24 A20 A21 A23 A19 P2 ADAPTER BOARD 64 COND CABLE MVME712 TRANSITION BOARD 5 8 3 7 4 20 2 DB25 1354 9403 CTS DCD RXD GND RTS DTR TXD Connection Diagrams B Figure B-8.
B-10 CTS3* CD3* RXD3 TXCI3 RXCI3 TXCO3 DTR3* RTS3* TXD3 CD2401 67 22 38 52 51 47 68 69 42 R MC145406 R MC145406 R MC145406 R MC145406 D MC145406 R MC145406 D MC145406 D MC145406 D MC145406 D MC145406 MVME167P / MVME177P 1 J7 1 J6 A29 A31 A26 A28 A32 A27 A30 A25 P2 ADAPTER BOARD 64 COND CABLE RTXC4 TRXC4 1 J15 MVME712 TRANSITION BOARD 5 8 3 7 24 17 15 4 20 2 DB25 1355 9403 CTS DCD RXD GND TTXC RRXC RTXC RTS DTR TXD Printer and Se
CRelated Documentation C MCG Documents The Motorola Computer Group publications listed below are referenced in this manual. You can obtain paper or electronic copies of MCG publications by: ❏ Contacting your local Motorola sales office ❏ Visiting MCG’s World Wide Web literature site, http://www.motorola.com/computer/literature .. Table C-1.
Related Documentation Manufacturers’ Documents For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As a further help, sources for the listed documents are also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice. C Table C-2.
Related Specifications Table C-2. Manufacturers’ Documents (Continued) Document Title and Source Z85230 Serial Communications Controller Product Brief Zilog Inc. 210 Hacienda Avenue Campbell, CA 95008-6609 Web: http://www.zilog.com/products Publication Number C Z85230pb.pdf Related Specifications For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As a further help, sources for the listed documents are also provided.
Related Documentation Table C-3. Related Specifications (Continued) Publication Number Document Title and Source C OR Microprocessor system bus for 1 to 4 byte data Bureau Central de la Commission Electrotechnique Internationale 3, rue de Varembé Geneva, Switzerland IEC 821 BUS ANSI Small Computer System Interface-2 (SCSI-2), Draft Document X3.131198X, Revision 10c Global Engineering Documents 15 Inverness Way East Englewood, CO 80112-5704 X3.131-198X Rev.
Index Numerics 53C710 SCSI controller 1-15, 3-6 82596CA LAN coprocessor 1-14, 3-3 LAN coprocessor memory map 1-40 LANC Interrupt Control Register 3-35 A A16/D16 space, VMEbus 2-37 A16/D16 space, VMEchip2 ASIC 2-6 A16/D32 space, VMEbus 2-37 A16/D32 space, VMEchip2 ASIC 2-6 A24/D16 space, VMEbus 2-37, 2-51 A24/D16 space, VMEchip2 ASIC 2-6 A32/D16 space, VMEbus 2-37, 2-51 A32/D16 space, VMEchip2 ASIC 2-6 ABORT switch interrupt, address 1-18 AC Fail interrupter, VMEbus 2-19 access cycles, VMEbus 2-33 access t
Index B I N D E X Back Off signal (PCCchip2 ASIC) 3-5 backward compatibility 1-2 base address, VMEchip2 LCSR 2-20 battery backup 1-10 BBRAM configuration area memory map 1-42 interface, PCCchip2 3-3 memory map 1-41 speed control 3-15 BBRAM (battery-backed-up RAM) 1-12 restoring lost Ethernet address 1-15 BBSY* signal, VMEbus 2-98 BERR* signal, VMEbus 2-17 BGIN filters, VMEbus 2-98 binary number, symbol for xxiii block (D64) access cycles, VMEbus 2-33, 2-36 block access cycles, VMEbus 2-33, 2-36 block dia
clear-on-compare mode, VMEchip2 counters 2-15 clocks for VMEchip2 counters and timers 2-67 command chaining mode, VMEchip2 DMAC 2-12, 2-52 command packets, DMAC 2-52 compatibility, backward 1-2 connection diagrams printer and serial port B-1 transition module B-1 Control and Status registers (CSRs), PCCchip2 ASIC 3-11 memory map 3-12 counter enable tick timer 1 3-23 tick timer 2 3-22 cycle types, MCECC sector 4-5 D data access cycles, VMEbus 2-33, 2-36 data bus structure 1-7 data sheets, sources of C-2 dat
Index E I N D E X ECC (error-correcting code) 4-5 edge/level-sensitive interrupt, GPIO 3-24 LANC 3-35 printer acknowledge 3-39 printer busy 3-43 printer fault 3-40 printer paper error 3-42 printer select 3-41 edge-sensitive interrupters, VMEbus 2-19 edge-sensitive interrupts, VMEchip2 ASIC 2-74 EIA-232-D drivers/receivers 1-13 ending address register (VMEbus slave) 2-38 ending address register, slave map decoder 2-27 EPROM 1-8 addresses 1-21 socket 1-3 errata sheets, obtaining 1-25 error conditions, desc
ID register, VMEchip2 2-104 VMEchip2 Board Status/Control register 2-106 VMEchip2 ID register 2-104 VMEchip2 LM/SIG register 2-104 VMEchip2 Revision register 2-103 GPI inputs, addresses 1-18 GPIO pin (PCCchip2 ASIC) 3-25 GPIO pin drive (PCCchip2 ASIC) 3-25 GPIO pin logic (PCCchip2 ASIC) 3-25 group address, GCSR 2-47 H hexadecimal number, symbol for xxiii I I/O interfaces 1-3 I/O map decoders 2-6, 2-37, 2-39 I/O memory maps 1-25 i486-bus interface 3-4 IACK cycle, VMEbus 2-20 IACK daisy-chain driver, VMEbus
Index I N D E X Interrupt Priority Level register (PCCchip2 ASIC) 3-48 interrupt sources PCCchip2 VBR 3-17 VMEchip2 ASIC 2-18 interrupt status GPIO 3-24 LANC bus error 3-36 LANC interrupt 3-35 printer acknowledge 3-39 printer busy 3-43 printer fault 3-40 printer input 3-44 printer paper error 3-42 printer select 3-41 SCC modem 3-28 SCC receive 3-30 SCC transmit 3-29 SCSI processor 3-38 tick timer 1 3-26 tick timer 2 3-26 interrupt status bit 2-77 Interrupt Vector Base register (PCCchip2 ASIC) 3-16 interru
local bus interrupter registers I/O Control register 1 2-96 I/O Control register 2 2-97 I/O Control register 3 2-97 Interrupt Level register 4 (bits 0-7) 2-95 Miscellaneous Control register 2-98 Status register (bits 16-23) 2-78 Status register (bits 24-31) 2-77 Vector Base register 2-95 local bus master 2-9 VMEbus and 2-10 local bus slave (VMEbus master) registers Address Translation Address Register 4 2-42 Address Translation Select Register 4 2-42 Attribute Register 1 2-46 Attribute Register 2 2-45 Attri
Index I N D E X Defaults register 2 4-32 DRAM Control register 4-15 Error Address (bits 23-16) 4-28 Error Address (bits 31-24) 4-28 Error Address (bits 7-4) 4-29 Error Address Bits (15-8) 4-29 Error Logger register 4-27 Error Syndrome register 4-30 features 4-1 initialization 4-34 internal register memory map 4-11 Memory Configuration register 4-14 refresh control 4-8 Scrub Address counter (bits 15-8) 4-26 Scrub Address counter (bits 23-16) 4-26 Scrub Address counter (bits 26-24) 4-25 Scrub Address counte
non-privileged access cycles, VMEbus 2-34, 2-37 Non-Volatile RAM (NVRAM) 1-3 memory map 1-41 see BBRAM 1-41 O overflow counter output tick timer 1 3-23 tick timer 2 3-22 overflow counter, VMEchip2 ASIC 2-72, 2-73 P P2 connector and Ethernet station address 1-15 parallel port interface (PCCchip2 ASIC) 3-6 parallel printer port 1-14 PCCchip2 ASIC 82596CA LAN controller interface 3-3 BBRAM interface 3-3 block diagram 3-2 CD2401 SCC interface 3-7 Chip ID register 3-15 Chip Revision register 3-14 features 3-1
Index I N D E X Printer Input Status register (PCCchip2 ASIC) 3-44 Printer PE Interrupt Control register (PCCchip2 ASIC) 3-42 printer port connection MVME1X7P, MVME712M B-2, B-3, B-4, B-5, B-6, B-7, B-8, B-9, B-10 printer port connection diagrams B-1 Printer Port Control register (PCCchip2 ASIC) 3-45 Printer SEL Interrupt Control register 3-41 Priority (PRI) arbitration mode, VMEbus 2-17 processor-to-VMEbus transfers 1-12 program access cycles, VMEbus 2-33, 2-36 program address modifier code (VMEbus) 2-50
SCC Receive Interrupt Control register (PCCchip2 ASIC) 3-30 SCC Transmit Interrupt Control register (PCCchip2 ASIC) 3-29 scrub cycle type 4-7 SCSI controller interface (PCCchip2 ASIC) 3-6 Error Status register (PCCchip2 ASIC) 3-37 ID (see local SCSI ID) 1-45 interface 1-16 Interrupt Control register (PCCchip2 ASIC) 3-38 LTO error 1-63 memory map 1-41 offboard error 1-62 parity error 1-62 terminator configuration 1-16 SDRAM implementation 1-2, 4-1, 4-5 map decoder 1-11 segment size, address translation 2-31
Index T I N D E X TEA source 3-34 Tick Timer 1 Compare register 3-18 Tick Timer 1 Control register (PCCchip2 ASIC) 3-23 Tick Timer 1 counter (PCCchip2 ASIC) 3-19 Tick Timer 1 Interrupt Control register (PCCchip2 ASIC) 3-26 Tick Timer 2 Compare register (PCCchip2 ASIC) 3-19 Tick Timer 2 Control register (PCCchip2 ASIC) 3-22 Tick Timer 2 counter (PCCchip2 ASIC) 3-20 Tick Timer 2 Interrupt Control register (PCCchip2 ASIC) 3-25 tick timer interrupters 2-19 tick timers 1-3, 1-16 PCCchip2 ASIC 3-9, 3-18 VMEchi
slave 2-9 slave map decoders 2-26 slave map decoders, programming 2-26 system controller function 2-17 timer 2-18 VMEbus Slave registers Address Modifier Select Register 1 2-36 Address Modifier Select Register 2 2-33 Address Translation Address Offset Register 1 2-29 Address Translation Address Offset Register 2 2-31 Address Translation Select Register 1 2-30 Address Translation Select Register 2 2-31 Ending Address Register 1 2-28 Ending Address Register 2 2-29 GCSR Board Address Register 2-48 GCSR Group A
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