Embedded Computing for Business-Critical ContinuityTM CPCI-6200 Installation and Use P/N: 6806800J66C August 2011
© 2011 Emerson All rights reserved. Trademarks Emerson, Business-Critical Continuity, Emerson Network Power and the Emerson Network Power logo are trademarks and service marks of Emerson Electric Co. © 2011 Emerson Electric Co. All other product or service names are the property of their respective owners. Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.
Contents About this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1 1.2 1.3 1.4 1.5 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Contents 3.4 3.5 3.6 4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1 4.2 4.3 4.4 4.5 4 3.3.1 CPCI Bus Connector, J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3.2 CPCI Bus Connector, J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.3.
Contents 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 5 Ethernet Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Local Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.7.1 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.8 6 Control via IPMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.1 6.2 6.3 6.4 6.5 6 MOTLoad Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 MOTLoad Implementation and Memory Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents 7 Memory Maps and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 7.1 7.2 7.3 7.4 Default Processor Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 CPCI-6200 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Local Bus Controller Memory Map . . . . . . . . . . . .
Contents Contents 7.5 7.6 7.7 A Replacing the Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 A.1 A.2 B 7.4.27.4 Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 I2C Device Addresses . . .
List of Tables Table 1-1 Table 1-2 Table 1-3 Table 2-1 Table 2-2 Table 2-3 Table 2-4 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 5-1 Table 6-1 Table 6-2 Table 6-3 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 6-4 Table 6-5 Table 6-6 Table 6-7 Table 6-8 Table 6-9 Table 6-10 Table 6-11 Table 6-12 Table 6-13 Table 6-14 Table 6-15 Table 6-16 Table 6-17 Table 6-18 Table 6-19 Table 6-20 Table 6-21 Table 6-22 Table 6-23 Table 6-24 Table 6-25 Table 6-26 Table 6-27 Table 6-28 Table 6-29 Table 6-30 Table 6-31 Table 6-32 Table 6-33 Table 6-34 Table 6-35 Table 6-36 Table 6-37 Table 6-38 Table 6-39 10 Supported SEL Device Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 6-40 Table 7-1 Table 7-2 Table 7-3 Table 7-4 Table 7-5 Table 7-6 Table 7-7 Table 7-8 Table 7-9 Table 7-10 Table 7-11 Table 7-12 Table 7-13 Table 7-14 Table 7-15 Table 7-16 Table 7-17 Table 7-18 Table 7-19 Table 7-20 Table 7-21 Table 7-22 Table 7-23 Table 7-24 Table 7-25 Table 7-26 Table 7-27 Table 7-28 Table 7-29 Table 7-30 Table 7-31 Table 7-32 Table 7-33 Table 7-34 Table 7-35 VPCore Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 7-36 Table 7-37 Table 7-38 Table 7-39 Table 7-40 Table 7-41 Table 7-42 Table 7-43 Table 7-44 Table 7-45 Table 7-46 Table 7-47 Table 7-48 Table 7-49 Table 7-50 Table 7-51 Table 7-52 Table 7-53 Table 7-54 Table 7-55 Table 7-56 Table 7-57 Table 7-58 Table 7-59 Table 7-60 Table 7-61 Table 7-62 Table B-1 Table B-2 Table B-3 12 NAND Flash Chip 2 Status Register Field Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 CPCI Control/Status Register, 0xF200_0018 . . . . .
List of Figures Figure 1-1 Figure 1-2 Figure 2-1 Figure 3-1 Figure 3-2 Figure 3-3 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 7-1 Figure 7-2 Declaration of Conformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Location of the Product Serial Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Location of Configuration Switches . . . . . . . . . . . . . . . . .
List of Figures 14 CPCI-6200 Installation and Use (6806800J66C)
About this Manual Overview of Contents This manual is divided into the following chapters and appendices. Introduction provides an overview of the features of the product, including ordering and other product information like the location of labels. Hardware Preparation and Installation discusses procedures on installing the CPCI baseboard, PMC modules, and other accessories. Controls, LEDs, and Connectors provides information on connector pinouts and board and front panel layouts.
About this Manual About this Manual 16 Abbreviation Definition CPCI Compact PCI CPLD Complex Programmable Logic Device COP Common On-Chip Processor CRC Cyclic Redundancy Check DDR Double Data Rate DIMM Dual Inline Memory Module DMA Direct Memory Access DRAM Dynamic Random Access Memory DUART Dual Universal Asynchronous Receiver/Transmitter ECC Error Correction Code EEPROM Electrically Erasable Programmable Read-Only Memory EPROM Erasable Programmable Read-Only Memory ESD Electro
About this Manual Abbreviation Definition MRAM Magnetoresistive Random Access Memory MSB Most Significant Byte Msb Most Significant Bit NEBS Network Equipment Building System NVRAM Non-Volatile Random Access Memory PCI Peripheral Component Interconnect PCIe or PCI-E Peripheral Component Interconnect Express PCI-X Peripheral Component Interconnect -X PHY Physical Interface PIC Programmable Interrupt Controller PIM PCI Mezzanine Card Input/Output Module PICMG PCI Industrial Computer
About this Manual About this Manual Abbreviation Definition SPD Serial Presence Detect SRAM Static Random Access Memory TSEC Three-Speed Ethernet Controller UART Universal Asynchronous Receiver/Transmitter VIO Input/Output Voltage VME Versa Module Eurocard VPD Vital Product Data Conventions The following table describes the conventions used throughout this manual.
About this Manual Notation Description . Omission of information from example/command that is not necessary at the time being . . .. Ranges, for example: 0..4 means one of the integers 0,1,2,3, and 4 (used in registers) | Logical OR Indicates a hazardous situation which, if not avoided, could result in death or serious injury Indicates a hazardous situation which, if not avoided, may result in minor or moderate injury Indicates a property damage message No danger encountered.
About this Manual About this Manual 20 CPCI-6200 Installation and Use (6806800J66C)
Chapter 1 Introduction 1.1 Features The CPCI-6200 is a high performance, hot swappable universal Compact PCI board based on the MPC8572 integrated processor. Table 1-1 Summary of Features Function Features Processor Host Controller Memory Controller One 8572 integrated processor Two e500 cores with integrated 1 MB L2 cache 32 KB data and instruction cache on each core Core frequency from 1.3 to 1.
Introduction Table 1-1 Summary of Features (continued) Function Features NVRAM One 512 KB MRAM PCI Express 4x port to PCI Express expansion 4x port to 6-port PCI Express switch for PCI Express interface One mini DB9 connector on the face plate (one serial channel) Two RJ-45 connectors on the face plate with integrated LEDs for two 10/100/1000 Ethernet channels Two 10/100/1000 Ethernet chanels for rear J3 I/O One USB 2.
Introduction Table 1-1 Summary of Features (continued) Function Features Others One RESET/ABORT switch on the face plate User/Fail LED on the face plate Blue hot swap LED on the face plate One standard 16-pin JTAG/COP header Support for boundary scan VxWorks Linux Software Support RTM CPCI-6200 Installation and Use (6806800J66C) Compatible with RTM-CPCI-6115 (01-W3766F11A) 23
Introduction 1.2 Standard Compliances The CPCI-6200 is designed to be CE compliant and to meet the following standard requirements. Standard Description UL 60950-1 Safety Requirements (legal) EN 60950-1 IEC 60950-1 CAN/CSA C22.
Introduction Figure 1-1 Declaration of Conformity CPCI-6200 Installation and Use (6806800J66C) 25
Introduction 1.3 Mechanical Data The CPCI-6200 is a full 6U 18-layer board. It is designed with ruggedization holes to support ruggedization application. This board occupies a single CPCI card slot with PMC modules installed. 1.4 Ordering Information Use the information in the following sections when ordering boards and accessories. 1.4.1 Supported Board Models Table 1-2 Order Numbers for Baseboard Variants 1.4.2 Marketing Number Description CPCI6200-13-2G MPC8572, 1.
Introduction 1.
Introduction 28 CPCI-6200 Installation and Use (6806800J66C)
Chapter 2 Hardware Preparation and Installation 2.1 Overview This chapter provides instructions on preparing and installing the CompactPCI board. A fully implemented CPCI-6200 consists of the baseboard, PMC modules, and an optional rear transition module. 2.2 Unpacking the CPCI Baseboard 1. Make sure that you receive all items of your shipment: Printed Quick Start Guide and Safety Notes CPCI-6200 baseboard Optional items that were ordered 2.
Hardware Preparation and Installation 2.3 Environmental Requirements The environmental conditions must be tested and proven in the used system configuration. These conditions refer to the surroundings of the board within the user environment. Operating temperatures refer to the temperature of the air circulating around the board and not to the component temperature. To ensure that the operating conditions are met, forced air cooling is required within the shelf environment.
Hardware Preparation and Installation Table 2-1 CPCI-6200 Environmental Requirements (continued) Characteristics Operating Non-Operating Shock Half-sine, 11 ms, 30 ms Blade-level packaging Half-sine, 6 ms at 180 ms Free Fall 2.4 Blade-level packaging 100 mm (unpackaged) per GR-63CORE Power Requirements The board's power requirements depend on the installed hardware accessories. The following table gives examples of typical power requirements for a processor running without any accessories.
Hardware Preparation and Installation 2.5 Installing Accessories 2.5.1 Installing a PMC Module on the CPCI Baseboard One double-width or two single-width PCI mezzanine cards (PMC) can be mounted on the CPCI-6200 baseboard. Each PMC slot has four connectors that provide a PCI interface to two PMC slots that provide user I/O to the backplane. Damage of Circuits Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life.
Hardware Preparation and Installation 4. Remove the PMC filler plate from the front panel of CPCI-6200. PMC Alignment PMC Filler Plate Voltage Key 5. Make sure that hole on the PMC matches the voltage key on CPCI-6200. Do not remove the PMC voltage key. CPCI-6200 supports only 3.3 V I/O PMC modules. 6. Slide the edge connector of the PMC module into the front panel opening from behind, and then place the PMC module on top of the baseboard.
Hardware Preparation and Installation The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors (J11/12/13/14) or (J21/22/23/24) on CPCI-6200. 7. Insert the four short Phillips screws, provided with the PMC, through the holes on the bottom side of CPCI-6200 and into the PMC front bezel and rear standoffs, and then tighten the screws. 2.5.
Hardware Preparation and Installation Perform the following steps before you install your board into the CompactPCI backplane to prevent possible backplane pin damage. 1. Inspect the board connectors to ensure that they are not damaged by previous insertions or accidental mishandling. If any connector is damaged, do not install the board into the backplane to prevent the bending of pins. 2. Inspect the slot where the board will be installed for any bent pins on the backplane. 2.6.
Hardware Preparation and Installation Switches are used to control options that are not software configurable. The switch settings are described in the succeeding sections. Figure 2-1 Location of Configuration Switches Board Configuration Switch, S1 IPMI Configuration Switch, S2 2.6.3.1 Board Configuration Switch, S1 The CPCI-6200 uses an 8-position SMT configuration switch to: 36 Control the flash bank write-protect. Select the flash boot image. Control the safe start ENV settings.
Hardware Preparation and Installation The default switch position is OFF.
Hardware Preparation and Installation When the SA_MODE switch is OFF, board operation is normal. When the switch is ON, the board operates in stand-alone mode i.e., it operates in a peripheral slot without the system board in the chassis. When the LRO_SW switch is OFF, if the board is placed in reset, it is only a local reset. When the switch in ON, the board reset is propagated to CPCI bus. For more information, see Reset Control Logic on page 87.
Hardware Preparation and Installation When the IPMI_MODE_1 and IPMI_MODE_2 switches are OFF, the IPMI controller operates normally. When both switches are ON, the IPMI controller enters programming mode. Any other switch setting is not supported and treated as reserved. When the IPMI_SYSEN switch is OFF, the IPMI operates in non-system mode. When the switch is ON, IPMI operates in system mode. When the FORCE_PM switch is OFF, the IPMI operates in non-peripheral management mode.
Hardware Preparation and Installation 5. Remove the filler panel from the appropriate card slot. 6. Set the VIO on the backplane to either +3.3 V or +5 V, depending on your CompactPCI system signaling requirements, and ensure the backplane does not bus J3 or J5 signals. 7. Slide the baseboard into the appropriate slot. Grasping the top and bottom injector handles, be sure the module is well seated in the P1 through P5 connectors on the backplane. Make sure you do not damage or bend connector pins. 8.
Hardware Preparation and Installation 2.8 Removing the CPCI Baseboard The board is fully compliant to Compact PCI Hot Swap Specification PICMG 2.1 R2.0, and can run in both 3.3 V and 5 V Compact PCI systems. Data Loss Removing the RTM with the system power on and the blue LED on the front blade still flashing causes data loss.
Hardware Preparation and Installation 4. Wait until blue hot swap LED lights up. Data Loss Removing the product with the blue LED still blinking causes data loss. Wait until the blue LED is permanently illuminated before removing the product. 5. Remove the board from the slot by fully opening the ejector handles. 2.9 Connecting to a Console Port When the CPCI-6200 is installed in the chassis, you are ready to connect peripherals and apply power to the board.
Hardware Preparation and Installation The image should boot to the following prompt: Emerson Network Power Embedded Computing Linux Kernel 2.6.29.6 on a 2-processor CPCI6200 localhost login: Login as root with no password. If you want to use IPMI, load the IPMI SMBus driver using: # modprobe ipmi_smb Contact Emerson for kernel patches and additional information on using Linux on the CPCI6200.
Hardware Preparation and Installation 44 CPCI-6200 Installation and Use (6806800J66C)
Chapter 3 Controls, LEDs, and Connectors 3.
Controls, LEDs, and Connectors 3.2 Front Panel For more information on the front panel connectors, see Front Panel LEDs on page 67.
Controls, LEDs, and Connectors 3.
Controls, LEDs, and Connectors Table 3-1 Onboard Connectors (continued) Reference Designator Function P6 Processor COP header Planar header for processor COP emulation P7 Planar header for debugging the PCI Express switch device XJ1, XJ2 DDR3 DIMM 1 and 2 Socket 204-pin SO-UDIMM socket for DDR3 DIMM 3.3.1 S1 8-position switch S2 8-position switch for IPMI functionality CPCI Bus Connector, J1 J1 is a five-row CPCI bus connector.
Controls, LEDs, and Connectors Table 3-2 CPCI Bus Connector Pinout, J1 (continued) 3.3.2 Pin Row A Row B Row C Row D Row E 9 C/BE[3]# IDSEL AD[23] GND1 AD[22] 8 AD[26] GND V(IO) AD[25] AD[24] 7 AD[30] AD[29] AD[28] GND1 AD[27] 6 REQ# GND +3.3 V1 CLK AD[31] 5 BRSVR1A5 BRSVR1B5 RST# GND1 GNT# 4 IPMB_PWR HEALTHY# V(IO)1 INTP INTS 3 INTA# INTB# INTC# +5.0 V1 INTD# 2 TCK +5.0 V TMS TDO TDI 1 +5.0 V -12 V TRST# +12 V +5.
Controls, LEDs, and Connectors Table 3-3 CPCI Bus Connector Pinout, J2 (continued) Pin Row A Row B Row C Row D Row E 10 AD[49] AD[48] AD[47] GND AD[46] 9 AD[52] GND V(IO) AD[51] AD[50] 8 AD[56] AD[55] AD[54] GND AD[53] 7 AD[59] GND V(IO) AD[58] AD[57] 6 AD[63] AD[62] AD[61] GND AD[60] 5 C/BE[5]# 64EN# V(IO) C/BE[4]# PAR64 4 V(IO) BRSVP2B4 C/BE[7]# GND C/BE[6]# 3 RSV GND RSV RSV RSV 1 2 RSV RSV SYSEN# RSV RSV 1 RSV GND RSV RSV RSV 1.
Controls, LEDs, and Connectors Table 3-4 CPCI User I/O Connector Pinout, J3 (continued) Pin Row A Row B Row C Row D Row E 9 PMCIO25 PMCIO24 PMCIO23 PMCIO22 PMCIO21 10 PMCIO20 PMCIO19 PMCIO18 PMCIO17 PMCIO16 11 PMCIO15 PMCIO14 PMCIO13 PMCIO12 PMCIO11 12 PMCIO10 PMCIO9 PMCIO8 PMCIO7 PMCIO6 13 PMCIO5 PMCIO4 PMCIO3 PMCIO2 PMCIO1 14 +3.3V +3.3V +3.
Controls, LEDs, and Connectors Row F is ground and is not shown in the table. Table 3-5 CPCI User I/O Connector Pinout, J5 3.3.
Controls, LEDs, and Connectors Connectors J11, J12, J13 and J14 are used for PMC1 while J21, J22, J23 and J24 are used for PMC2. Table 3-6 PMC Connector Pinout, J11/J21 Pin J11/J21 Pin 1 TCK -12 V 2 3 GND INTA# 4 5 INTB# INTC# 6 7 PRESENT# +5 V 8 9 INTD# PCI_RSVD 10 11 GND NC (+3.
Controls, LEDs, and Connectors Table 3-6 PMC Connector Pinout, J11/J21 (continued) Pin J11/J21 Pin 51 GND C/BE0# 52 53 AD06 AD05 54 55 AD04 GND 56 57 VIO AD03 58 59 AD02 AD01 60 61 AD00 +5 V 62 63 GND REQ64# 64 Table 3-7 PMC Connector Pinout, J12/J22 54 Pin J12 J22 Pin 1 +12 V TRST# 2 3 TMS TDO 4 5 TDI GND 6 7 GND PCI_RSVD 8 9 PCI_RSVD PCI_RSVD 10 11 MOT_RSVD +3.3 V 12 13 RST# MOT_RSVD 14 15 +3.
Controls, LEDs, and Connectors Table 3-7 PMC Connector Pinout, J12/J22 (continued) Pin J12 J22 Pin 35 TRDY# +3.3 V 36 37 GND STOP# 38 39 PERR# GND 40 41 +3.3 V SERR# 42 43 C/BE1# GND 44 45 AD14 AD13 46 47 M66EN AD10 48 49 AD08 +3.3 V 50 51 AD07 REQB_L 52 53 +3.3 V GNTB_L 54 55 MOT_RSVD GND 56 57 MOT_RSVD EREADY 58 59 GND NC (RESETOUT_L) 60 61 ACK64# +3.
Controls, LEDs, and Connectors Table 3-8 PMC Connector Pinout, J13/J23 (continued) Pin J13/J23 Pin 19 AD57 GND 20 21 VIO AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 VIO AD32 58 59 PCI_RSVD PCI_RSVD
Controls, LEDs, and Connectors Table 3-9 PMC Connector Pin Assignments , J14/J24 (continued) Pin J14/J24 Pin 3 PMCIO3 PMCIO4 4 5 PMCIO5 PMCIO6 6 7 PMCIO7 PMCIO8 8 9 PMCIO9 PMCIO10 10 11 PMCIO11 PMCIO12 12 13 PMCIO13 PMCIO14 14 15 PMCIO15 PMCIO16 16 17 PMCIO17 PMCIO18 18 19 PMCIO19 PMCIO20 20 21 PMCIO21 PMCIO22 22 23 PMCIO23 PMCIO24 24 25 PMCIO25 PMCIO26 26 27 PMCIO27 PMCIO28 28 29 PMCIO29 PMCIO30 30 31 PMCIO31 PMCIO32 32 33 PMCIO33 PMCIO34 3
Controls, LEDs, and Connectors Table 3-9 PMC Connector Pin Assignments , J14/J24 (continued) Pin 3.3.7 J14/J24 Pin 57 PMCIO57 PMCIO58 58 59 PMCIO59 PMCIO60 60 61 PMCIO61 PMCIO62 62 63 PMCIO63 PMCIO64 64 Ethernet Connector There are two Ethernet ports on the front panel through a single connector J6. J6 is a single housing with two RJ-45 ports. The pin configuration is based on IEEE standards 802.3ab-1999. 3.3.
Controls, LEDs, and Connectors 3.3.9 Serial Port Connector, J16 The serial port connector (COM1) is located on the front panel. Figure 3-3 1 2 3 4 5 Serial Port Connector Pinout, J16 Not Connected RXD TXD Not Connected GND 1 6 Not Connected 9 5 RTS# CTS# Not Connected 6 7 8 9 Note: G1 and G2 are connected to ground. 3.3.10 Board Insertion/Extraction Connector, P1 A board insertion and extraction connector is located near the front panel.
Controls, LEDs, and Connectors 3.3.11 DDR3 SO-DIMM Connectors, XJ1 and XJ2 The CPCI-6200 provides two 204-pin DDR3 SO-UDIMM connectors for installing DDR3 SDRAMs.
Controls, LEDs, and Connectors Table 3-11 DDR3 SO-DIMMs Pinout, XJ1 and XJ2 (continued) Pin Number Signal Pin Number Signal Pin Number Signal Pin Number Signal 47 VSS 48 DQ22 149 VSS 150 DQ45 49 DQ18 50 DQ23 151 DQ40 152 VSS 51 DQ19 52 VSS 153 DQ41 154 DQS5# 53 VSS 54 DQ28 155 VSS 156 DQS5 55 DQ24 56 DQ29 157 DM5 158 VSS 57 DQ25 58 VSS 159 DQ42 160 DQ46 59 DM3 60 DQS3# 161 DQ43 162 DQ47 61 VSS 62 DQS3 163 VSS 164 VSS 63 DQ26 64 VSS
Controls, LEDs, and Connectors Table 3-11 DDR3 SO-DIMMs Pinout, XJ1 and XJ2 (continued) Pin Number Signal Pin Number Signal Pin Number Signal Pin Number Signal 101 VDD 102 VDD 203 VTT 204 VTT 3.3.12 PCI Express Expansion Connector, J17 The CPCI-6200 provides PCI Express expansion capability through 76-pin Mictor connector.
Controls, LEDs, and Connectors Table 3-12 PCI Express Expansion Connector Pinout, J17 Pin Number Signal Pin Number Signal 41 NC 42 NC 43 NC 44 NC 45 GND 46 GND 47 NC 48 NC 49 NC 50 NC 51 GND 52 GND 53 NC 54 NC 55 NC 56 NC 57 GND 58 GND 59 NC 60 NC 61 NC 62 NC 63 GND 64 GND 65 NC 66 NC 67 NC 68 NC 69 TDI 70 TDO 71 TRST# 72 I2C_CLK 73 TMS 74 I2C_DATA 75 TCK 76 PRESENT# G1 GND G2 GND G3 GND G4 GND G5 GND G6 GND G7 GND G8
Controls, LEDs, and Connectors 3.3.13 IPMI Debug and FW Programming Header, P3 The CPCI-6200 provides one 4-pin planar header connected to IPMI serial port 2 for debugging and programming IPMI firmware. Table 3-13 IPMI Debug Pinout, P3 Pin Number Signal 1 TXD 2 GND 3 RXD 4 GND 3.3.14 Processor Debug Header, P4 The CPCI-6200 has a 10-pin header for debugging. This header can debug a DDR or LBC interface.
Controls, LEDs, and Connectors 3.3.15 Boundary Scan Header, P5 The CPCI-6200 uses a standard 20-pin boundary scan port header that provides an interface for programming the onboard PLDs, and boundary scan testing and debugging. Table 3-15 Boundary Scan Header Pinout, P5 Pin Number Signal Signal Pin Number 1 TCK GND 2 3 TDO GND 4 5 TMS GND 6 7 TRST# GND 8 9 TDI BSCAN_EN# 10 11 Key (no pin) NC 12 13 GND BSCAN_AW# 14 15 GND NC 16 17 GND NC 18 19 GND NC 20 3.3.
Controls, LEDs, and Connectors Table 3-16 COP Header Pinout, P6 (continued) Pin Number Signal Signal Pin Number 15 CPU_CKSTPO# GND 16 3.3.17 PCI Express Switch Header, P7 There is one standard 10-pin header located on the CPCI-6200 that provides the debug capability of the PCI Express device PLX8624 using the I2C bus. The connector connects to the Aardvark I2C/SPI Host Adapter. This header is only used for prototype debugging and is not installed in the released product.
Controls, LEDs, and Connectors 3.4.2 Reset/Abort Switch, P2 There is one push button switch located on the front panel that provides access to board reset and abort function. Table 3-18 Front Panel Reset Switch Pinout, P2 Pin Number Signal 1 FP_SWITCH 2 GND This is a multifunction switch. When the switch is pushed for one to three seconds, an abort is issued. When switch is pushed for five or more seconds, it is treated as reset function. 3.
Controls, LEDs, and Connectors 3.6 Status Indicators The CPCI-6200 provides four front panel status indicators as well as multiple planar status indicators that are used for general board function status and Ethernet link/speed/activity status. Table 3-19 CPCI-6200 Status Indicators Function Location Label Color Description Board Fail/User 1 Front panel User / Fail Orange This indicator lights up during a hard reset and remains lit until software turns it off.
Controls, LEDs, and Connectors Table 3-19 CPCI-6200 Status Indicators (continued) Function Location TSEC4 Link/Speed Onboard TSEC4 Activity Onboard Label Color Description Yellow - D30 Off No link Green - D29 Yellow 10/100 BASE-T operation Green 1000 BASE-T operation Off No activity Blinking Green Activity is proportional to bandwidth utilization.
Controls, LEDs, and Connectors 70 CPCI-6200 Installation and Use (6806800J66C)
Chapter 4 Functional Description 4.1 Overview The CPCI-6200 is based on Freescale’s MPC8572 integrated processor. CPCI-6200 provides the following: A USB 2.0 interface Compact PCI interfaces Dual 32—64 bit/33—133 MHz PCI/PCI-X PMC sites 128 MB of NOR flash and up to 8 GB of NAND flash Up to 4 GB of DDR3 SDRAM Quad 10/100/1000 Ethernet and three serial ports This board supports front and rear I/O. Access to rear I/O is available with a rear transition module (RTM).
Functional Description Figure 4-1 CPCI-6200 Block Diagram DDR 3 SDRAM SO-DIMM Socket (upto 2GB) DDR2/3 MC LBC DUART DUART Flash A 128 MB Dual Core 8572 Processor RTC M41 T83 TSEC4 COM2 MRAM 512KB I2C I 2C TSEC3 Flash B 4 – 8 GB User EEPROM 512Kb TSEC2 TSEC1 2 IC CPLD Timer/Reg PCIe IC x4 PCIe Expansion x1 TL16C2550 DUART x4 E2P Tsi384 SRAM 64K x 16 VPD EEPROM 64Kb PCIe x4 2 Renesas H8S IPMI DDR 3 SDRAM SO-DIMM Socket (upto 2GB) DDR2/3 MC x4 PCIe Switch x4 E2P Tsi384 PMC1 I
Functional Description 4.2 MPC8572 Integrated Processor TheCPCI-6200 supports the MPC8572 (dual e500 core) processor. The MPC8572 is an integrated processor with built-in DDR2/3 memory controllers (it supports two sides, up to four banks per side), PCI Express interfaces, four 10/100/1000 Ethernet fast ports, dual universal asynchronous receiver and transmitter (DUART), I2C controller, local bus interface, etc. The processor is configured to operate at 1.33 or 1.
Functional Description 4.3.4 I2C Bus 3 Bus 3 is connected between the IPMI controller and the following onboard I2C devices: 4.3.
Functional Description DDR3 memory is implemented using external SO-UDIMM, unbuffered, ECC-supported modules. 4.5 Timers The timing functions are provided by eight 32-bit timers that are integrated into the processor. These timers are clocked by the real-time clock (RTC) input, which is driven by a 1 MHz clock. There are also four independent 32-bit timers in a programmable logic device (PLD). The clock source for the four 32-bit timers in the PLD is derived from 25 MHz.
Functional Description A hardware flash bank write protect switch is provided on the CPCI-6200 to enable write protection of the NOR flash. Regardless of the state of the software flash write protect bit in the NOR Flash Control/Status register, write protection is enabled when this switch is ON. When this switch is OFF, write protection is controlled by the state of the software flash write protect bits and can only be disabled by clearing this bit in the NOR FLASH Control/Status register.
Functional Description Figure 4-3 4.7.2 Boot Block B MRAM (Magnetoresistive Random Access Memory) This board includes a 512 KB MRAM device that is connected to the processor's local bus. This memory device provides a non-volatile memory that has unlimited writes, fast access, and long term data retention without power. The MRAM is organized as 256 K by 16. 4.7.3 Control and Timers PLD The CPCI-6200 control and timers PLD resides on the local bus.
Functional Description 4.7.4 Serial COM Ports This board supports four serial ports. Two serial ports, COM1 and COM2, are provided through the built-in DUART interface of the processor. The remaining two ports, COM3 and COM4, are provided by TL16C2550 on the local bus. COM1 is routed to the front panel. COM2 is for internal use only. COM3 and COM4 are multiplexed through the serial MUX PLD and routed to the RTM through the J5 connector. 4.
Functional Description 4.9 PCI Express Port The processor is configured for two x4-lane PCI Express ports. PCIe 1 is connected to a six-port PEX8624 PCI Express switch. PCIe 2 is connected to a PCI Express expansion connector. Port 0 of PEX8624 is configured as an upstream port while the rest is configured as downstream ports. Each downstream port is connected to a PCI/PCI-X bridge. Each PCI Express lane is capable of supporting a data rate of 2.5 Gb/s.
Functional Description 4.10 PCI/PCI-X Bus Four separate PCI/PCI-X bus segments are implemented. These segments are connected to the processor through PCI Express bridges and a PCI Express switch. PCI-X bus 1 and PCI-X bus 2 connect to PMC site 1 and PMC site 2, respectively, using a Tsi384 bridge. Both buses are configured dynamically to operate in 25/33/66 MHz PCI or 100/133 MHz PCI-X mode depending on the PMC installed.
Functional Description 4.10.3 USB (PCI Bus 4) The USB 2.0 host controller (NEC uPD720101) provides USB ports with integrated transceivers for connectivity with any USB-compliant device or hub. USB channel 1 is routed to a single USB connector located on the front panel. DC power to the front panel USB port is supplied via a USB power switch. This power switch provides soft-start, current limiting, over current detection, and power enable for port 1. 4.10.
Functional Description 4.11.1 System Controller Mode In this mode, PCI6466 is configured in universal transparent mode. The red lines indicate active signals, while the gray lines indicate inactive signals. Figure 4-5 System Controller Mode 4.11.2 Peripheral Mode In this mode, PCI6466 is configured in universal non-transparent mode.
Functional Description The red lines indicate active signals, while the gray lines indicate inactive signals. Figure 4-6 Peripheral Mode 4.11.3 Stand Alone Mode In this mode, PCI6466 is configured in non-transparent mode.
Functional Description The red lines indicate active signals, while the gray lines indicate inactive signals. Figure 4-7 4.12 Stand Alone Mode PCI Express Expansion CPCI-6200 provides an additional module capability through the a 76-pin stacking connector. This connector is connected to the second PCI Express port on the processor.
Functional Description 4.13 System Interrupts CPCI-6200 provides several sources of interrupts that are handled by the processor. The processor supports 12 external interrupts. Interrupts coming through PCI Express switch (PEX8624) are routed to the first four interrupts (IRQ0 — IRQ3). Interrupts coming through the PCI Express expansion interface are routed to the next four interrupts (IRQ4-IRQ7). The remaining processor interrupts (IRQ8-IRQ11) are connected to LBPC CPLD interrupt sources.
Functional Description 4.14 Clock Distribution The clock function generates and distributes all of the clocks that are required for system operation. The PCI Express clocks are generated using an eight-output differential clock driver. The PCI/PCI-X bus clocks are generated by the bridge chips from the PCI Express clock. Additional clocks required by individual devices are generated near the devices using individual oscillators.
Functional Description 4.15 MPC8572 System Clock An oscillator drives the MPC8572 system clock. The following table details the clock frequencies for various processor configurations. Table 4-2 System Clock Frequencies 4.16 Clock/CPU Configuration 1.33 GHz CPU Blade 1.5 GHz CPU Blade SYSCLK (a) 66.67 MHz 100 MHz CCB (Platform) (b) 533 MHz 600 MHz Core 0/1 (c) 1.33 GHz 1.5 GHz DDRCLK (d) 66.66 MHz 66.
Functional Description Table 4-3 Reset Sources (continued) SW_RST Reset Source WD_EN SYS_RST 1 PB_RST_MASK LRO SW System Slot Function Abort/Reset Switch, RTC, IPMI, COP HRESET X X X X ON YES Note 1 X X X X OFF YES Note 2 X X X X ON NO Note 1 X X X X OFF NO Note 2 0 X 1 0 X YES Note 1 0 X 1 1 X YES Note 2 0 X 1 0 X NO Note 1 0 X 1 1 X NO Note 2 Watch Dog Local 1 0 0 X X X Note 2 Watch Dog System 1 1 0 X X X Note 1 CPU X X X
Functional Description Table 4-4 Reset Functions (continued) Note Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Reset Type System Wide Local Reset CPU SRESET CPU TRESET HSC Reset IPMI Reset CPU, TRESET NO NO NO YES NO NO PCI / PCI-X YES YES NO NO NO NO PHYs, COMs YES YES NO NO NO NO USB, Flash, CPLDs YES YES NO NO NO NO HSC Power NO NO NO NO YES NO IPMI NO NO NO NO NO YES PCI Bridge Primary YES YES NO NO NO NO PCI Bridge Secondary YES NO NO NO
Functional Description 4.16.2 Reset Timing Different devices have different reset timing requirements. CPCI-6200 uses a Reset Control PLD to meet their requirements.
Functional Description Table 4-5 Reset Timing Requirements (continued) Device Reset Signal Source of Reset Minimum Reset Time Actual Reset Time USB3 PCI4_RST_N Tsi381 1 ms 1.35 ms CPCI Backplane Reset3 PCI_BP_RST_N CPCI CPLD 1 ms 1.35 ms Flash A1 FRESET_N Reset CPLD 500 ns 125 μs 1. With MotLoad reset command 2. PCI Specification 4.17 RTC Battery The CPCI-6200 provides onboard battery clips for holding a coin cell type battery.
Functional Description The controller operates at 32 MHz clock frequency derived from 7.37 MHz external oscillator. An external SRAM is also added to increase the size of total SRAM available to IPMI firmware. IPMI firmware resides in internal flash memory. A serial port and I2C bus is connected between IPMI controller and processor for inter-communication. You can set the IPMI controller to function as a baseboard management controller (BMC) or a peripheral management (PM) controller.
Functional Description 4.19 Programmable Devices The CPCI-6200 uses many programmable devices that include Boot Flash, CPLDs and SROMs. The following table shows the all programmable devices, their functions and programming methods.
Functional Description Table 4-6 Programming Devices (continued) Reference Designator Description Function Pgm Method Remark U84 EEPROM 512K, 8P SOIC IPMI, SEL Customer Software For customer use only U12 Microcontroller, TQFP144 IPMI Controller ICT or through P3 header U83 EEPROM 512K, 8P SOIC IPMI FRU and SDR ICT or through P3 header 0 to 1800 is address for FRU data; above 1800 is SDR data 4.19.1 Local Bus Control CPLD This connects to the local bus controller of the processor.
Chapter 5 MOTLoad Firmware 5.1 Overview This chapter describes the basic features of the MOTLoad firmware product. It is designed by Emerson as the next generation initialization, debugger and diagnostic tool for highperformance embedded board products. In addition to an overview of the product, this chapter includes a list of standard MOTLoad commands and the default Compact PCI settings that you can change, as allowed by the firmware. 5.
MOTLoad Firmware 5.4 MOTLoad Commands CPCI-6200 supports two types of commands (applications): utilities and tests. Both types of commands are invoked from the CPCI-6200 command line in a similar fashion. Beyond that, CPCI-6200 utilities and CPCI-6200 tests are distinctly different. 5.5 MOTLoad Utility Applications The definition of a MOTLoad utility application is very broad. Simply stated, it is considered a MOTLoad command if it is not a MOTLoad test.
MOTLoad Firmware All devices that are available to MOTLoad for validation/verification testing are represented by a unique device path string. Most MOTLoad tests require the operator to specify a test device at the MOTLoad command line when invoking the test. A listing of all device path strings can be displayed through the devShow command. If an SBC device does not have a device path string, it is not supported by MOTLoad and cannot be directly tested.
MOTLoad Firmware Example: CPCI6200> If an invalid MOTLoad command is entered at the MOTLoad command line prompt, MOTLoad displays a message that the command was not found. Example: CPCI6200> mytest "mytest" not found CPCI6200> If the user enters a partial MOTLoad command string that can be resolved to a unique valid MOTLoad command and presses the carriage-return key, the command will be executed as if the entire command string had been entered.
MOTLoad Firmware CPCI6200> te "te" ambiguous CPCI6200> 5.7.2 Command Line Help Each MOTLoad firmware package has an extensive, product-specific help facility that can be accessed through the help command. The user can enter help at the MOTLoad command line to display a complete listing of all available tests and utilities.
MOTLoad Firmware The argument/option identifier character is always preceded by a hyphen (“-”) character. Options are identified by a single character. Option arguments immediately follow (no spaces) the option. All commands, command options, device tree strings, etc., are case sensitive. Example: CPCI6200> flashProgram -d/dev/flash0 -n00100000 For more information on MOTLoad operation and function, refer to the MOTLoad Firmware Package User’s Manual. 5.
MOTLoad Firmware Table 5-1 MOTLoad Commands (continued) Command Description bsb bsh bsw Block Search Byte/Halfword/Word bvb bvh bvw Block Verify Byte/Halfword/Word cdDir ISO9660 File System Directory Listing cdGet ISO9660 File System File Load clear Clear the Specified Status/History Table(s) cm Turns on Concurrent Mode csb Checksum Byte/Halfword/Word , csh , csw devShow Display (Show) Device/Node Table diskBoot Disk Boot (Direct-Access Mass-Storage Device) downLoad Down Load S-Record
MOTLoad Firmware Table 5-1 MOTLoad Commands (continued) 102 Command Description gevDump Global Environment Variable(s) Dump (NVRAM Header + Data) gevEdit Global Environment Variable Edit gevInit Global Environment Variable Area Initialize (NVRAM Header) gevList Global Environment Variable Labels (Names) Listing gevShow Global Environment Variable Show gn Go Execute User-Program to Next Instruction go Go Execute User-Program gt Go Execute User-Program to Temporary Break-Point hbd Displa
MOTLoad Firmware Table 5-1 MOTLoad Commands (continued) Command Description pciDump Dump PCI Device Configuration Header Register pciShow Display PCI Device Configuration Header Register pciSpace Display PCI Device Address Space Allocation ping Ping Network Host portSet Port Set portShow Display Port Device Configuration Data rd User Program Register Display reset Reset System rs User Program Register Set set Set Date and Time sromRead SROM Read sromWrite SROM Write sta Symbol Ta
MOTLoad Firmware Table 5-1 MOTLoad Commands (continued) 104 Command Description testRamCodeCopy RAM Code Copy and Execute testRamEccMonitor Monitor for ECC Errors testRamMarch RAM March testRamPatterns RAM Patterns testRamPerm RAM Permutations testRamQuick RAM Quick testRamRandom RAM Random Data Patterns testRtcAlarm RTC Alarm testRtcReset RTC Reset testRtcRollOver RTC Rollover testRtcTick RTC Tick testSerialExtLoop Serial External Loopback testSeriallntLoop Serial Internal Loo
MOTLoad Firmware Table 5-1 MOTLoad Commands (continued) Command Description vmeCfg Manages user specified VME configuration parameters vpdDisplay VPD Display vpdEdit VPD Edit waitProbe Wait for I/O Probe to Complete Note: Due to the difference in endianness of the board, the sromWrite command automatically swaps bytes as these are written into memory. The sromRead command accesses the actual memory contents and does not swap bytes as it reads.
MOTLoad Firmware 106 CPCI-6200 Installation and Use (6806800J66C)
Chapter 6 Control via IPMI 6.1 Standard IPMI Commands The IPMC is fully compliant to the Intelligent Platform Management Interface v.1.5. This section provides information on which IPMI commands are supported. 6.1.1 Global IPMI Commands The IPMC supports the following global IPMI commands. Table 6-1 Supported Global IPMI Commands 6.1.2 Command NetFn (Request/Response) CMD Comments Get Device ID 0x06/0x07 0x01 - Master Write-Read 0x06/0x07 0x52 Only for accessing private I2C buses.
Control via IPMI 6.1.3 IPMI Messaging Commands The IPMC supports the following IPMI messaging commands. Table 6-3 Supported Watchdog Commands 6.1.
Control via IPMI 6.1.5 SDR Repository Commands The IPMC supports the following SDR repository commands. Table 6-5 Supported SDR Repository Commands 6.1.
Control via IPMI 6.1.7 Sensor Device Commands The IPMC supports the following sensor device commands.
Control via IPMI 6.1.8 Chassis Device Commands The IPMC supports the following chassis device commands. Table 6-8 Supported Chassis Device Commands 6.2 Command NetFn (Request/Response) CMD Get Chassis Capabilities 0x00/0x01 0x00 Get Chassis Status 0x00/0x01 0x01 Chassis Control 0x00/0x01 0x02 Get System Restart Cause 0x00/0x01 0x07 Set System Boot Options 0x00/0x01 0x08 Get System Boot Options 0x00/0x01 0x09 PICMG 2.
Control via IPMI 6.3 Emerson Specific Commands The Emerson IPMC supports several commands which are not defined in the IPMI or PICMG 2.9 specification but are introduced by Emerson: Firmware upgrade and status change commands. 6.3.1 Before sending any of these commands, the shelf management software must check whether the receiving IPMI controller is an Emerson IPMI controller, that means IPMC, by using the IPMI command 'Get Device ID'.
Control via IPMI The following table shows the firmware upgrade commands together with their network function and command code. Table 6-10 Firmware Upgrade Commands 6.3.1.
Control via IPMI 6.3.1.2 Continue Firmware Upgrade The Continue Firmware Upgrade command writes a part of the firmware image to the target IPMC. It also checks file integrity and makes the target IPMC leave the firmware upgrade mode if an error occurs. If an error occurs, the whole firmware upgrade sequence must be repeated beginning from the Start Firmware Upgrade command and the whole firmware upgrade image must be retransmitted. 6.3.1.2.
Control via IPMI 6.3.1.3.1 Request Data The following table lists the request data applicable to the Finish Firmware Upgrade command. Table 6-14 Request Data of Finish Firmware Upgrade Byte Data Field 1..23 None 6.3.1.3.2 Response Data The following table lists the response data applicable to the Finish Firmware Upgrade command. Table 6-15 Response Data of Finish Firmware Upgrade Byte Data Field 1 Completion Code 0: Command executed successfully 0x01..0xFF: Error 6.3.
Control via IPMI 6.3.2.1 BMC/PM Change Role The BMC/PM Change Role command switches between the role of a BMC/PM. As a result its I2C addresses on IPMB0 and IPMB1 are configured to 0x20. Any message addressed to the system management software are passed to the host interface. The system management software must ensure that only one BMC is in the system. SDR will be updated to reflect I2C address changes. The role of BMC/PM can also be defined via the onboard DIP switches.
Control via IPMI 6.3.2.2.1 Request Data The following table lists the request data applicable to the Get Geographical Address command. Table 6-19 Request Data of Get Geographical Address Byte Data Field - - 6.3.2.2.2 Response Data The following table lists the response data applicable to the Get Geographical Address command.
Control via IPMI 6.4 FRU Information The CPCI-6200 provides the following FRU information in FRU ID 0. Table 6-21 FRU Information CPCI-6200 Area Description Internal use area Not used Board info area Product info area Multi record area 6.5 Value Access Manufacturing date/time According to Intel's Platform Management FRU information Storage Definition v1.
Control via IPMI Table 6-22 IPMI Sensors Overview (continued) Sensor Number Detailed SDR Description Emerson-specific Discrete Digital 0x98 See Table 6-24 on page 121 CPCI Signal Emerson-specific Discrete Digital 0x83 See Table 6-25 on page 121 CPU Status Processor 0x87 See Table 6-26 on page 122 Critical IRQ Emerson-specific Discrete Digital 0x82 See Table 6-27 on page 123 Ejector Switch Emerson-specific Discrete Digital 0x80 See Table 6-28 on page 124 ADT7461Temp Temperature 0x09
Control via IPMI The AggregateT sensor reads all on-board temperature sensors and indicates whether a threshold of any evaluated sensor is asserted or not. The following table shows the main sensor data record field values of the AggregateT sensor.
Control via IPMI The AggregateV sensor reads all on-board voltage sensors and indicates whether a threshold of any evaluated sensor is asserted or not. The following table shows the main sensor data record field values of the AggregateV sensor.
Control via IPMI Table 6-25 CPCI Signal Sensor (continued) Feature Raw Value Description Entity ID 0x07 - Sensor Type 0xD2 Emerson-specific Discrete Digital Event/Reading Type 0x6F Discrete (sensor-specific) Assertion Event Mask(Byte 15) 0x03 - Assertion Event Mask(Byte 16) 0x00 - Deassertion Event Mask(Byte 17) 0x03 - Deassertion Event Mask(Byte 18) 0x00 - Threshold Mask(Byte 19) 0x03 - Threshold Mask(Byte 20) 0x00 - Base Unit 0x00 (unspecified) Rearm mode 0x01 Auto Hys
Control via IPMI Table 6-26 CPU Status Sensor (continued) Feature Raw Value Description - Event Offset: 1 Thermal Trip Deassertion Event Mask(Byte 17) 0x02 - Deassertion Event Mask(Byte 18) 0x00 - Deassertion Events - - - Event Offset: 1 Thermal Trip Threshold Mask(Byte 19) 0xFF - Threshold Mask(Byte 20) 0x07 - Base Unit 0x00 (unspecified) Rearm mode 0x01 Auto Hysteresis Support 0x00 No Hysteresis or unspecified Threshold Access Support 0x00 No Tresholds Event Message Co
Control via IPMI Table 6-27 Critical IRQ Sensor (continued) Feature Raw Value Description Threshold Mask(Byte 20) 0x00 - Base Unit 0x00 (unspecified) Rearm mode 0x01 Auto Hysteresis Support 0x00 No Hysteresis or unspecified Threshold Access Support 0x00 No Tresholds Event Message Control 0x00 Per Threshold / Discrete State Reading Definition - - Feature Raw Value Description Sensor Name Ejector Switch - Sensor LUN 0x00 - Sensor Number 0x80 - Entity ID 0x07 - Sensor Ty
Control via IPMI Table 6-28 Ejector Switch Sensor (continued) Feature Raw Value Description Reading Definition - - Table 6-29 Max1617Temp Sensor Feature Raw Value Description Sensor Name ADT7461Temp - Sensor LUN 0x00 - Sensor Number 0x09 - Entity ID 0x03 - Sensor Type 0x01 Temperature Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A -
Control via IPMI Table 6-29 Max1617Temp Sensor (continued) Feature Raw Value Description Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading Table 6-30 CoreTemp Sensor 126 Feature Raw Value Description Sensor Name CoreTemp - Sensor LUN 0x00 - Sensor Number 0x0A Entity ID 0x03 Sensor Type 0x01 Temperature Event/Reading Type 0x01 Threshold Assertion Event Mask (Byte 15) 0x95 - Assertion Event Mask (Byte 16) 0
Control via IPMI Table 6-30 CoreTemp Sensor (continued) Feature Raw Value Description Threshold Access Support 0x03 Readable and Setable Event Message Control 0x00 Per Threshold/Discrete State Reading Definition Analog reading byte Analog sensor reading Table 6-31 SEL Fullness Sensor Feature Raw Value Description Sensor Name SEL Fullness - Sensor LUN 0x00 - Sensor Number 0x64 - Entity ID 0x06 - Sensor Type 0xD0 OEM Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte
Control via IPMI Table 6-31 SEL Fullness Sensor (continued) Feature Raw Value Description Hysteresis Support 0x02 Readable and Setable Threshold Access Support 0x02 Readable and Setable Event Message Control 0x00 Per Threshold / Discrete State Reading Definition Analog reading byte Analog sensor reading Table 6-32 Signal Status Sensor 128 Feature Raw Value Description Sensor Name Signal Status - Sensor LUN 0x00 - Sensor Number 0x85 - Entity ID 0x07 - Sensor Type 0xD2 Emers
Control via IPMI Table 6-33 VCC1_2 Sensor Feature Raw Value Description Sensor Name VCC1_2 - Sensor LUN 0x00 - Sensor Number 0x08 - Entity ID 0x07 - Sensor Type 0x02 Voltage Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A - Threshold Mask(Byte 19) 0x3F - Threshold Mask(Byte 20) 0x3F - Base Unit 0x04 Volt Nominal Reading 0x7C 1.
Control via IPMI Table 6-34 VCC1_5 Sensor 130 Feature Raw Value Description Sensor Name VCC1_5 - Sensor LUN 0x00 - Sensor Number 0x06 - Entity ID 0x07 - Sensor Type 0x02 Voltage Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A - Threshold Mask(Byte 19) 0x3F - Threshold Mask(Byte 20) 0x3F - Base Unit 0x04 Volt Nominal Reading 0x9B
Control via IPMI Table 6-35 VCC1_8 Sensor Feature Raw Value Description Sensor Name VCC1_8 - Sensor LUN 0x00 - Sensor Number 0x01 - Entity ID 0x07 - Sensor Type 0x02 Voltage Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A - Threshold Mask(Byte 19) 0x3F - Threshold Mask(Byte 20) 0x3F - Base Unit 0x04 Volt Nominal Reading 0xB8 1.
Control via IPMI Table 6-36 VCC3_3 Sensor 132 Feature Raw Value Description Sensor Name VCC3_3 - Sensor LUN 0x00 - Sensor Number 0x02 - Entity ID 0x07 - Sensor Type 0x02 Voltage Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A - Threshold Mask(Byte 19) 0x3F - Threshold Mask(Byte 20) 0x3F - Base Unit 0x04 Volt Nominal Reading 0xA4
Control via IPMI Table 6-37 VCC2_5 Sensor Feature Raw Value Description Sensor Name VCC2_5 - Sensor LUN 0x00 - Sensor Number 0x05 - Entity ID 0x07 - Sensor Type 0x02 Voltage Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A - Threshold Mask(Byte 19) 0x3F - Threshold Mask(Byte 20) 0x3F - Base Unit 0x04 Volt Nominal Reading 0xB8 2.
Control via IPMI Table 6-38 VCC5_0 Sensor 134 Feature Raw Value Description Sensor Name VCC5_0 - Sensor LUN 0x00 - Sensor Number 0x03 - Entity ID 0x07 - Sensor Type 0x02 Voltage Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A - Threshold Mask(Byte 19) 0x3F - Threshold Mask(Byte 20) 0x3F - Base Unit 0x04 Volt Nominal Reading 0xAC
Control via IPMI Table 6-39 VCC1_0 Sensor Feature Raw Value Description Sensor Name VCC1_0 - Sensor LUN 0x00 - Sensor Number 0x07 - Entity ID 0x07 - Sensor Type 0x02 Voltage Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A - Threshold Mask(Byte 19) 0x3F - Threshold Mask(Byte 20) 0x3F - Base Unit 0x04 Volt Nominal Reading 0x66 1.
Control via IPMI Table 6-40 VPCore Sensor 136 Feature Raw Value Description Sensor Name VPCore - Sensor LUN 0x00 - Sensor Number 0x04 - Entity ID 0x03 - Sensor Type 0x02 Voltage Event/Reading Type 0x01 Threshold Assertion Event Mask(Byte 15) 0x95 - Assertion Event Mask(Byte 16) 0x7A - Deassertion Event Mask(Byte 17) 0x95 - Deassertion Event Mask(Byte 18) 0x7A - Threshold Mask(Byte 19) 0x3F - Threshold Mask(Byte 20) 0x3F - Base Unit 0x04 Volt Nominal Reading 0x71
Chapter 7 Memory Maps and Addresses 7.1 Default Processor Memory Map The following table describes a default memory map from the point of view of the processor after a processor reset. Note that the e500 core only provides one default TLB entry to access boot code and it allows for accesses within the highest 4 KB of memory. In order to access the full 8 MB of default boot space (and the 1 MB of CCSR space), additional TLB entries must be set up within the e500 core for mapping these regions.
Memory Maps and Addresses 7.2 CPCI-6200 Memory Map The following diagram and the succeeding table detail the physical memory map implemented by the MotLoad firmware. Figure 7-1 CPCI-6200 Memory Map Diagram 0x0_0000_0000 0x0_F200_0000 0x0_F200_FFFF 0x0_F201_0000 System Memory (3.
Memory Maps and Addresses Table 7-2 CPCI-6200 Address Memory Map (continued) Processor Address 7.
Memory Maps and Addresses 7.4 System I/O Memory Map System resources, including system control and status registers, external timers, flash, and DUART, are mapped to a 224 MB address range that is accessible from the CPCI-6200 local bus via the MPC8572 LBC. The memory map is defined in the following table including the LBC bank chip select used to decode the register.
Memory Maps and Addresses Table 7-4 System I/O Memory Map (continued) Address F200 00203 Definition LBC Bank/Chip Select Watchdog Timer Load 3 1 F200 0021 Reserved 3 F200 00221 Reserved 3 F200 00231 Reserved 3 F200 0024 Watchdog Timer Control 3 F200 00253 Watchdog Timer Resolution 3 F200 0026 Watchdog Timer Count (16 bits) 3 F200 0028—F200 002F1 Reserved 3 F200 00303 3 3 PLD Revision 3 1 Reserved 3 1 F200 0032 Reserved 3 F200 00331 F200 0031 Reserved 3 3 PLD Date
Memory Maps and Addresses Table 7-4 System I/O Memory Map (continued) Definition LBC Bank/Chip Select Reserved 5 F202 0020 External PLD Tick Timer 2 Control Register 5 F202 00242 External PLD Tick Timer 2 Compare Register 5 F202 00282 External PLD Tick Timer 2 Counter Register 5 F202 002C2 Reserved 5 F202 00302 External PLD Tick Timer 3 Control Register 5 F202 00342 External PLD Tick Timer 3 Compare Register 5 F202 00382 External PLD Tick Timer 3 Counter Register 5 F202 003C2 Rese
Memory Maps and Addresses 7.4.1 System Status Register This is a read-only register that provides general board status information. Table 7-5 System Status Register, 0xF200_0000 Bit Field Operation Reset 7 PWR12V_EN_STS R X 6 PWR_12P_STS R X 5 PWR_12N_STS R X 4 SW5 R X 3 SAFE_START R X 2 PEX_8624_ERROR R X 1 BD_TYPE R 10 0 Table 7-6 System Status Register Field Definition PWR12V_EN_STS PWR_12P_STS PWR_12N_STS SW5 12V Power Enable Status from Switch 1 12 V is enabled.
Memory Maps and Addresses Table 7-6 System Status Register Field Definition SAFE_START ENV Safe Start PEX_8624_ERROR BD_TYPE 7.4.2 1 Indicates that firmware should use the safe ENV settings 0 Indicates the ENV settings programmed in NVRAM should be used by the firmware PEX8624 Fatal Error 1 Indicates that the Fatal Error signal from the PEX8624 is active 0 Indicates no Fatal Error signal from the PEX8624 Board Type. These bits indicate the board type.
Memory Maps and Addresses Table 7-8 System Control Register Field Definition BRD_RST 7.4.3 Board Reset. These bits are used to force a hard reset of the board 101 Hard reset is generated. xxx Does not generate hard reset for any other bit patterns RSVD Reserved EEPROM_WP EEPROM Write Protect 1 Disable writes to the onboard EEPROM devices 0 Enable writes to the onboard EEPROM devices Front Panel LEDs Control and Status Register This register controls the front panel LEDs.
Memory Maps and Addresses Table 7-10 Front Panel LED Control/Status Register Field Definition RSVD Reserved USR1_LED User Green LED USR2_LED 7.4.4 1 Turn on the green LED. 0 Turn off green LED. User / Failure Indicating Yellow LED 1 Turn on the yellow LED 0 Turn off yellow LED. The board can also turn on the LED if a failure condition is detected.
Memory Maps and Addresses Table 7-12 NOR Flash Control/Status Register Field Definition MAP_SEL F_WP_SW F_WP_HW FBT_BLK_SEL FLASH_RDY Memory Map Select 1 Flash memory boot block A is selected and mapped to the highest address. See Figure 4-2 on page 76. 0 Flash memory map is controlled by the Flash Boot Block Select switch. Software flash bank write protect. This bit provides softwarecontrolled protection against inadvertent writes to the flash memory devices. 1 Flash is write-protected.
Memory Maps and Addresses 7.4.5 Interrupt Register 1 This register may be read by the system software to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt.
Memory Maps and Addresses 7.4.6 Interrupt Register 2 The CPCI CPLD, IPMI Controller, RTC, temperature sensor and abort switch interrupts are OR'd together. This register may be read by the system software to determine which device originated the interrupt.
Memory Maps and Addresses Table 7-16 Interrupt Register 2 Field Definition TEMP_INT ABORT 7.4.7 Interrupt fromTemperature Sensor 1 Temp sensor interrupt is asserted. 0 Temp sensor interrupt is not asserted. Abort Status. This bit reflects the current state of the onboard abort signal. This is a debounced version of the abort switch and may be used to determine the state of the abort switch. 1 Abort push button switch is pressed for less than three seconds.
Memory Maps and Addresses Table 7-18 Interrupt Mask Register (continued) CPCI_PLD_INT_MASK IPMI_INT_MASK RTC_INT_MASK TEMP_INT_MASK ABORT_MASK 7.4.8 Interrupt Mask for CPCI Control CPLD 1 CPCI CPLD interrupt generation is disabled. 0 CPCI CPLD is allowed to generate interrupt. IPMI Controller Interrupt Mask 1 IPMI interrupt generation is disabled. 0 IPMI is allowed to generate interrupt. RTC Interrupt Mask 1 RTC interrupt generation is disabled. 0 RTC is allowed to generate interrupt.
Memory Maps and Addresses Table 7-19 Presence Detect Register, 0xF200_0008 (continued) Bit Field Operation Reset 3 RTM_PRSNT R X 2 XEP R X 1 PMC2P R X 0 PMC1P R X Table 7-20 Presence Detect Register Field Definition RSVD Reserved ERDY2 EREADY2. Indicates the enumeration status of PrPMC module installed in PMC site 2 ERDY1 RTM_PRSNT XEP PMC2P 152 1 PrPMC module installed in PMC site 2 is ready for enumeration.1 0 PrPMC module is not ready for enumeration EREADY1.
Memory Maps and Addresses Table 7-20 Presence Detect Register Field Definition PMC1P PMC Module 1 Present 1 PMC module is installed at PMC site 1. 0 PMC module is not installed at PMC site 1. 1. If PrPMC module is not installed, this bit is always 1. 7.4.
Memory Maps and Addresses Table 7-22 NAND Flash Chip 1 Control Register Field Definition 0 WP RSVD ALE is not asserted when the device is accessed. Write Protect 1 WP is asserted when the device is accessed. 0 WP is not asserted when the device is accessed. Reserved 7.4.
Memory Maps and Addresses Table 7-24 NAND Flash Chip 1 Select Register Field Definition CE2 CE3 CE4 RSVD Chip Enable 2 1 CE2 is asserted when the device is accessed. 0 CE2 is not asserted when the device is accessed. Chip Enable 3 1 CE3 is asserted when the device is accessed. 0 CE3 is not asserted when the device is accessed. Chip Enable 1 1 CE4 is asserted when the device is accessed. 0 CE4 is not asserted when the device is accessed. Reserved 7.4.
Memory Maps and Addresses Table 7-26 NAND Flash Chip 1 Presence Register Field Definition C1P RSVD Chip 1 Present 1 Chip 1 is installed on the board. 0 Chip 1 is not installed on the board. Reserved 7.4.
Memory Maps and Addresses Table 7-28 NAND Flash Chip 1 Status Register Field Definition (continued) RB3 Ready/Busy 3 RB4 1 Device 3 is ready. 0 Device 3 is busy. Ready/Busy 4 RSVD 1 Device 4 is ready. 0 Device 4 is busy. Reserved 7.4.
Memory Maps and Addresses Table 7-30 NAND Flash Chip 2 Control Register Field Definition ALE WP RSVD Address Latch Enable 1 ALE is asserted when the device is accessed. 0 ALE is not asserted when the device is accessed. Write Protect 1 WP is asserted when the device is accessed. 0 WP is not asserted when the device is accessed. Reserved 7.4.
Memory Maps and Addresses Table 7-32 NAND Flash Chip 2 Select Register (continued) CE2 CE3 CE4 RSVD Chip Enable 2 1 CE2 is asserted when the device is accessed. 0 CE2 is not asserted when the device is accessed. Chip Enable 3 1 CE3 is asserted when the device is accessed. 0 CE3 is not asserted when the device is accessed. Chip Enable 4 1 CE4 is asserted when the device is accessed. 0 CE4 is not asserted when the device is accessed. Reserved 7.4.
Memory Maps and Addresses Table 7-34 NAND Flash Chip 2 Presence Register Field Definition RSVD 1 Chip 2 is installed on the board. 0 Chip 2 is not installed on the board. Reserved 7.4.
Memory Maps and Addresses Table 7-36 NAND Flash Chip 2 Status Register Field Definition (continued) RB3 RB4 RSVD Ready/Busy 3 1 Device 3 is ready. 0 Device 3 is busy. Ready/Busy 4 1 Device 4 is ready. 0 Device 4 is busy. Reserved 7.4.17 CPCI Control and Status Register This register controls CPCI functions.
Memory Maps and Addresses Table 7-38 CPCI Control/Status Register Field Definition (continued) BP_RST_MASK CPCI Backplane Reset Mask HS_LED_ON1 1 Disable backplane CPCI bus reset. 0 Enable backplane CPCI bus reset. Hot Swap (Blue) LED ON SA_MODE 1 Turn on Blue LED. 0 Don't turn on Blue LED. Stand alone mode SYS_EN_STS 1 Board operates in stand alone mode e.g. operate in non-system slot and without system slot board. 0 Board operates in normal mode.
Memory Maps and Addresses Table 7-39 Geographic Address Read Register, 0xF200_0019 (continued) Bit Field Operation Reset 1 RSVD R 0 0 RSVD R 0 Table 7-40 Geographic Address Read Register Field Definition GA[4:0] Geographic Address Bits from Backplane. The value will depend upon the chassis slot used for the board. RSVD Reserved 7.4.
Memory Maps and Addresses 7.4.20 Watchdog Timer Control Register Table 7-42 Watchdog Timer Control Register, 0xF200_0024 Bit Field Operation Reset 7 WDG_EN R/W 0 6 SYS_RST R/W 0 5 RSVD R 0 4 RSVD R 0 3 RSVD R 0 2 RSVD R 0 1 RSVD R 0 0 RSVD R 0 Table 7-43 Watchdog Timer Control Register Field Definition WDG_EN SYS_RST RSVD 164 Watch Dog Timer Enable 1 Watchdog timer is enabled. 0 Watchdog timer is disabled.
Memory Maps and Addresses 7.4.
Memory Maps and Addresses Table 7-45 Watchdog Timer Resolution Register (continued) WDG_RES Watchdog Timer Resolution 0000 2 μs 0001 4 μs 0010 8 μs 0011 16 μs 0100 32 μs 0101 64 μs 0110 128 μs 0111 256 μs 1000 512 μs 1001 1 ms (default) 1010 2 ms 1011 4 ms 1100 8 ms 1101 16 ms 1110 32 ms 1111 64 ms 7.4.22 Watchdog Timer Count Register Table 7-46 Watchdog Timer Counter Register, 0xF200_0026 Bit Field Operation Reset 15:0 WDG_COUNT R/W1 XX 1.
Memory Maps and Addresses WDG_COUNT–Count; These bits define the watchdog timer count value. When the watchdog counter is enabled or there is a write to the load register, the watchdog counter is set to the count value. When enabled, the watchdog counter will decrement at a rate defined by the resolution register. The counter will continue to decrement until it reaches zero or the software writes to the load register. If the counter reaches zero, a system or board level reset is generated. 7.4.
Memory Maps and Addresses 7.4.24 PLD Date Code Register This is a 32-bit register that contains the build date code of the timers/registers PLD.
Memory Maps and Addresses 7.4.26 Test Register 2 This is a second 32-bit test register that reads back the complement of the data in Test Register 1. Table 7-52 Test Register 2, 0xF200_003C Bit Field Operation Reset 31:0 TEST_2 R/W XX TEST_2–A read from this address will return the complement of the data pattern in Test Register 1. A write to this address will write the uncomplemented data to register TEST_1. 7.4.
Memory Maps and Addresses The prescaler provides the clock required by each of the four timers. The input clock to the prescaler is 25 MHz. The default value is set for $E7 which gives a 1 MHz reference clock for a 25 MHz input clock source. 7.4.27.
Memory Maps and Addresses Table 7-55 Tick Timer Control Field Definition (continued) EN_INT Enable Interrupt 1 Interrupt is enabled. 0 Interrupt is disabled. OVF Overflow bits. These bits are the output of the overflow counter. The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter. The overflow counter can be cleared by writing a 1 to the COVF bit. COVF Clear overflow bits. The overflow counter is cleared when a 1 is written to this bit.
Memory Maps and Addresses The Tick Timer Counter is compared to the Compare Register. When they are equal, the tick timer interrupt is asserted and the Overflow Counter is incremented. If the clear-on-compare mode is enabled, the counter is also cleared.
Memory Maps and Addresses 7.5 Interrupt Controller The CPCI-6200 uses the MPC8572 integrated programmable interrupt controller (PIC) to manage locally generated interrupts.The following table shows the external interrupting devices and interrupt assignments along with corresponding edge/levels and polarities.
Memory Maps and Addresses The following figure shows how PCI interrupts are mapped to processor interrupts.
Memory Maps and Addresses Table 7-59 I2C Bus Device Addressing Device Address 2 2 A2 A1 A0 Size I C Bus I C Bus Address (binary) (bytes) Function Bus 4 0xA0 000 N/A Reserved 0xA2 001 256 x 8 DDR3 memory bank 1 SPD1 0xA4 010 256 x 8 DDR3 memory bank 2 SPD1 0xA6 011 64K x 8 User configuration 1 0xA8 / 0xAA 100 512 x 8 RTM VPD (off-board configuration) 0xAC 110 64K x 8 User configuration 2 0xAE 111 8K x 8 VPD (on-board configuration) 0xD0 N/A N/A M41T83 real-time clock
Memory Maps and Addresses 7.7.1 PCI IDSEL and Interrupt Assignment Each PCI device has an associated address line connected via a resistor to its IDSEL pin for Configuration Space accesses. Refer to the MPC8572, Tsi384, Tsi381 and PEX8624 datasheets for details on generating configuration cycles on each of the PCI buses.
Memory Maps and Addresses 7.7.3 PCI Arbitration Assignments The integrated PCI/X arbiters internal to the Tsi381, Tsi384, and PCI6466 bridges provide PCI arbitration for the CPCI-6200.
Memory Maps and Addresses 178 CPCI-6200 Installation and Use (6806800J66C)
Appendix A A Replacing the Battery A.1 Battery Location For information on the battery’s functional description, see RTC Battery on page 91.
Replacing the Battery Product Damage Incorrect replacement of lithium batteries can result in a hazardous explosion. When exchanging the on-board lithium battery, make sure that the new and the old battery are exactly the same battery models. If the respective battery model is not available, contact your local Emerson sales representative for the availability of alternative officially approved battery models.
Appendix B B Related Documentation B.1 Emerson Network Power - Embedded Computing Documents The publications listed below are referenced in this manual. You can obtain electronic copies of the publications by contacting your local Emerson sales office. For documentation of released products, you can also visit http://www.emersonnetworkpower.com/embeddedcomputing. Navigate to Solution Services > Technical Documentation Search. Use the search field to look for the appropriate publication.
Related Documentation B.2 Manufacturer’s Publications For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. A source for the listed document is provided. Please note that, while these sources have been verified, the information is subject to change without notice.
Related Documentation Table B-2 Manufacturers’ Publications (continued) Company Document Title and Publication Number PLX Technology PCI6466 PC I-to-PCI Bus Bridge User Manual, Version 1.0, April, 2005 http://www.plxtech.com/ ExpressLane PEX 8624AA 5-Port/24-Lane Versatile PCI Express Switch Data Book, Version 0.92 STMicroelectronics M41T83 Serial Real-Time Clock, Rev 6, November 2007 http://www.st.com/stonline/ Texas Instruments TL16C2550, Dual UART with 16-Byte FIFO's, October 2006 http://www.
Related Documentation Table B-3 Related Specifications (continued) Source Document Title and Publication Number PCI Industrial Manufacturers Group (PICMG) CPCI Hot Swap Specification, PICMG 2.1 R 2.0 http://www.picmig.com CPCI System Management Specification, PICMG 2.9 R 1.0 CPCI Base Specification, PICMG 2.0 R 3.0 CPCI Packet Switching Backplane Specification, PICMG 2.16 R1.0 Universal Serial Bus Universal Serial Bus Specification, Revision 2.0 April 27, 2000 http://www.usb.
Safety Notes This section provides warnings that precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed during all phases of operation, service, and repair of this equipment. You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment.
Safety Notes EMC FCC Class A This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to Part 15 of the FCC Rules, EN55022. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment.
Safety Notes Operation Product Damage High humidity and condensation on surfaces cause short circuits. Do not operate the product outside the specified environmental limits. Make sure the product is completely dry and there is no moisture on any surface before applying power. Personal Injury or Death This product operates with dangerous voltages that can cause injury or death. Use extreme caution when handling, testing, and adjusting this equipment and its components.
Safety Notes Hot Swap Data Loss Removing the product with the blue LED still blinking causes data loss. Wait until the blue LED is permanently illuminated before removing the product. Data Loss Removing the RTM with the system power on and the blue LED on the front blade still flashing causes data loss. Before removing the RTM from a powered system, power down the slot and the front blade’s payload by opening the lower handle of the front blade and wait until the blue LED is permanently ON.
Sicherheitshinweise Dieses Kapitel enthält Hinweise, die potentiell gefährlichen Prozeduren innerhalb dieses Handbuchs vorrangestellt sind. Beachten Sie unbedingt in allen Phasen des Betriebs, der Wartung und der Reparatur des Systems die Anweisungen, die diesen Hinweisen enthalten sind. Sie sollten außerdem alle anderen Vorsichtsmaßnahmen treffen, die für den Betrieb des Systems innerhalb Ihrer Betriebsumgebung notwendig sind.
Sicherheitshinweise Emerson und unsere Zulieferer unternehmen größte Anstrengungen um sicherzustellen, dass sich Pins und Stecker von Boards vor dem Verlassen der Produktionsstätte in einwandfreiem Zustand befinden. Verbogene Pins, verursacht durch fehlerhafte Installation oder durch Installation von Boards mit beschädigten Steckern kann die durch Emerson gewährte Garantie für Boards und Backplanes erlöschen lassen.
Sicherheitshinweise Wenn dieses Produkt ohne Frontblende ausgeliefert wird oder wenn die Frontblende entfernt wird, muss Ihr System die notwendigenSchutzmechnismen gegen elektromagnetische interferenzen bereitstellen, um die Einhaltung der eletromagnetischen Verträglichkeit des Systems zu gewährleisten. Boardprodukte werden in einem repräsentativen System getestet, um zu zeigen, dass das Board den oben aufgeführten EMV-Richtlinien entspricht.
Sicherheitshinweise Batterie Datenverlust Wenn Sie einen anderen Batterietyp installieren als der, der bei Auslieferung des Produktes installiert war, kann Datenverlust die Folge sein, da die neu installierte Batterie für andere Umgebungsbedingungen oder eine andere Lebenszeit ausgelegt sein könnte. Verwenden Sie daher den gleichen Batterietyp, der bei Auslieferung des Produktes installiert war.
Index A abbreviations 15 accessories 26 installing 32 ordering 26 B baseboard features 21 installing 39 mechanical information 26 ordering 26 removing 41 size 26 battery replacing 179 board configuring 35 features 21 layout 45 ordering 26 removal 41 status indicators 67 C command line rules MOTLoad 99 compliances 24 configuring baseboard 35 board 35 CPCI-6200 35 connectors COM1 59 CPCI bus connector, J1 48 CPCI bus connector, J2 49 CPCI connector, J4 51 CPCI user I/O connector, J3 50 CPCI user I/O connec
Index L R list of commands MOTLoad 100 local bus interface 75 removing baseboard 41 board 41 CPCI-6200 41 single board computer 41 replacing battery 179 requirements environmental 30 operating 30 reset timing 90 M MOTLoad command characteristics 97 command line help 99 command line rules 99 command types 96 command versus test 96 described 95 how employed 95 interface 97 list of commands 100 memory requirements 95 prompt explained 97 test suites 97 tests described 96 O operation modes 81 ordering 26 b
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